src/mainboard/lenovo/t60/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  20  * MA 02110-1301 USA
  21  */
  22
  23 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <arch/io.h>
  28 #include <device/pci_def.h>
  29 #include <device/pnp_def.h>
  30 #include <cpu/x86/lapic.h>
  31 #include <lib.h>
  32 #include <arch/acpi.h>
  33 #include <cbmem.h>
  34 #include <timestamp.h>
  35 #include <pc80/mc146818rtc.h>
  36 #include <console/console.h>
  37 #include <cpu/x86/bist.h>
  38 #include "northbridge/intel/i945/i945.h"
  39 #include "northbridge/intel/i945/raminit.h"
  40 #include "southbridge/intel/i82801gx/i82801gx.h"
  41 #include "dock.h"
  42
  43 void setup_ich7_gpios(void)
  44 {
  45         printk(BIOS_DEBUG, " GPIOS...");
  46
  47         /* T60 GPIO:
  48             6: LEGACYIO#
  49             7: BDC_PRESENCE#
  50             8: H8_WAKE#
  51            10: MDI_DETECT
  52            12: H8SCI#
  53            14: CPUSB#
  54            15: CPPE#
  55            25: MDC_KILL#
  56            27: EXC_PWR_CTRL
  57            28: EXC_AUX_CTRL
  58            35: CLKREQ_SATA#
  59            36: PLANARID0
  60            37: PLANARID1
  61            38: PLANARID2
  62            39: PLANARID3
  63         */
  64         outl(0x1f48f7c2, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
  65         outl(0xe0e0ffc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
  66         outl(0xfbfefb7d, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
  67         /* Output Control Registers */
  68         outl(0x00040000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
  69         /* Input Control Registers */
  70         outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
  71         outl(0x000100f0, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
  72         outl(0x000000f1, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
  73         outl(0x000300a3, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL2 */
  74 }
  75
  76 static void ich7_enable_lpc(void)
  77 {
  78         // Enable Serial IRQ
  79         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
  80         // decode range
  81         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210);
  82         // decode range
  83         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d);
  84
  85         /* range 0x1600 - 0x167f */
  86         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);
  87         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c);
  88
  89         /* range 0x15e0 - 0x10ef */
  90         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1);
  91         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c);
  92
  93         /* range 0x1680 - 0x169f */
  94         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681);
  95         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c);
  96 }
  97
  98 static void early_superio_config(void)
  99 {
 100         int timeout = 100000;
 101         device_t dev = PNP_DEV(0x2e, 3);
 102
 103         pnp_write_config(dev, 0x29, 0xa0);
 104
 105         while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--)
 106                 udelay(1000);
 107
 108         /* Enable COM1 */
 109         pnp_set_logical_device(dev);
 110         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
 111         pnp_set_enable(dev, 1);
 112 }
 113
 114 static void rcba_config(void)
 115 {
 116         /* Set up virtual channel 0 */
 117         RCBA32(0x0014) = 0x80000001;
 118         RCBA32(0x001c) = 0x03128010;
 119
 120         /* Device 1f interrupt pin register */
 121         RCBA32(0x3100) = 0x00001230;
 122         RCBA32(0x3108) = 0x40004321;
 123
 124         /* PCIe Interrupts */
 125         RCBA32(0x310c) = 0x00004321;
 126         /* HD Audio Interrupt */
 127         RCBA32(0x3110) = 0x00000002;
 128
 129         /* dev irq route register */
 130         RCBA16(0x3140) = 0x1007;
 131         RCBA16(0x3142) = 0x0076;
 132         RCBA16(0x3144) = 0x3210;
 133         RCBA16(0x3146) = 0x7654;
 134         RCBA16(0x3148) = 0x0010;
 135
 136         /* Enable IOAPIC */
 137         RCBA8(0x31ff) = 0x03;
 138
 139         /* Enable upper 128bytes of CMOS */
 140         RCBA32(0x3400) = (1 << 2);
 141
 142         /* Disable unused devices */
 143         RCBA32(0x3418) = FD_PCIE6 | FD_PCIE5 | FD_INTLAN | FD_ACMOD | FD_ACAUD;
 144         RCBA32(0x3418) |= (1 << 0); // Required.
 145
 146         /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 147         RCBA32(0x1e84) = 0x00020001;
 148         RCBA32(0x1e80) = 0x0000fe01;
 149
 150         /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
 151         RCBA32(0x1e9c) = 0x000200f0;
 152         RCBA32(0x1e98) = 0x000c0801;
 153 }
 154
 155 static void early_ich7_init(void)
 156 {
 157         uint8_t reg8;
 158         uint32_t reg32;
 159
 160         // program secondary mlt XXX byte?
 161         pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 162
 163         // reset rtc power status
 164         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 165         reg8 &= ~(1 << 2);
 166         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 167
 168         // usb transient disconnect
 169         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 170         reg8 |= (3 << 0);
 171         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
 172
 173         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
 174         reg32 |= (1 << 29) | (1 << 17);
 175         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
 176
 177         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
 178         reg32 |= (1 << 31) | (1 << 27);
 179         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 180
 181         RCBA32(0x0088) = 0x0011d000;
 182         RCBA16(0x01fc) = 0x060f;
 183         RCBA32(0x01f4) = 0x86000040;
 184         RCBA32(0x0214) = 0x10030549;
 185         RCBA32(0x0218) = 0x00020504;
 186         RCBA8(0x0220) = 0xc5;
 187         reg32 = RCBA32(0x3410);
 188         reg32 |= (1 << 6);
 189         RCBA32(0x3410) = reg32;
 190         reg32 = RCBA32(0x3430);
 191         reg32 &= ~(3 << 0);
 192         reg32 |= (1 << 0);
 193         RCBA32(0x3430) = reg32;
 194         RCBA32(0x3418) |= (1 << 0);
 195         RCBA16(0x0200) = 0x2008;
 196         RCBA8(0x2027) = 0x0d;
 197         RCBA16(0x3e08) |= (1 << 7);
 198         RCBA16(0x3e48) |= (1 << 7);
 199         RCBA32(0x3e0e) |= (1 << 7);
 200         RCBA32(0x3e4e) |= (1 << 7);
 201
 202         // next step only on ich7m b0 and later:
 203         reg32 = RCBA32(0x2034);
 204         reg32 &= ~(0x0f << 16);
 205         reg32 |= (5 << 16);
 206         RCBA32(0x2034) = reg32;
 207 }
 208
 209 void main(unsigned long bist)
 210 {
 211         u32 reg32;
 212         int boot_mode = 0, dock_err;
 213         int cbmem_was_initted;
 214         const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
 215
 216
 217         timestamp_init(get_initial_timestamp());
 218         timestamp_add_now(TS_START_ROMSTAGE);
 219
 220         if (bist == 0)
 221                 enable_lapic();
 222
 223         /* Force PCIRST# */
 224         pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
 225         udelay(200 * 1000);
 226         pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
 227
 228         ich7_enable_lpc();
 229
 230         /* We want early GPIO setup, to be able to detect legacy I/O module */
 231         pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
 232         /* Enable GPIOs */
 233         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);
 234         setup_ich7_gpios();
 235
 236         dock_err = dlpc_init();
 237
 238         /* We prefer Legacy I/O module over docking */
 239         if (legacy_io_present()) {
 240                 legacy_io_init();
 241                 early_superio_config();
 242         } else if (!dock_err && dock_present()) {
 243                 dock_connect();
 244                 early_superio_config();
 245         }
 246
 247         /* Setup the console */
 248         console_init();
 249
 250         /* Halt if there was a built in self test failure */
 251         report_bist_failure(bist);
 252
 253         if (MCHBAR16(SSKPD) == 0xCAFE) {
 254                 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 255                 outb(0x6, 0xcf9);
 256                 while (1) asm("hlt");
 257         }
 258
 259         /* Perform some early chipset initialization required
 260          * before RAM initialization can work
 261          */
 262         i945_early_initialization();
 263
 264         /* Read PM1_CNT */
 265         reg32 = inl(DEFAULT_PMBASE + 0x04);
 266         printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 267         if (((reg32 >> 10) & 7) == 5) {
 268                 if (acpi_s3_resume_allowed()) {
 269                         printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 270                         boot_mode = 2;
 271                         /* Clear SLP_TYPE. This will break stage2 but
 272                          * we care for that when we get there.
 273                          */
 274                         outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 275                 } else {
 276                         printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 277                 }
 278         }
 279
 280         /* Enable SPD ROMs and DDR-II DRAM */
 281         enable_smbus();
 282
 283 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 284         dump_spd_registers();
 285 #endif
 286
 287         timestamp_add_now(TS_BEFORE_INITRAM);
 288         sdram_initialize(boot_mode, spd_addrmap);
 289         timestamp_add_now(TS_AFTER_INITRAM);
 290
 291         /* Perform some initialization that must run before stage2 */
 292         early_ich7_init();
 293
 294         /* This should probably go away. Until now it is required
 295          * and mainboard specific
 296          */
 297         rcba_config();
 298
 299         /* Chipset Errata! */
 300         fixup_i945_errata();
 301
 302         /* Initialize the internal PCIe links before we go into stage2 */
 303         i945_late_initialization();
 304
 305 #if !CONFIG_HAVE_ACPI_RESUME
 306 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 307 #if CONFIG_DEBUG_RAM_SETUP
 308         sdram_dump_mchbar_registers();
 309
 310         {
 311                 /* This will not work if TSEG is in place! */
 312                 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 313
 314                 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 315                 ram_check(0x00000000, 0x000a0000);
 316                 ram_check(0x00100000, tom);
 317         }
 318 #endif
 319 #endif
 320 #endif
 321
 322         MCHBAR16(SSKPD) = 0xCAFE;
 323
 324         cbmem_was_initted = !cbmem_recovery(boot_mode==2);
 325
 326 #if CONFIG_HAVE_ACPI_RESUME
 327         /* If there is no high memory area, we didn't boot before, so
 328          * this is not a resume. In that case we just create the cbmem toc.
 329          */
 330         if ((boot_mode == 2) && cbmem_was_initted) {
 331                 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 332
 333                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 334                  * through stage 2. We could keep stuff like stack and heap in high tables
 335                  * memory completely, but that's a wonderful clean up task for another
 336                  * day.
 337                  */
 338                 if (resume_backup_memory)
 339                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 340
 341                 /* Magic for S3 resume */
 342                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 343         }
 344 #endif
 345
 346         timestamp_add_now(TS_END_ROMSTAGE);
 347
 348 }