src/soc/intel/skylake/vr_config.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2015 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <device/pci_ids.h>
  18 #include <device/pci_ops.h>
  19 #include <fsp/api.h>
  20 #include <soc/ramstage.h>
  21 #include <soc/vr_config.h>
  22 #include <console/console.h>
  23 #include <intelblocks/cpulib.h>
  24
  25 /* Default values for domain configuration. PSI3 and PSI4 are disabled. */
  26 static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
  27         [VR_SYSTEM_AGENT] = {
  28                 .vr_config_enable = 1,
  29                 .psi1threshold = VR_CFG_AMP(20),
  30                 .psi2threshold = VR_CFG_AMP(4),
  31                 .psi3threshold = VR_CFG_AMP(1),
  32                 .psi3enable = 0,
  33                 .psi4enable = 0,
  34                 .imon_slope = 0x0,
  35                 .imon_offset = 0x0,
  36                 .icc_max = VR_CFG_AMP(7),
  37                 .voltage_limit = 1520,
  38         },
  39         [VR_IA_CORE] = {
  40                 .vr_config_enable = 1,
  41                 .psi1threshold = VR_CFG_AMP(20),
  42                 .psi2threshold = VR_CFG_AMP(5),
  43                 .psi3threshold = VR_CFG_AMP(1),
  44                 .psi3enable = 0,
  45                 .psi4enable = 0,
  46                 .imon_slope = 0x0,
  47                 .imon_offset = 0x0,
  48                 .icc_max = VR_CFG_AMP(34),
  49                 .voltage_limit = 1520,
  50         },
  51         [VR_GT_UNSLICED] = {
  52                 .vr_config_enable = 1,
  53                 .psi1threshold = VR_CFG_AMP(20),
  54                 .psi2threshold = VR_CFG_AMP(5),
  55                 .psi3threshold = VR_CFG_AMP(1),
  56                 .psi3enable = 0,
  57                 .psi4enable = 0,
  58                 .imon_slope = 0x0,
  59                 .imon_offset = 0x0,
  60                 .icc_max = VR_CFG_AMP(35),
  61                 .voltage_limit = 1520,
  62         },
  63         [VR_GT_SLICED] = {
  64                 .vr_config_enable = 1,
  65                 .psi1threshold = VR_CFG_AMP(20),
  66                 .psi2threshold = VR_CFG_AMP(5),
  67                 .psi3threshold = VR_CFG_AMP(1),
  68                 .psi3enable = 0,
  69                 .psi4enable = 0,
  70                 .imon_slope = 0x0,
  71                 .imon_offset = 0x0,
  72                 .icc_max = VR_CFG_AMP(35),
  73                 .voltage_limit = 1520,
  74         },
  75 };
  76
  77 static uint16_t get_sku_icc_max(int domain)
  78 {
  79         const uint16_t tdp = cpu_get_power_max();
  80
  81         static uint16_t mch_id = 0, igd_id = 0;
  82         if (!mch_id) {
  83                 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
  84                 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
  85         }
  86         if (!igd_id) {
  87                 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
  88                 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
  89         }
  90
  91         /*
  92          * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the
  93          * Iccmax is the same among KBL-Y but KBL-U/R.
  94          * Addendum for AML-Y #594883, IccMax for IA core is 28A.
  95          * KBL-S #335195, KBL-H #335190, SKL-S #332687, SKL-H #332986,
  96          * SKL-U/Y #332990
  97          *
  98          *   Platform             Segment           SA       IA      GT (GT/GTx)
  99          * ---------------------------------------------------------------------
 100          *   KBL/SKL-S            (95W) quad        11.1     100     45
 101          *   SKL-S                (80W) quad        11.1     82      45
 102          *   KBL/SKL-S            (65W) quad        11.1     79      45
 103          *   SKL-S                (45W) quad        11.1     70      0
 104          *   KBL/SKL-S            (35W) quad        11.1     66      35
 105          *   SKL-S                (25W) quad        11.1     55      35
 106          *
 107          *   KBL/SKL-S            (54W) dual        11.1     58      48
 108          *   KBL/SKL-S            (51W) dual        11.1     45      48
 109          *   KBL/SKL-S            (35W) dual        11.1     40      48
 110          *
 111          *   SKL-H + OPC          (65W) GT4 quad    8        74      105/24
 112          *   SKL-H + OPC          (45W) GT4 quad    8        74      94/20
 113          *   SKL-H + OPC          (35W) GT4 quad    8        66      94/20
 114          *
 115          *   SKL-H                (35W) GT2 dual    11.1     60      55
 116          *
 117          *   KBL/SKL-H            (45W) GT2 quad    11.1     68      55
 118          *   KBL-H                (18W) GT2 quad    6.6      60      55
 119          *
 120          *   SKL-U + OPC          (28W) GT3 dual    5.1      32      57/19
 121          *   SKL-U + OPC          (15W) GT3 dual    5.1      29      57/19
 122          *   SKL-U                (15W) GT2 dual    4.5      29      31
 123          *
 124          *   KBL-U/R + OPC        (28W) GT3 dual    5.1      32      57/19
 125          *   KBL-U/R + OPC        (15W) GT3 dual    5.1      32      57/19
 126          *
 127          *   KBL-U/R              (15W) GT2 quad    6        64      31
 128          *   KBL-U/R              (15W) GT1/2 dual  4.5      32      31
 129          *   KBL-U/R              (15W) GT2 quad    4.5      29      31
 130          *
 131          *   SKL/KBL-Y            (6W)              4.1      24      24
 132          *   SKL/KBL-Y            (4.5W)            4.1      24      24
 133          */
 134
 135         switch (mch_id) {
 136         case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */
 137         case PCI_DEVICE_ID_INTEL_KBL_ID_S: {
 138                 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 40, 48, 48);
 139                 if (tdp >= 54)
 140                         icc_max[VR_IA_CORE] = VR_CFG_AMP(58);
 141                 else if (tdp >= 51)
 142                         icc_max[VR_IA_CORE] = VR_CFG_AMP(45);
 143
 144                 return icc_max[domain];
 145         }
 146         case PCI_DEVICE_ID_INTEL_SKL_ID_S_4:  /* fallthrough */
 147         case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */
 148         case PCI_DEVICE_ID_INTEL_KBL_ID_DT: {
 149                 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 55, 45, 45);
 150                 if (tdp >= 91)
 151                         icc_max[VR_IA_CORE] = VR_CFG_AMP(100);
 152                 else if (tdp >= 80)
 153                         icc_max[VR_IA_CORE] = VR_CFG_AMP(82);
 154                 else if (tdp >= 65)
 155                         icc_max[VR_IA_CORE] = VR_CFG_AMP(79);
 156                 else if (tdp >= 45) {
 157                         icc_max[VR_IA_CORE] = VR_CFG_AMP(70);
 158                         icc_max[VR_GT_SLICED] = 0;
 159                         icc_max[VR_GT_UNSLICED] = 0;
 160                 } else if (tdp >= 25) {
 161                         if (tdp >= 35)
 162                                 icc_max[VR_IA_CORE] = VR_CFG_AMP(66);
 163
 164                         icc_max[VR_GT_SLICED] = VR_CFG_AMP(35);
 165                         icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(35);
 166                 }
 167
 168                 return icc_max[domain];
 169         }
 170         case PCI_DEVICE_ID_INTEL_SKL_ID_H_4: {
 171                 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(11.1, 60, 94, 20);
 172                 if (tdp >= 45) {
 173                         icc_max[VR_IA_CORE] = VR_CFG_AMP(74);
 174                         if (tdp >= 65) {
 175                                 icc_max[VR_GT_SLICED] = VR_CFG_AMP(105);
 176                                 icc_max[VR_GT_UNSLICED] = VR_CFG_AMP(24);
 177                         }
 178                 }
 179                 return icc_max[domain];
 180         }
 181         case PCI_DEVICE_ID_INTEL_SKL_ID_H_2:  /* fallthrough */
 182         case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */
 183         case PCI_DEVICE_ID_INTEL_KBL_ID_H: {
 184                 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(6.6, 60, 55, 55);
 185                 if (tdp >= 35) {
 186                         if (tdp >= 45)
 187                                 icc_max[VR_IA_CORE] = VR_CFG_AMP(68);
 188
 189                         icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1);
 190                 }
 191
 192                 return icc_max[domain];
 193         }
 194         case PCI_DEVICE_ID_INTEL_SKL_ID_U: {
 195                 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(5.1, 29, 57, 19);
 196                 if (tdp >= 28)
 197                         icc_max[VR_IA_CORE] = VR_CFG_AMP(32);
 198                 else if (igd_id != PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) {
 199                         const uint16_t icc_max_gt2[NUM_VR_DOMAINS] =
 200                                 VR_CFG_ALL_DOMAINS_ICC(4.5, 29, 31, 31);
 201
 202                         return icc_max_gt2[domain];
 203                 }
 204                 return icc_max[domain];
 205         }
 206         case PCI_DEVICE_ID_INTEL_KBL_U_R: {
 207                 const uint16_t icc_max[NUM_VR_DOMAINS] =
 208                                 VR_CFG_ALL_DOMAINS_ICC(6, 64, 31, 31);
 209                 return icc_max[domain];
 210         }
 211         case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */
 212         case PCI_DEVICE_ID_INTEL_KBL_ID_Y: {
 213                 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.1, 24, 24, 24);
 214
 215                 if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX)
 216                         icc_max[VR_IA_CORE] = VR_CFG_AMP(28);
 217
 218                 return icc_max[domain];
 219         }
 220         case PCI_DEVICE_ID_INTEL_KBL_ID_U: {
 221                 uint16_t icc_max[NUM_VR_DOMAINS] = VR_CFG_ALL_DOMAINS_ICC(4.5, 32, 31, 31);
 222
 223                 if ((igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) ||
 224                     (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2))
 225                         icc_max[VR_IA_CORE] = VR_CFG_AMP(29);
 226
 227                 return icc_max[domain];
 228         }
 229         default:
 230                 printk(BIOS_ERR, "ERROR: Unknown MCH (%u) in VR-config\n", mch_id);
 231         }
 232         return 0;
 233 }
 234
 235 static uint16_t get_sku_ac_dc_loadline(const int domain)
 236 {
 237         static uint16_t mch_id = 0, igd_id = 0;
 238         if (!mch_id) {
 239                 struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 240                 mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
 241         }
 242         if (!igd_id) {
 243                 struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
 244                 igd_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff;
 245         }
 246
 247         switch (mch_id) {
 248         case PCI_DEVICE_ID_INTEL_SKL_ID_S_2: /* fallthrough */
 249         case PCI_DEVICE_ID_INTEL_SKL_ID_S_4: /* fallthrough */
 250         case PCI_DEVICE_ID_INTEL_KBL_ID_S:   /* fallthrough */
 251         case PCI_DEVICE_ID_INTEL_KBL_ID_DT:  /* fallthrough */
 252         case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: {
 253                 /* SA Loadline is not specified */
 254                 const uint16_t loadline[NUM_VR_DOMAINS] =
 255                                 VR_CFG_ALL_DOMAINS_LOADLINE(0, 2.1, 3.1, 3.1);
 256                 return loadline[domain];
 257         }
 258         case PCI_DEVICE_ID_INTEL_SKL_ID_H_2:  /* fallthrough */
 259         case PCI_DEVICE_ID_INTEL_SKL_ID_H_EM: /* fallthrough */
 260         case PCI_DEVICE_ID_INTEL_SKL_ID_H_4:  /* fallthrough */
 261         case PCI_DEVICE_ID_INTEL_KBL_ID_H: {
 262                 const uint16_t loadline[NUM_VR_DOMAINS] =
 263                                 VR_CFG_ALL_DOMAINS_LOADLINE(10, 1.8, 2.65, 2.65);
 264
 265                 if (igd_id == PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM) {
 266                         const uint16_t loadline_gt4[NUM_VR_DOMAINS] =
 267                                         VR_CFG_ALL_DOMAINS_LOADLINE(6, 1.6, 1.4, 6);
 268                         return loadline_gt4[domain];
 269                 }
 270
 271                 return loadline[domain];
 272         }
 273         case PCI_DEVICE_ID_INTEL_SKL_ID_Y: /* fallthrough */
 274         case PCI_DEVICE_ID_INTEL_KBL_ID_Y: {
 275                 uint16_t loadline[NUM_VR_DOMAINS] =
 276                                 VR_CFG_ALL_DOMAINS_LOADLINE(18, 5.9, 5.7, 5.7);
 277
 278                 if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX)
 279                         loadline[VR_IA_CORE] = VR_CFG_MOHMS(4);
 280
 281                 return loadline[domain];
 282         }
 283         case PCI_DEVICE_ID_INTEL_SKL_ID_U: /* fallthrough */
 284         case PCI_DEVICE_ID_INTEL_KBL_U_R:  /* fallthrough */
 285         case PCI_DEVICE_ID_INTEL_KBL_ID_U: {
 286                 uint16_t loadline[NUM_VR_DOMAINS] =
 287                                 VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 3.1, 3.1);
 288
 289                 if ((igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_1) ||
 290                     (igd_id == PCI_DEVICE_ID_INTEL_SKL_GT3E_SULTM_2) ||
 291                     (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_1) ||
 292                     (igd_id == PCI_DEVICE_ID_INTEL_KBL_GT3E_SULTM_2)) {
 293                         loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(2);
 294                         loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6);
 295                 }
 296
 297                 return loadline[domain];
 298         }
 299         default:
 300                 printk(BIOS_ERR, "ERROR: Unknown MCH (%u) in VR-config\n", mch_id);
 301         }
 302         return 0;
 303 }
 304
 305 void fill_vr_domain_config(void *params,
 306                 int domain, const struct vr_config *chip_cfg)
 307 {
 308         FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
 309         const struct vr_config *cfg;
 310
 311         if (domain < 0 || domain >= NUM_VR_DOMAINS)
 312                 return;
 313
 314         /* Use device tree override if requested. */
 315         if (chip_cfg->vr_config_enable)
 316                 cfg = chip_cfg;
 317         else
 318                 cfg = &default_configs[domain];
 319
 320         vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
 321         vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
 322         vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
 323         vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
 324         vr_params->Psi3Enable[domain] = cfg->psi3enable;
 325         vr_params->Psi4Enable[domain] = cfg->psi4enable;
 326         vr_params->ImonSlope[domain] = cfg->imon_slope;
 327         vr_params->ImonOffset[domain] = cfg->imon_offset;
 328         /* If board provided non-zero value, use it. */
 329         if (cfg->icc_max)
 330                 vr_params->IccMax[domain] = cfg->icc_max;
 331         else
 332                 vr_params->IccMax[domain] = get_sku_icc_max(domain);
 333         vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
 334
 335         if (cfg->ac_loadline)
 336                 vr_params->AcLoadline[domain] = cfg->ac_loadline;
 337         else
 338                 vr_params->AcLoadline[domain] = get_sku_ac_dc_loadline(domain);
 339         if (cfg->dc_loadline)
 340                 vr_params->DcLoadline[domain] = cfg->dc_loadline;
 341         else
 342                 vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain);
 343 }