src/cpu/amd/family_10h-family_15h/model_10xxx_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <console/console.h>
  18 #include <cpu/x86/msr.h>
  19 #include <cpu/amd/mtrr.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22 #include <string.h>
  23 #include <cpu/x86/msr.h>
  24 #include <cpu/x86/smm.h>
  25 #include <cpu/x86/pae.h>
  26 #include <pc80/mc146818rtc.h>
  27 #include <cpu/x86/lapic.h>
  28 #include "northbridge/amd/amdfam10/amdfam10.h"
  29 #include <cpu/amd/model_10xxx_rev.h>
  30 #include <cpu/cpu.h>
  31 #include <cpu/x86/cache.h>
  32 #include <cpu/x86/mtrr.h>
  33 #include <cpu/amd/multicore.h>
  34 #include <cpu/amd/model_10xxx_msr.h>
  35
  36 #define MCI_STATUS 0x401
  37
  38 static inline uint8_t is_fam15h(void)
  39 {
  40         uint8_t fam15h = 0;
  41         uint32_t family;
  42
  43         family = cpuid_eax(0x80000001);
  44         family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
  45
  46         if (family >= 0x6f)
  47                 /* Family 15h or later */
  48                 fam15h = 1;
  49
  50         return fam15h;
  51 }
  52
  53 static inline uint8_t is_gt_rev_d(void)
  54 {
  55         uint8_t fam15h = 0;
  56         uint8_t rev_gte_d = 0;
  57         uint32_t family;
  58         uint32_t model;
  59
  60         family = model = cpuid_eax(0x80000001);
  61         model = ((model & 0xf0000) >> 12) | ((model & 0xf0) >> 4);
  62         family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
  63
  64         if (family >= 0x6f)
  65                 /* Family 15h or later */
  66                 fam15h = 1;
  67
  68         if ((model >= 0x8) || fam15h)
  69                 /* Revision D or later */
  70                 rev_gte_d = 1;
  71
  72         return rev_gte_d;
  73 }
  74
  75 static volatile uint8_t fam15h_startup_flags[MAX_NODES_SUPPORTED][MAX_CORES_SUPPORTED] = {{ 0 }};
  76
  77 static void model_10xxx_init(device_t dev)
  78 {
  79         u8 i;
  80         msr_t msr;
  81         struct node_core_id id;
  82 #if CONFIG_LOGICAL_CPUS
  83         u32 siblings;
  84 #endif
  85         uint8_t delay_start;
  86
  87         id = get_node_core_id(read_nb_cfg_54());        /* nb_cfg_54 can not be set */
  88         printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
  89
  90         if (is_fam15h())
  91                 delay_start = !!(id.coreid & 0x1);
  92         else
  93                 delay_start = 0;
  94
  95         /* Turn on caching if we haven't already */
  96         x86_enable_cache();
  97
  98         if (!delay_start) {
  99                 /* Initialize all variable MTRRs except the first pair.
 100                  * This prevents Linux from having to correct an inconsistent
 101                  * MTRR setup, which would crash Family 15h CPUs due to the
 102                  * compute unit structure sharing MTRR MSRs between AP cores.
 103                  */
 104                 msr.hi = 0x00000000;
 105                 msr.lo = 0x00000000;
 106
 107                 disable_cache();
 108
 109                 for (i = 0x2; i < 0x10; i++) {
 110                         wrmsr(0x00000200 | i, msr);
 111                 }
 112
 113                 enable_cache();
 114
 115                 /* Set up other MTRRs */
 116                 amd_setup_mtrrs();
 117         } else {
 118                 while (!fam15h_startup_flags[id.nodeid][id.coreid - 1]) {
 119                         /* Wait for CU first core startup */
 120                 }
 121         }
 122
 123         x86_mtrr_check();
 124
 125         disable_cache();
 126
 127         /* zero the machine check error status registers */
 128         msr.lo = 0;
 129         msr.hi = 0;
 130         for (i = 0; i < 5; i++) {
 131                 wrmsr(MCI_STATUS + (i * 4), msr);
 132         }
 133
 134         enable_cache();
 135
 136         /* Enable the local cpu apics */
 137         setup_lapic();
 138
 139         /* Set the processor name string */
 140         init_processor_name();
 141
 142 #if CONFIG_LOGICAL_CPUS
 143         siblings = cpuid_ecx(0x80000008) & 0xff;
 144
 145         if (siblings > 0) {
 146                 msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
 147                 msr.lo |= 1 << 28;
 148                 wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
 149
 150                 msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
 151                 msr.hi |= 1 << (33 - 32);
 152                 wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 153         }
 154         printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 155 #endif
 156
 157         /* Set bus unit configuration */
 158         if (is_fam15h()) {
 159                 uint32_t f5x80;
 160                 uint8_t enabled;
 161                 uint8_t compute_unit_count = 0;
 162                 f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80);
 163                 enabled = f5x80 & 0xf;
 164                 if (enabled == 0x1)
 165                         compute_unit_count = 1;
 166                 if (enabled == 0x3)
 167                         compute_unit_count = 2;
 168                 if (enabled == 0x7)
 169                         compute_unit_count = 3;
 170                 if (enabled == 0xf)
 171                         compute_unit_count = 4;
 172                 msr = rdmsr(BU_CFG2_MSR);
 173                 msr.lo &= ~(0x3 << 6);                          /* ThrottleNbInterface[1:0] */
 174                 msr.lo |= (((compute_unit_count - 1) & 0x3) << 6);
 175                 wrmsr(BU_CFG2_MSR, msr);
 176         } else {
 177                 uint32_t f0x60;
 178                 uint32_t f0x160;
 179                 uint8_t core_count = 0;
 180                 uint8_t node_count = 0;
 181                 f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60);
 182                 core_count = (f0x60 >> 16) & 0x1f;
 183                 node_count = ((f0x60 >> 4) & 0x7) + 1;
 184                 if (is_gt_rev_d()) {
 185                         f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160);
 186                         core_count |= ((f0x160 >> 16) & 0x7) << 5;
 187                 }
 188                 core_count++;
 189                 core_count /= node_count;
 190                 msr = rdmsr(BU_CFG2_MSR);
 191                 if (is_gt_rev_d()) {
 192                         msr.hi &= ~(0x3 << (36 - 32));                  /* ThrottleNbInterface[3:2] */
 193                         msr.hi |= ((((core_count - 1) >> 2) & 0x3) << (36 - 32));
 194                 }
 195                 msr.lo &= ~(0x3 << 6);                          /* ThrottleNbInterface[1:0] */
 196                 msr.lo |= (((core_count - 1) & 0x3) << 6);
 197                 msr.lo &= ~(0x1 << 24);                         /* WcPlusDis = 0 */
 198                 wrmsr(BU_CFG2_MSR, msr);
 199         }
 200
 201         /* Disable Cf8ExtCfg */
 202         msr = rdmsr(NB_CFG_MSR);
 203         msr.hi &= ~(1 << (46 - 32));
 204         wrmsr(NB_CFG_MSR, msr);
 205
 206         if (is_fam15h()) {
 207                 msr = rdmsr(BU_CFG3_MSR);
 208                 /* Set CombineCr0Cd */
 209                 msr.hi |= (1 << (49-32));
 210                 wrmsr(BU_CFG3_MSR, msr);
 211         } else {
 212                 msr = rdmsr(BU_CFG2_MSR);
 213                 /* Clear ClLinesToNbDis */
 214                 msr.lo &= ~(1 << 15);
 215                 /* Clear bit 35 as per Erratum 343 */
 216                 msr.hi &= ~(1 << (35-32));
 217                 wrmsr(BU_CFG2_MSR, msr);
 218         }
 219
 220         if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
 221                 printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
 222
 223                 /* Set SMM base address for this CPU */
 224                 msr = rdmsr(SMM_BASE_MSR);
 225                 msr.lo = SMM_BASE - (lapicid() * 0x400);
 226                 wrmsr(SMM_BASE_MSR, msr);
 227
 228                 /* Enable the SMM memory window */
 229                 msr = rdmsr(SMM_MASK_MSR);
 230                 msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
 231                 wrmsr(SMM_MASK_MSR, msr);
 232         } else {
 233                 printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
 234
 235                 /* Set SMM base address for this CPU */
 236                 msr = rdmsr(SMM_BASE_MSR);
 237                 msr.lo = SMM_BASE - (lapicid() * 0x400);
 238                 wrmsr(SMM_BASE_MSR, msr);
 239
 240                 /* Disable the SMM memory window */
 241                 msr.hi = 0x0;
 242                 msr.lo = 0x0;
 243                 wrmsr(SMM_MASK_MSR, msr);
 244         }
 245
 246         /* Set SMMLOCK to avoid exploits messing with SMM */
 247         msr = rdmsr(HWCR_MSR);
 248         msr.lo |= (1 << 0);
 249         wrmsr(HWCR_MSR, msr);
 250
 251         fam15h_startup_flags[id.nodeid][id.coreid] = 1;
 252 }
 253
 254 static struct device_operations cpu_dev_ops = {
 255         .init = model_10xxx_init,
 256 };
 257
 258 static struct cpu_device_id cpu_table[] = {
 259 //AMD_GH_SUPPORT
 260         { X86_VENDOR_AMD, 0x100f00 },           /* SH-F0 L1 */
 261         { X86_VENDOR_AMD, 0x100f10 },           /* M2 */
 262         { X86_VENDOR_AMD, 0x100f20 },           /* S1g1 */
 263         { X86_VENDOR_AMD, 0x100f21 },
 264         { X86_VENDOR_AMD, 0x100f2A },
 265         { X86_VENDOR_AMD, 0x100f22 },
 266         { X86_VENDOR_AMD, 0x100f23 },
 267         { X86_VENDOR_AMD, 0x100f40 },           /* RB-C0 */
 268         { X86_VENDOR_AMD, 0x100f42 },           /* RB-C2 */
 269         { X86_VENDOR_AMD, 0x100f43 },           /* RB-C3 */
 270         { X86_VENDOR_AMD, 0x100f52 },           /* BL-C2 */
 271         { X86_VENDOR_AMD, 0x100f62 },           /* DA-C2 */
 272         { X86_VENDOR_AMD, 0x100f63 },           /* DA-C3 */
 273         { X86_VENDOR_AMD, 0x100f80 },           /* HY-D0 */
 274         { X86_VENDOR_AMD, 0x100f81 },           /* HY-D1 */
 275         { X86_VENDOR_AMD, 0x100f91 },           /* HY-D1 */
 276         { X86_VENDOR_AMD, 0x100fa0 },           /* PH-E0 */
 277         { X86_VENDOR_AMD, 0x600f12 },           /* OR-B2 */
 278         { X86_VENDOR_AMD, 0x600f20 },           /* OR-C0 */
 279         { 0, 0 },
 280 };
 281
 282 static const struct cpu_driver model_10xxx __cpu_driver = {
 283         .ops      = &cpu_dev_ops,
 284         .id_table = cpu_table,
 285 };