src/mainboard/google/sarien/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2018 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <variant/ec.h>
  17
  18 #include <arch/acpi.h>
  19 DefinitionBlock(
  20         "dsdt.aml",
  21         "DSDT",
  22         0x02,           /* DSDT revision: ACPI v2.0 and up */
  23         OEM_ID,
  24         ACPI_TABLE_CREATOR,
  25         0x20110725      /* OEM revision */
  26 )
  27 {
  28         #include <soc/intel/cannonlake/acpi/platform.asl>
  29
  30         /* global NVS and variables */
  31         #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
  32
  33         /* CPU */
  34         #include <cpu/intel/common/acpi/cpu.asl>
  35
  36         Scope (\_SB) {
  37                 Device (PCI0)
  38                 {
  39                         #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
  40                         #include <soc/intel/cannonlake/acpi/southbridge.asl>
  41                 }
  42                 /* Per board variant mainboard hooks. */
  43                 #include <variant/acpi/mainboard.asl>
  44         }
  45
  46 #if CONFIG(CHROMEOS)
  47         /* Chrome OS specific */
  48         #include <vendorcode/google/chromeos/acpi/chromeos.asl>
  49         /* VPD support */
  50         #include <vendorcode/google/chromeos/acpi/vpd.asl>
  51 #endif
  52
  53         #include <southbridge/intel/common/acpi/sleepstates.asl>
  54
  55         /* Low power idle table */
  56         #include <soc/intel/cannonlake/acpi/lpit.asl>
  57
  58 #if CONFIG(EC_GOOGLE_WILCO)
  59         /* Chrome OS Embedded Controller */
  60         Scope (\_SB.PCI0.LPCB)
  61         {
  62                 /* ACPI code for EC SuperIO functions */
  63                 #include <ec/google/wilco/acpi/superio.asl>
  64                 /* ACPI code for EC functions */
  65                 #include <ec/google/wilco/acpi/ec.asl>
  66         }
  67 #endif
  68
  69         /* Dynamic Platform Thermal Framework */
  70         Scope (\_SB)
  71         {
  72                 /* Per board variant specific definitions. */
  73                 #include <variant/acpi/dptf.asl>
  74                 /* Include soc specific DPTF changes */
  75                 #include <soc/intel/cannonlake/acpi/dptf.asl>
  76                 /* Include common dptf ASL files */
  77                 #include <soc/intel/common/acpi/dptf/dptf.asl>
  78         }
  79 }