src/soc/intel/cannonlake/include/soc/pci_devs.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Google Inc.
   5  * Copyright (C) 2017 Intel Corporation.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef _SOC_CANNONLAKE_PCI_DEVS_H_
  18 #define _SOC_CANNONLAKE_PCI_DEVS_H_
  19
  20 #include <device/pci_def.h>
  21 #include <rules.h>
  22
  23 #define _SA_DEVFN(slot)         PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
  24 #define _PCH_DEVFN(slot, func)  PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
  25
  26 #if !defined(__SIMPLE_DEVICE__)
  27 #include <device/device.h>
  28 #include <device/pci_def.h>
  29 #define _SA_DEV(slot)           dev_find_slot(0, _SA_DEVFN(slot))
  30 #define _PCH_DEV(slot, func)    dev_find_slot(0, _PCH_DEVFN(slot, func))
  31 #else
  32 #include <arch/io.h>
  33 #define _SA_DEV(slot)           PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
  34 #define _PCH_DEV(slot, func)    PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
  35 #endif
  36
  37 /* System Agent Devices */
  38
  39 #define SA_DEV_SLOT_ROOT        0x00
  40 #define  SA_DEVFN_ROOT          _SA_DEVFN(ROOT)
  41 #define  SA_DEV_ROOT            _SA_DEV(ROOT)
  42
  43 #define SA_DEV_SLOT_IGD         0x02
  44 #define  SA_DEVFN_IGD           _SA_DEVFN(IGD)
  45 #define  SA_DEV_IGD             _SA_DEV(IGD)
  46
  47 #define SA_DEV_SLOT_DSP         0x04
  48 #define  SA_DEVFN_DSP           _SA_DEVFN(DSP)
  49 #define  SA_DEV_DSP             _SA_DEV(DSP)
  50
  51 /* PCH Devices */
  52 #define PCH_DEV_SLOT_THERMAL    0x12
  53 #define  PCH_DEVFN_THERMAL      _PCH_DEVFN(THERMAL, 0)
  54 #define  PCH_DEVFN_UFS          _PCH_DEVFN(THERMAL, 5)
  55 #define  PCH_DEVFN_GSPI2        _PCH_DEVFN(THERMAL, 6)
  56 #define  PCH_DEV_THERMAL        _PCH_DEV(THERMAL, 0)
  57 #define  PCH_DEV_UFS            _PCH_DEV(THERMAL, 5)
  58 #define  PCH_DEV_GSPI2          _PCH_DEV(THERMAL, 6)
  59
  60 #define PCH_DEV_SLOT_ISH        0x13
  61 #define  PCH_DEVFN_ISH          _PCH_DEVFN(ISH, 0)
  62 #define  PCH_DEV_ISH            _PCH_DEV(ISH, 0)
  63
  64 #define PCH_DEV_SLOT_XHCI       0x14
  65 #define  PCH_DEVFN_XHCI         _PCH_DEVFN(XHCI, 0)
  66 #define  PCH_DEVFN_USBOTG       _PCH_DEVFN(XHCI, 1)
  67 #define  PCH_DEVFN_CNViWIFI     _PCH_DEVFN(XHCI, 3)
  68 #define  PCH_DEVFN_SDCARD       _PCH_DEVFN(XHCI, 5)
  69 #define  PCH_DEV_XHCI           _PCH_DEV(XHCI, 0)
  70 #define  PCH_DEV_USBOTG         _PCH_DEV(XHCI, 1)
  71 #define  PCH_DEV_CNViWIFI       _PCH_DEV(XHCI, 3)
  72 #define  PCH_DEV_SDCARD         _PCH_DEV(XHCI, 5)
  73
  74 #define PCH_DEV_SLOT_SIO1       0x15
  75 #define  PCH_DEVFN_I2C0         _PCH_DEVFN(SIO1, 0)
  76 #define  PCH_DEVFN_I2C1         _PCH_DEVFN(SIO1, 1)
  77 #define  PCH_DEVFN_I2C2         _PCH_DEVFN(SIO1, 2)
  78 #define  PCH_DEVFN_I2C3         _PCH_DEVFN(SIO1, 3)
  79 #define  PCH_DEV_I2C0           _PCH_DEV(SIO1, 0)
  80 #define  PCH_DEV_I2C1           _PCH_DEV(SIO1, 1)
  81 #define  PCH_DEV_I2C2           _PCH_DEV(SIO1, 2)
  82 #define  PCH_DEV_I2C3           _PCH_DEV(SIO1, 3)
  83
  84 #define PCH_DEV_SLOT_CSE        0x16
  85 #define  PCH_DEVFN_CSE          _PCH_DEVFN(CSE, 0)
  86 #define  PCH_DEVFN_CSE_2        _PCH_DEVFN(CSE, 1)
  87 #define  PCH_DEVFN_CSE_IDER     _PCH_DEVFN(CSE, 2)
  88 #define  PCH_DEVFN_CSE_KT       _PCH_DEVFN(CSE, 3)
  89 #define  PCH_DEVFN_CSE_3        _PCH_DEVFN(CSE, 4)
  90 #define  PCH_DEVFN_CSE_4        _PCH_DEVFN(CSE, 5)
  91 #define  PCH_DEV_CSE            _PCH_DEV(CSE, 0)
  92 #define  PCH_DEV_CSE_2          _PCH_DEV(CSE, 1)
  93 #define  PCH_DEV_CSE_IDER       _PCH_DEV(CSE, 2)
  94 #define  PCH_DEV_CSE_KT         _PCH_DEV(CSE, 3)
  95 #define  PCH_DEV_CSE_3          _PCH_DEV(CSE, 4)
  96 #define  PCH_DEV_CSE_4          _PCH_DEV(CSE, 5)
  97
  98 #define PCH_DEV_SLOT_SATA       0x17
  99 #define  PCH_DEVFN_SATA         _PCH_DEVFN(SATA, 0)
 100 #define  PCH_DEV_SATA           _PCH_DEV(SATA, 0)
 101
 102 #define PCH_DEV_SLOT_SIO2       0x19
 103 #define  PCH_DEVFN_I2C4         _PCH_DEVFN(SIO2, 0)
 104 #define  PCH_DEVFN_I2C5         _PCH_DEVFN(SIO2, 1)
 105 #define  PCH_DEVFN_UART2        _PCH_DEVFN(SIO2, 2)
 106 #define  PCH_DEV_I2C4           _PCH_DEV(SIO2, 0)
 107 #define  PCH_DEV_I2C5           _PCH_DEV(SIO2, 1)
 108 #define  PCH_DEV_UART2          _PCH_DEV(SIO2, 2)
 109
 110 #define PCH_DEV_SLOT_STORAGE    0x1A
 111 #define  PCH_DEVFN_EMMC         _PCH_DEVFN(STORAGE, 0)
 112 #define  PCH_DEV_EMMC           _PCH_DEV(STORAGE, 0)
 113
 114 #define PCH_DEV_SLOT_PCIE       0x1c
 115 #define  PCH_DEVFN_PCIE1        _PCH_DEVFN(PCIE, 0)
 116 #define  PCH_DEVFN_PCIE2        _PCH_DEVFN(PCIE, 1)
 117 #define  PCH_DEVFN_PCIE3        _PCH_DEVFN(PCIE, 2)
 118 #define  PCH_DEVFN_PCIE4        _PCH_DEVFN(PCIE, 3)
 119 #define  PCH_DEVFN_PCIE5        _PCH_DEVFN(PCIE, 4)
 120 #define  PCH_DEVFN_PCIE6        _PCH_DEVFN(PCIE, 5)
 121 #define  PCH_DEVFN_PCIE7        _PCH_DEVFN(PCIE, 6)
 122 #define  PCH_DEVFN_PCIE8        _PCH_DEVFN(PCIE, 7)
 123 #define  PCH_DEV_PCIE1          _PCH_DEV(PCIE, 0)
 124 #define  PCH_DEV_PCIE2          _PCH_DEV(PCIE, 1)
 125 #define  PCH_DEV_PCIE3          _PCH_DEV(PCIE, 2)
 126 #define  PCH_DEV_PCIE4          _PCH_DEV(PCIE, 3)
 127 #define  PCH_DEV_PCIE5          _PCH_DEV(PCIE, 4)
 128 #define  PCH_DEV_PCIE6          _PCH_DEV(PCIE, 5)
 129 #define  PCH_DEV_PCIE7          _PCH_DEV(PCIE, 6)
 130 #define  PCH_DEV_PCIE8          _PCH_DEV(PCIE, 7)
 131
 132 #define PCH_DEV_SLOT_PCIE_1     0x1d
 133 #define  PCH_DEVFN_PCIE9        _PCH_DEVFN(PCIE_1, 0)
 134 #define  PCH_DEVFN_PCIE10       _PCH_DEVFN(PCIE_1, 1)
 135 #define  PCH_DEVFN_PCIE11       _PCH_DEVFN(PCIE_1, 2)
 136 #define  PCH_DEVFN_PCIE12       _PCH_DEVFN(PCIE_1, 3)
 137 #define  PCH_DEVFN_PCIE13       _PCH_DEVFN(PCIE_1, 4)
 138 #define  PCH_DEVFN_PCIE14       _PCH_DEVFN(PCIE_1, 5)
 139 #define  PCH_DEVFN_PCIE15       _PCH_DEVFN(PCIE_1, 6)
 140 #define  PCH_DEVFN_PCIE16       _PCH_DEVFN(PCIE_1, 7)
 141 #define  PCH_DEV_PCIE9          _PCH_DEV(PCIE_1, 0)
 142 #define  PCH_DEV_PCIE10         _PCH_DEV(PCIE_1, 1)
 143 #define  PCH_DEV_PCIE11         _PCH_DEV(PCIE_1, 2)
 144 #define  PCH_DEV_PCIE12         _PCH_DEV(PCIE_1, 3)
 145 #define  PCH_DEV_PCIE13         _PCH_DEV(PCIE_1, 4)
 146 #define  PCH_DEV_PCIE14         _PCH_DEV(PCIE_1, 5)
 147 #define  PCH_DEV_PCIE15         _PCH_DEV(PCIE_1, 6)
 148 #define  PCH_DEV_PCIE16         _PCH_DEV(PCIE_1, 7)
 149
 150 #define PCH_DEV_SLOT_SIO3       0x1e
 151 #define  PCH_DEVFN_UART0        _PCH_DEVFN(SIO3, 0)
 152 #define  PCH_DEVFN_UART1        _PCH_DEVFN(SIO3, 1)
 153 #define  PCH_DEVFN_GSPI0        _PCH_DEVFN(SIO3, 2)
 154 #define  PCH_DEVFN_GSPI1        _PCH_DEVFN(SIO3, 3)
 155 #define  PCH_DEV_UART0          _PCH_DEV(SIO3, 0)
 156 #define  PCH_DEV_UART1          _PCH_DEV(SIO3, 1)
 157 #define  PCH_DEV_GSPI0          _PCH_DEV(SIO3, 2)
 158 #define  PCH_DEV_GSPI1          _PCH_DEV(SIO3, 3)
 159
 160 #define PCH_DEV_SLOT_LPC        0x1f
 161 #define  PCH_DEVFN_LPC          _PCH_DEVFN(LPC, 0)
 162 #define  PCH_DEVFN_P2SB         _PCH_DEVFN(LPC, 1)
 163 #define  PCH_DEVFN_PMC          _PCH_DEVFN(LPC, 2)
 164 #define  PCH_DEVFN_HDA          _PCH_DEVFN(LPC, 3)
 165 #define  PCH_DEVFN_SMBUS        _PCH_DEVFN(LPC, 4)
 166 #define  PCH_DEVFN_SPI          _PCH_DEVFN(LPC, 5)
 167 #define  PCH_DEVFN_GBE          _PCH_DEVFN(LPC, 6)
 168 #define  PCH_DEVFN_TRACEHUB     _PCH_DEVFN(LPC, 7)
 169 #define  PCH_DEV_LPC            _PCH_DEV(LPC, 0)
 170 #define  PCH_DEV_P2SB           _PCH_DEV(LPC, 1)
 171 #define  PCH_DEV_PMC            _PCH_DEV(LPC, 2)
 172 #define  PCH_DEV_HDA            _PCH_DEV(LPC, 3)
 173 #define  PCH_DEV_SMBUS          _PCH_DEV(LPC, 4)
 174 #define  PCH_DEV_SPI            _PCH_DEV(LPC, 5)
 175 #define  PCH_DEV_GBE            _PCH_DEV(LPC, 6)
 176 #define  PCH_DEV_TRACEHUB       _PCH_DEV(LPC, 7)
 177
 178 #endif