src/mainboard/lenovo/x200/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 secunet Security Networks AG
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  18
  19 #include <stdint.h>
  20 #include <string.h>
  21 #include <arch/io.h>
  22 #include <arch/acpi.h>
  23 #include <cpu/x86/lapic.h>
  24 #include <cpu/x86/msr.h>
  25 #include <cpu/x86/tsc.h>
  26 #include <cpu/intel/romstage.h>
  27 #include <cbmem.h>
  28 #include <lib.h>
  29 #include <pc80/mc146818rtc.h>
  30 #include <romstage_handoff.h>
  31 #include <console/console.h>
  32 #include <southbridge/intel/i82801ix/i82801ix.h>
  33 #include <northbridge/intel/gm45/gm45.h>
  34 #include "gpio.h"
  35 #include <timestamp.h>
  36
  37 #define LPC_DEV PCI_DEV(0, 0x1f, 0)
  38 #define MCH_DEV PCI_DEV(0, 0, 0)
  39
  40
  41 static void early_lpc_setup(void)
  42 {
  43         /* Set up SuperIO LPC forwards */
  44
  45         /* Configure serial IRQs.*/
  46         pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
  47         /* Map COMa on 0x3f8, COMb on 0x2f8. */
  48         pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
  49         pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
  50         pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
  51         pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
  52         pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
  53 }
  54
  55 void mainboard_romstage_entry(unsigned long bist)
  56 {
  57         sysinfo_t sysinfo;
  58         int s3resume = 0;
  59         int cbmem_initted;
  60         u16 reg16;
  61
  62         timestamp_init(timestamp_get());
  63         timestamp_add_now(TS_START_ROMSTAGE);
  64
  65         /* basic northbridge setup, including MMCONF BAR */
  66         gm45_early_init();
  67
  68         if (bist == 0)
  69                 enable_lapic();
  70
  71         /* First, run everything needed for console output. */
  72         i82801ix_early_init();
  73         early_lpc_setup();
  74         console_init();
  75         printk(BIOS_DEBUG, "running main(bist = %lu)\n", bist);
  76
  77         reg16 = pci_read_config16(LPC_DEV, D31F0_GEN_PMCON_3);
  78         pci_write_config16(LPC_DEV, D31F0_GEN_PMCON_3, reg16);
  79         if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE) && !(reg16 & (1 << 9))) {
  80                 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
  81                 gm45_early_reset();
  82         }
  83
  84         setup_pch_gpios(&x200_gpio_map);
  85
  86         /* ASPM related setting, set early by original BIOS. */
  87         DMIBAR16(0x204) &= ~(3 << 10);
  88
  89         /* Check for S3 resume. */
  90         const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
  91         if (((pm1_cnt >> 10) & 7) == 5) {
  92 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
  93                 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
  94                 s3resume = 1;
  95                 /* Clear SLP_TYPE. This will break stage2 but
  96                  * we care for that when we get there.
  97                  */
  98                 outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
  99 #else
 100                 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 101 #endif
 102         }
 103
 104         /* RAM initialization */
 105         enter_raminit_or_reset();
 106         memset(&sysinfo, 0, sizeof(sysinfo));
 107         sysinfo.spd_map[0] = 0x50;
 108         sysinfo.spd_map[2] = 0x51;
 109         sysinfo.enable_igd = 1;
 110         sysinfo.enable_peg = 0;
 111         get_gmch_info(&sysinfo);
 112         raminit(&sysinfo, s3resume);
 113
 114         const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN);
 115         /* Disable D4F0 (unknown signal controller). */
 116         pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000);
 117
 118         init_pm(&sysinfo, 0);
 119
 120         i82801ix_dmi_setup();
 121         gm45_late_init(sysinfo.stepping);
 122         i82801ix_dmi_poll_vc1();
 123
 124         MCHBAR16(SSKPD_MCHBAR) = 0xCAFE;
 125         /* Enable ethernet.  */
 126         RCBA32(0x3414) &= ~0x20;
 127
 128         RCBA32(0x0238) = 0x00543210;
 129         RCBA32(0x0240) = 0x009c0b02;
 130         RCBA32(0x0244) = 0x00a20b1a;
 131         RCBA32(0x0248) = 0x005402cb;
 132         RCBA32(0x0254) = 0x00470966;
 133         RCBA32(0x0258) = 0x00470473;
 134         RCBA32(0x0260) = 0x00e90825;
 135         RCBA32(0x0278) = 0x00bc0efb;
 136         RCBA32(0x027c) = 0x00c00f0b;
 137         RCBA32(0x0280) = 0x00670000;
 138         RCBA32(0x0284) = 0x006d0000;
 139         RCBA32(0x0288) = 0x00600b4e;
 140         RCBA32(0x1e10) = 0x00020800;
 141         RCBA32(0x1e18) = 0x36ea00a0;
 142         RCBA32(0x1e80) = 0x000c0801;
 143         RCBA32(0x1e84) = 0x000200f0;
 144         RCBA32(0x2028) = 0x04c8f95e;
 145         RCBA32(0x202c) = 0x055c095e;
 146         RCBA32(0x204c) = 0x001ffc00;
 147         RCBA32(0x2050) = 0x00100fff;
 148         RCBA32(0x2090) = 0x37000000;
 149         RCBA32(0x20b0) = 0x0c000000;
 150         RCBA32(0x20d0) = 0x09000000;
 151         RCBA32(0x20f0) = 0x05000000;
 152         RCBA32(0x3400) = 0x0000001c;
 153         RCBA32(0x3410) = 0x00100461;
 154         RCBA32(0x3414) = 0x00000000;
 155         RCBA32(0x341c) = 0xbf4f001f;
 156         RCBA32(0x3420) = 0x00000000;
 157         RCBA32(0x3430) = 0x00000001;
 158
 159         init_iommu();
 160
 161         /* FIXME: make a proper SMBUS mux support.  */
 162         outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
 163
 164         cbmem_initted = !cbmem_recovery(s3resume);
 165
 166         romstage_handoff_init(cbmem_initted && s3resume);
 167
 168         printk(BIOS_SPEW, "exit main()\n");
 169 }