src/soc/intel/skylake/romstage/pmc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2016 Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <soc/pci_devs.h>
  17 #include <soc/pm.h>
  18
  19 void pmc_set_disb(void)
  20 {
  21         /* Set the DISB after DRAM init */
  22         u32 disb_val = 0;
  23         pci_devfn_t dev = PCH_DEV_PMC;
  24         disb_val = pci_read_config32(dev, GEN_PMCON_A);
  25         disb_val |= DISB;
  26
  27         /* Don't clear bits that are write-1-to-clear */
  28         disb_val &= ~(GBL_RST_STS | MS4V);
  29         pci_write_config32(dev, GEN_PMCON_A, disb_val);
  30 }