src/mainboard/pcengines/apu1/mainboard.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <amdblocks/acpimmio.h>
  16 #include <console/console.h>
  17 #include <device/device.h>
  18 #include <device/mmio.h>
  19 #include <device/pci_ops.h>
  20 #include <device/pci_def.h>
  21 #include <southbridge/amd/common/amd_pci_util.h>
  22 #include <smbios.h>
  23 #include <string.h>
  24 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
  25 #include <southbridge/amd/cimx/sb800/pci_devs.h>
  26 #include <northbridge/amd/agesa/family14/pci_devs.h>
  27 #include <superio/nuvoton/nct5104d/nct5104d.h>
  28 #include "gpio_ftns.h"
  29
  30 /***********************************************************
  31  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  32  * This table is responsible for physically routing the PIC and
  33  * IOAPIC IRQs to the different PCI devices on the system.  It
  34  * is read and written via registers 0xC00/0xC01 as an
  35  * Index/Data pair.  These values are chipset and mainboard
  36  * dependent and should be updated accordingly.
  37  *
  38  * These values are used by the PCI configuration space,
  39  * MP Tables.  TODO: Make ACPI use these values too.
  40  *
  41  * The PCI INTA/B/C/D pins are connected to
  42  * FCH pins INTE/F/G/H on the schematic so these need
  43  * to be routed as well.
  44  */
  45 static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
  46         /* INTA# - INTH# */
  47         [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
  48         /* Misc-nil,0,1,2, INT from Serial irq */
  49         [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  50         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
  51         [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
  52         /* IMC INT0 - 5 */
  53         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  54         /* USB Devs 18/19/20/22 INTA-C */
  55         [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
  56         /* IDE, SATA */
  57         [0x40] = 0x0B,0x0B,
  58         /* GPPInt0 - 3 */
  59         [0x50] = 0x0A,0x0B,0x0A,0x0B
  60 };
  61
  62 static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  63         /* INTA# - INTH# */
  64         [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
  65         /* Misc-nil,0,1,2, INT from Serial irq */
  66         [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  67         /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
  68         [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
  69         /* IMC INT0 - 5 */
  70         [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  71         /* USB Devs 18/19/22/20 INTA-C */
  72         [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
  73         /* IDE, SATA */
  74         [0x40] = 0x11,0x13,
  75         /* GPPInt0 - 3 */
  76         [0x50] = 0x10,0x11,0x12,0x13
  77 };
  78
  79 /*
  80  * This table defines the index into the picr/intr_data
  81  * tables for each device.  Any enabled device and slot
  82  * that uses hardware interrupts should have an entry
  83  * in this table to define its index into the FCH
  84  * PCI_INTR register 0xC00/0xC01.  This index will define
  85  * the interrupt that it should use.  Putting PIRQ_A into
  86  * the PIN A index for a device will tell that device to
  87  * use PIC IRQ 10 if it uses PIN A for its hardware INT.
  88  */
  89 /*
  90  * The PCI slot INTA/B/C/D connected to PIRQE/F/G/H
  91  * but because of PCI INT_PIN swizzle isn't implemented to match
  92  * the IDSEL (dev 3) of the slot, the table is adjusted for the
  93  * swizzle and INTA is connected to PIRQH so PINA/B/C/D on
  94  * off-chip devices should get mapped to PIRQH/E/F/G.
  95  */
  96 static const struct pirq_struct mainboard_pirq_data[] = {
  97         /* {PCI_devfn,        {PIN A, PIN B, PIN C, PIN D}}, */
  98         {GFX_DEVFN,           {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}},      /* VGA:       01.0 */
  99         {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       04.0 */
 100         {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       05.0 */
 101         {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* NIC:       06.0 */
 102         {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* miniPCIe:  07.0 */
 103         {SATA_DEVFN,          {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},  /* SATA:      11.0 */
 104         {OHCI1_DEVFN,         {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1:     12.0 */
 105         {EHCI1_DEVFN,         {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1:     12.2 */
 106         {OHCI2_DEVFN,         {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2:     13.0 */
 107         {EHCI2_DEVFN,         {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2:     13.2 */
 108         {SMBUS_DEVFN,         {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS:     14.0 */
 109         {IDE_DEVFN,           {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},   /* IDE:       14.1 */
 110         {HDA_DEVFN,           {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* HDA:       14.2 */
 111         {SB_PCI_PORT_DEVFN,   {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},        /* PCI bdg:   14.4 */
 112         {OHCI4_DEVFN,         {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4:     14.5 */
 113         {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},        /* miniPCIe:  15.0 */
 114         {OHCI3_DEVFN,         {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3:     16.0 */
 115         {EHCI3_DEVFN,         {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3:     16.2 */
 116 };
 117
 118 /* PIRQ Setup */
 119 static void pirq_setup(void)
 120 {
 121         pirq_data_ptr = mainboard_pirq_data;
 122         pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
 123         intr_data_ptr = mainboard_intr_data;
 124         picr_data_ptr = mainboard_picr_data;
 125 }
 126
 127 /* Wrapper to enable GPIO/UART devices under menuconfig. Revisit
 128  * once configuration file format for SPI flash storage is complete.
 129  */
 130 #define SIO_PORT 0x2e
 131
 132 static void config_gpio_mux(void)
 133 {
 134         struct device *uart, *gpio;
 135
 136         uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
 137         gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
 138         if (uart)
 139                 uart->enabled = CONFIG(APU1_PINMUX_UART_C);
 140         if (gpio)
 141                 gpio->enabled = CONFIG(APU1_PINMUX_GPIO0);
 142
 143         uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
 144         gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
 145         if (uart)
 146                 uart->enabled = CONFIG(APU1_PINMUX_UART_D);
 147         if (gpio)
 148                 gpio->enabled = CONFIG(APU1_PINMUX_GPIO1);
 149 }
 150
 151 static void pnp_raw_resource(struct device *dev, u8 reg, u8 val)
 152 {
 153         struct resource *res;
 154         res = new_resource(dev, reg);
 155         res->base = val;
 156         res->size = 0;
 157         res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED;
 158 }
 159
 160 static void config_addon_uart(void)
 161 {
 162         struct device *uart;
 163
 164         uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
 165         if (uart && uart->enabled && CONFIG(UART_C_RS485))
 166                 pnp_raw_resource(uart, 0xf2, 0x12);
 167
 168         uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
 169         if (uart && uart->enabled && CONFIG(UART_D_RS485))
 170                 pnp_raw_resource(uart, 0xf2, 0x12);
 171 }
 172
 173 /**********************************************
 174  * Enable the dedicated functions of the board.
 175  **********************************************/
 176 static void mainboard_enable(struct device *dev)
 177 {
 178         printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
 179
 180         config_gpio_mux();
 181         config_addon_uart();
 182
 183         /* Power off unused clock pins of GPP PCIe devices
 184          * GPP CLK0-2 are connected to the 3 ethernet chips
 185          * GPP CLK3-4 are connected to the miniPCIe slots
 186          */
 187         misc_write8(0, 0x21);
 188         misc_write8(1, 0x43);
 189         /* GPP CLK5 is only connected to test pads -> disable */
 190         misc_write8(2, 0x05);
 191         /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
 192         misc_write8(3, 0);
 193         misc_write8(4, 0);
 194
 195         /* Initialize the PIRQ data structures for consumption */
 196         pirq_setup();
 197 }
 198
 199 /*
 200  * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address
 201  * into the smbios serial number location.
 202  */
 203 const char *smbios_mainboard_serial_number(void)
 204 {
 205         static char serial[10];
 206         struct device *dev;
 207         uintptr_t bar18;
 208         u32 mac_addr = 0;
 209         int i;
 210
 211         /* Already initialized. */
 212         if (serial[0] != 0)
 213                 return serial;
 214
 215         dev = pcidev_on_root(4, 0);
 216         if (dev)
 217                 dev = pcidev_path_behind(dev->link_list, PCI_DEVFN(0, 0));
 218         if (!dev)
 219                 return serial;
 220
 221         /* Read in the last 3 bytes of NIC's MAC address. */
 222         bar18 = pci_read_config32(dev, 0x18);
 223         bar18 &= 0xFFFFFC00;
 224         for (i = 3; i < 6; i++) {
 225                 mac_addr <<= 8;
 226                 mac_addr |= read8((u8 *)bar18 + i);
 227         }
 228         mac_addr &= 0x00FFFFFF;
 229         mac_addr /= 4;
 230         mac_addr -= 64;
 231
 232         snprintf(serial, sizeof(serial), "%d", mac_addr);
 233         return serial;
 234 }
 235
 236 /*
 237  * Set up "Over Current Control 1" (reg 0x58) on the first OHCI device.
 238  * The remaining ports on the second device are for mcpie2/sdcard and
 239  * can stay at the power-on default value.
 240  *
 241  * The schematic shows this transposed mapping for the first device:
 242  * chipset port 0 -> port 1 (j12 external 2, usboc0#)
 243  * chipset port 1 -> port 4 (j17 mpcie1)
 244  * chipset port 2 -> port 2 (j14 header row1, usboc1#)
 245  * chipset port 3 -> port 3 (j14 header row2, usboc1#)
 246  * chipset port 4 -> port 0 (j12 external 1. usboc0#)
 247  *
 248  * Register mapping:
 249  * bit0-3: Mapping for HS Port 0
 250  * bit4-7: Mapping for HS Port 1
 251  * bit8-11: Mapping for HS Port 2
 252  * bit12-15: Mapping for HS Port 3
 253  * bit16-19: Mapping for HS Port 4
 254  * bit20-31: Reserved (0)
 255  *
 256  * power-on default: 0xfffff
 257  * A value >7 will disable the overcurrent detection.
 258  */
 259 static void usb_oc_setup(void)
 260 {
 261         struct device *dev = pcidev_on_root(0x12, 0);
 262
 263         pci_write_config32(dev, 0x58, 0x011f0);
 264 }
 265
 266 /*
 267  * We will stuff the memory size into the smbios sku location.
 268  */
 269 const char *smbios_system_sku(void)
 270 {
 271         static char sku[5];
 272         if (sku[0] != 0)
 273                 return sku;
 274
 275         if (!get_spd_offset())
 276                 snprintf(sku, sizeof(sku), "2 GB");
 277         else
 278                 snprintf(sku, sizeof(sku), "4 GB");
 279         return sku;
 280 }
 281
 282 static void mainboard_final(void *chip_info)
 283 {
 284         u32 mmio_base;
 285
 286         printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Final.\n");
 287
 288         /*
 289          * LED1/D7/GPIO_189 should be 0
 290          * LED2/D6/GPIO_190 should be 1
 291          * LED3/D5/GPIO_191 should be 1
 292          */
 293         mmio_base = find_gpio_base();
 294         configure_gpio(mmio_base, GPIO_189, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_LOW);
 295         configure_gpio(mmio_base, GPIO_190, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
 296         configure_gpio(mmio_base, GPIO_191, GPIO_FTN_1, GPIO_OUTPUT | GPIO_DATA_HIGH);
 297         usb_oc_setup();
 298 }
 299
 300 struct chip_operations mainboard_ops = {
 301         .enable_dev = mainboard_enable,
 302         .final = mainboard_final,
 303 };