2 * This file is part of the coreboot project.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <arch/acpi.h>
17 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
20 #include "routing.asl"
24 /* Routing is in System Bus scope */
28 /* Bus 0, Dev 0 - RS780 Host Controller */
29 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
30 Package(){0x0001FFFF, 0, INTC, 0 },
31 Package(){0x0001FFFF, 1, INTD, 0 },
32 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
33 Package(){0x0002FFFF, 0, INTC, 0 },
34 Package(){0x0002FFFF, 1, INTD, 0 },
35 Package(){0x0002FFFF, 2, INTA, 0 },
36 Package(){0x0002FFFF, 3, INTB, 0 },
37 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
38 Package(){0x0003FFFF, 0, INTD, 0 },
39 Package(){0x0003FFFF, 1, INTA, 0 },
40 Package(){0x0003FFFF, 2, INTB, 0 },
41 Package(){0x0003FFFF, 3, INTC, 0 },
42 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
43 Package(){0x0004FFFF, 0, INTA, 0 },
44 Package(){0x0004FFFF, 1, INTB, 0 },
45 Package(){0x0004FFFF, 2, INTC, 0 },
46 Package(){0x0004FFFF, 3, INTD, 0 },
47 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
48 Package(){0x0005FFFF, 0, INTB, 0 },
49 Package(){0x0005FFFF, 1, INTC, 0 },
50 Package(){0x0005FFFF, 2, INTD, 0 },
51 Package(){0x0005FFFF, 3, INTA, 0 },
52 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
53 Package(){0x0006FFFF, 0, INTC, 0 },
54 Package(){0x0006FFFF, 1, INTD, 0 },
55 Package(){0x0006FFFF, 2, INTA, 0 },
56 Package(){0x0006FFFF, 3, INTB, 0 },
57 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
58 Package(){0x0007FFFF, 0, INTD, 0 },
59 Package(){0x0007FFFF, 1, INTA, 0 },
60 Package(){0x0007FFFF, 2, INTB, 0 },
61 Package(){0x0007FFFF, 3, INTC, 0 },
63 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
67 /* Bus 0, Dev 17 - SATA controller */
68 Package(){0x0011FFFF, 0, INTD, 0 },
70 /* OHCI, dev 18, 19, 22 func 0
71 * EHCI, dev 18, 19, 22 func 2 */
72 Package(){0x0012FFFF, 0, INTC, 0 }, /* Dev 12, INTA, handled by INTC device, Global */
73 Package(){0x0012FFFF, 1, INTB, 0 }, /* Dev 12, INTB, handled by INTB device, Global */
75 Package(){0x0013FFFF, 0, INTC, 0 },
76 Package(){0x0013FFFF, 1, INTB, 0 },
78 Package(){0x0016FFFF, 0, INTC, 0 },
79 Package(){0x0016FFFF, 1, INTB, 0 },
81 /* Bus 0, Dev 20 - F0:SMBus/ACPI; F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
82 Package(){0x0014FFFF, 0, INTA, 0 },
83 Package(){0x0014FFFF, 1, INTB, 0 },
84 Package(){0x0014FFFF, 2, INTC, 0 },
85 Package(){0x0014FFFF, 3, INTD, 0 },
87 Package(){0x0015FFFF, 0, INTA, 0 },
88 Package(){0x0015FFFF, 1, INTB, 0 },
89 Package(){0x0015FFFF, 2, INTC, 0 },
90 Package(){0x0015FFFF, 3, INTD, 0 },
94 /* NB devices in APIC mode */
95 /* Bus 0, Dev 0 - RS780 Host Controller */
97 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
98 Package(){0x0001FFFF, 0, 0, 18 },
99 Package(){0x0001FFFF, 1, 0, 19 },
101 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
102 Package(){0x0002FFFF, 0, 0, 18 },
103 /* Package(){0x0002FFFF, 1, 0, 19 }, */
104 /* Package(){0x0002FFFF, 2, 0, 16 }, */
105 /* Package(){0x0002FFFF, 3, 0, 17 }, */
107 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
108 Package(){0x0003FFFF, 0, 0, 19 },
109 Package(){0x0003FFFF, 1, 0, 16 },
110 Package(){0x0003FFFF, 2, 0, 17 },
111 Package(){0x0003FFFF, 3, 0, 18 },
113 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
114 Package(){0x0004FFFF, 0, 0, 16 },
115 Package(){0x0004FFFF, 1, 0, 17 },
116 Package(){0x0004FFFF, 2, 0, 18 },
117 Package(){0x0004FFFF, 3, 0, 19 },
119 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
120 Package(){0x0005FFFF, 0, 0, 17 },
121 Package(){0x0005FFFF, 1, 0, 18 },
122 Package(){0x0005FFFF, 2, 0, 19 },
123 Package(){0x0005FFFF, 3, 0, 16 },
125 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
126 Package(){0x0006FFFF, 0, 0, 18 },
127 Package(){0x0006FFFF, 1, 0, 19 },
128 Package(){0x0006FFFF, 2, 0, 16 },
129 Package(){0x0006FFFF, 3, 0, 17 },
131 /* Bus 0, Dev 7 - PCIe Bridge for network card */
132 Package(){0x0007FFFF, 0, 0, 19 },
133 Package(){0x0007FFFF, 1, 0, 16 },
134 Package(){0x0007FFFF, 2, 0, 17 },
135 Package(){0x0007FFFF, 3, 0, 18 },
137 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
139 /* SB devices in APIC mode */
140 /* Bus 0, Dev 17 - SATA controller */
141 Package(){0x0011FFFF, 0, 0, 19 },
143 /* OHCI, dev 18, 19, 22 func 0
144 * EHCI, dev 18, 19, 22 func 2 */
145 Package(){0x0012FFFF, 0, 0, 18 },
146 Package(){0x0012FFFF, 1, 0, 17 },
148 Package(){0x0013FFFF, 0, 0, 18 },
149 Package(){0x0013FFFF, 1, 0, 17 },
151 Package(){0x0016FFFF, 0, 0, 18 },
152 Package(){0x0016FFFF, 1, 0, 17 },
154 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
155 Package(){0x0014FFFF, 0, 0, 16 },
156 Package(){0x0014FFFF, 1, 0, 17 },
157 Package(){0x0014FFFF, 2, 0, 18 },
158 Package(){0x0014FFFF, 3, 0, 19 },
159 /* Package(){0x00140004, 2, 0, 18 }, */
160 /* Package(){0x00140004, 3, 0, 19 }, */
161 /* Package(){0x00140005, 1, 0, 17 }, */
162 /* Package(){0x00140006, 1, 0, 17 }, */
165 Package(){0x0015FFFF, 0, 0, 16 },
166 Package(){0x0015FFFF, 1, 0, 17 },
167 Package(){0x0015FFFF, 2, 0, 18 },
168 Package(){0x0015FFFF, 3, 0, 19 },
172 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
173 Package(){0x0005FFFF, 0, INTA, 0 },
174 Package(){0x0005FFFF, 1, INTB, 0 },
175 Package(){0x0005FFFF, 2, INTC, 0 },
176 Package(){0x0005FFFF, 3, INTD, 0 },
178 Name(APR1, Package(){
179 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
180 Package(){0x0005FFFF, 0, 0, 18 },
181 Package(){0x0005FFFF, 1, 0, 19 },
182 /* Package(){0x0005FFFF, 2, 0, 20 }, */
183 /* Package(){0x0005FFFF, 3, 0, 17 }, */
187 /* The external GFX - Hooked to PCIe slot 2 */
188 Package(){0x0000FFFF, 0, INTC, 0 },
189 Package(){0x0000FFFF, 1, INTD, 0 },
190 Package(){0x0000FFFF, 2, INTA, 0 },
191 Package(){0x0000FFFF, 3, INTB, 0 },
193 Name(APS2, Package(){
194 /* The external GFX - Hooked to PCIe slot 2 */
195 Package(){0x0000FFFF, 0, 0, 18 },
196 Package(){0x0000FFFF, 1, 0, 19 },
197 Package(){0x0000FFFF, 2, 0, 16 },
198 Package(){0x0000FFFF, 3, 0, 17 },
202 /* PCIe slot - Hooked to PCIe slot 4 */
203 Package(){0x0000FFFF, 0, INTA, 0 },
204 Package(){0x0000FFFF, 1, INTB, 0 },
205 Package(){0x0000FFFF, 2, INTC, 0 },
206 Package(){0x0000FFFF, 3, INTD, 0 },
208 Name(APS4, Package(){
209 /* PCIe slot - Hooked to PCIe slot 4 */
210 Package(){0x0000FFFF, 0, 0, 16 },
211 Package(){0x0000FFFF, 1, 0, 17 },
212 Package(){0x0000FFFF, 2, 0, 18 },
213 Package(){0x0000FFFF, 3, 0, 19 },
217 /* PCIe slot - Hooked to PCIe slot 5 */
218 Package(){0x0000FFFF, 0, INTB, 0 },
219 Package(){0x0000FFFF, 1, INTC, 0 },
220 Package(){0x0000FFFF, 2, INTD, 0 },
221 Package(){0x0000FFFF, 3, INTA, 0 },
223 Name(APS5, Package(){
224 /* PCIe slot - Hooked to PCIe slot 5 */
225 Package(){0x0000FFFF, 0, 0, 17 },
226 Package(){0x0000FFFF, 1, 0, 18 },
227 Package(){0x0000FFFF, 2, 0, 19 },
228 Package(){0x0000FFFF, 3, 0, 16 },
232 /* PCIe slot - Hooked to PCIe slot 6 */
233 Package(){0x0000FFFF, 0, INTC, 0 },
234 Package(){0x0000FFFF, 1, INTD, 0 },
235 Package(){0x0000FFFF, 2, INTA, 0 },
236 Package(){0x0000FFFF, 3, INTB, 0 },
238 Name(APS6, Package(){
239 /* PCIe slot - Hooked to PCIe slot 6 */
240 Package(){0x0000FFFF, 0, 0, 18 },
241 Package(){0x0000FFFF, 1, 0, 19 },
242 Package(){0x0000FFFF, 2, 0, 16 },
243 Package(){0x0000FFFF, 3, 0, 17 },
247 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
248 Package(){0x0000FFFF, 0, INTD, 0 },
249 Package(){0x0000FFFF, 1, INTA, 0 },
250 Package(){0x0000FFFF, 2, INTB, 0 },
251 Package(){0x0000FFFF, 3, INTC, 0 },
253 Name(APS7, Package(){
254 /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
255 Package(){0x0000FFFF, 0, 0, 19 },
256 Package(){0x0000FFFF, 1, 0, 16 },
257 Package(){0x0000FFFF, 2, 0, 17 },
258 Package(){0x0000FFFF, 3, 0, 18 },
262 /* PCIe slot - Hooked to PCIe slot 10 */
263 Package(){0x0000FFFF, 0, INTA, 0 },
264 Package(){0x0000FFFF, 1, INTB, 0 },
265 Package(){0x0000FFFF, 2, INTC, 0 },
266 Package(){0x0000FFFF, 3, INTD, 0 },
268 Name(APE0, Package(){
269 /* PCIe slot - Hooked to PCIe */
270 Package(){0x0000FFFF, 0, 0, 16 },
271 Package(){0x0000FFFF, 1, 0, 17 },
272 Package(){0x0000FFFF, 2, 0, 18 },
273 Package(){0x0000FFFF, 3, 0, 19 },
277 /* PCIe slot - Hooked to PCIe slot 10 */
278 Package(){0x0000FFFF, 0, INTB, 0 },
279 Package(){0x0000FFFF, 1, INTC, 0 },
280 Package(){0x0000FFFF, 2, INTD, 0 },
281 Package(){0x0000FFFF, 3, INTA, 0 },
283 Name(APE1, Package(){
284 /* PCIe slot - Hooked to PCIe */
285 Package(){0x0000FFFF, 0, 0, 17 },
286 Package(){0x0000FFFF, 1, 0, 18 },
287 Package(){0x0000FFFF, 2, 0, 19 },
288 Package(){0x0000FFFF, 3, 0, 16 },
292 /* PCIe slot - Hooked to PCIe slot 10 */
293 Package(){0x0000FFFF, 0, INTC, 0 },
294 Package(){0x0000FFFF, 1, INTD, 0 },
295 Package(){0x0000FFFF, 2, INTA, 0 },
296 Package(){0x0000FFFF, 3, INTB, 0 },
298 Name(APE2, Package(){
299 /* PCIe slot - Hooked to PCIe */
300 Package(){0x0000FFFF, 0, 0, 18 },
301 Package(){0x0000FFFF, 1, 0, 19 },
302 Package(){0x0000FFFF, 2, 0, 16 },
303 Package(){0x0000FFFF, 3, 0, 17 },
307 /* PCIe slot - Hooked to PCIe slot 10 */
308 Package(){0x0000FFFF, 0, INTD, 0 },
309 Package(){0x0000FFFF, 1, INTA, 0 },
310 Package(){0x0000FFFF, 2, INTB, 0 },
311 Package(){0x0000FFFF, 3, INTC, 0 },
313 Name(APE3, Package(){
314 /* PCIe slot - Hooked to PCIe */
315 Package(){0x0000FFFF, 0, 0, 19 },
316 Package(){0x0000FFFF, 1, 0, 16 },
317 Package(){0x0000FFFF, 2, 0, 17 },
318 Package(){0x0000FFFF, 3, 0, 18 },
321 Name(PCIB, Package(){
322 /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Func 4. */
323 Package(){0x0003FFFF, 0, 0, 0x14 },
324 Package(){0x0003FFFF, 1, 0, 0x15 },
325 Package(){0x0003FFFF, 2, 0, 0x16 },
326 Package(){0x0003FFFF, 3, 0, 0x17 },
327 Package(){0x0004FFFF, 0, 0, 0x15 },
328 Package(){0x0004FFFF, 1, 0, 0x16 },
329 Package(){0x0004FFFF, 2, 0, 0x17 },
330 Package(){0x0004FFFF, 3, 0, 0x14 },
331 Package(){0x0005FFFF, 0, 0, 0x16 },
332 Package(){0x0005FFFF, 1, 0, 0x17 },
333 Package(){0x0005FFFF, 2, 0, 0x14 },
334 Package(){0x0005FFFF, 3, 0, 0x15 },