src/mainboard/lippert/toucan-af/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <AGESA.h>
  16 #include <PlatformMemoryConfiguration.h>
  17
  18 #include <northbridge/amd/agesa/state_machine.h>
  19
  20 static const PCIe_PORT_DESCRIPTOR PortList[] = {
  21         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
  22         {
  23                 0,
  24                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
  25                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
  26                                 HotplugDisabled,
  27                                 PcieGen2,
  28                                 PcieGen2,
  29                                 AspmL0sL1, 0)
  30         },
  31         // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
  32         {
  33                 0,
  34                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
  35                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
  36                                 HotplugDisabled,
  37                                 PcieGen2,
  38                                 PcieGen2,
  39                                 AspmL0sL1, 0)
  40         },
  41         // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
  42         {
  43                 0,
  44                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
  45                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
  46                                 HotplugDisabled,
  47                                 PcieGen2,
  48                                 PcieGen2,
  49                                 AspmL0sL1, 0)
  50         },
  51         // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
  52         {
  53                 0,
  54                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
  55                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
  56                                 HotplugDisabled,
  57                                 PcieGen2,
  58                                 PcieGen2,
  59                                 AspmL0sL1, 0)
  60         },
  61         // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
  62         {
  63                 DESCRIPTOR_TERMINATE_LIST,
  64                 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
  65                 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
  66                                 HotplugDisabled,
  67                                 PcieGen2,
  68                                 PcieGen2,
  69                                 AspmL0sL1, 0)
  70         }
  71 };
  72
  73 static const PCIe_DDI_DESCRIPTOR DdiList[] = {
  74         // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
  75         {
  76                 0,
  77                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
  78                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux1, Hdp1)
  79         },
  80         // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
  81         {
  82                 DESCRIPTOR_TERMINATE_LIST,
  83                 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
  84                 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
  85         }
  86 };
  87
  88 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  89         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  90         .SocketId     = 0,
  91         .PciePortList = PortList,
  92         .DdiLinkList  = DdiList,
  93 };
  94
  95 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  96 {
  97         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
  98         InitEarly->GnbConfig.PsppPolicy         = 0;
  99 }
 100
 101 /*----------------------------------------------------------------------------------------
 102  *                                              CUSTOMER OVERIDES MEMORY TABLE
 103  *----------------------------------------------------------------------------------------
 104  */
 105
 106 /*
 107  *      Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 108  *      (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 109  *      is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 110  *      use its default conservative settings.
 111  */
 112 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 113         HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
 114         NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
 115         NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
 116         PSO_END
 117 };
 118
 119 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 120 {
 121         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 122 }