src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <baseboard/gpio.h>
  16 #include <baseboard/variants.h>
  17 #include <commonlib/helpers.h>
  18
  19 /* Pad configuration in ramstage*/
  20 static const struct pad_config gpio_table[] = {
  21         /* PCH M.2 SSD */
  22         PAD_CFG_GPO(GPP_B16, 1, DEEP),
  23         PAD_CFG_GPO(GPP_H0, 1, DEEP),
  24
  25         /* Camera */
  26         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C3_SDA */
  27         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C3_SCL */
  28         PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* I2C5_SDA */
  29         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* I2C5_SCL */
  30         PAD_CFG_GPO(GPP_B23, 0, DEEP),
  31         PAD_CFG_GPO(GPP_C15, 0, DEEP),
  32         PAD_CFG_GPO(GPP_R6, 0, DEEP),
  33         PAD_CFG_GPO(GPP_H12, 0, DEEP),
  34
  35         /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */
  36         PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
  37         PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),
  38
  39         /* ISH UART0 RX/TX */
  40         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
  41         PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
  42
  43         /* ISH I2C0 */
  44         PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
  45         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  46
  47         /* ISH GPI 0-6 */
  48         PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
  49         PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
  50         PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
  51         PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
  52         PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
  53         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
  54         PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
  55         PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
  56
  57         /* Audio */
  58         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA */
  59         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL */
  60         PAD_CFG_GPO(GPP_C5, 1, DEEP),
  61         PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
  62
  63         /* CNVi */
  64         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),  /* CNV_RF_RST_L */
  65         PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3),  /* CNV_CLKREQ0 */
  66
  67 };
  68
  69 /* Early pad configuration in bootblock */
  70 static const struct pad_config early_gpio_table[] = {
  71         /* Audio */
  72         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),   /* I2S0_HP_SCLK */
  73         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),   /* I2S0_HP_SFRM */
  74         PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_HP_TX */
  75         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),   /* I2S0_HP_RX */
  76
  77         PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),  /* I2S1_SPKR_SCLK */
  78         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),   /* I2S1_SPKR_TX */
  79         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2),   /* I2S1_SPKR_RX */
  80         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2),   /* I2S1_SPKR_SFRM */
  81
  82         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),   /* SNDW0_HP_CLK */
  83         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),   /* SNDW0_HP_DATA */
  84         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),   /* SNDW1_SPKR_CLK */
  85         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),   /* SNDW1_SPKR_DATA */
  86
  87         PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),   /* DMIC1_CLK */
  88         PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),   /* DMIC1_DATA */
  89         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),   /* DMIC0_CLK */
  90         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),   /* DMIC0_DATA */
  91
  92         /* DP */
  93         PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* L_BKLTEN */
  94         PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* L_BKLTCTL */
  95         PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* L_VDDEN */
  96         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* HPD_A */
  97         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* HPD_B */
  98         PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */
  99         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */
 100         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */
 101 };
 102
 103 const struct pad_config *variant_gpio_table(size_t *num)
 104 {
 105         *num = ARRAY_SIZE(gpio_table);
 106         return gpio_table;
 107 }
 108
 109 const struct pad_config *variant_early_gpio_table(size_t *num)
 110 {
 111         *num = ARRAY_SIZE(early_gpio_table);
 112         return early_gpio_table;
 113 }
 114
 115 static const struct cros_gpio cros_gpios[] = {
 116         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
 117 };
 118
 119 const struct cros_gpio *variant_cros_gpios(size_t *num)
 120 {
 121         *num = ARRAY_SIZE(cros_gpios);
 122         return cros_gpios;
 123 }