src/mainboard/intel/strago/smihandler.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <arch/acpi.h>
  16 #include <arch/io.h>
  17 #include <console/console.h>
  18 #include <cpu/x86/smm.h>
  19 #include "ec.h"
  20
  21 #include <ec/google/chromeec/ec.h>
  22 #include <elog.h>
  23
  24 #include <soc/nvs.h>
  25 #include <soc/pm.h>
  26 #include <soc/gpio.h>
  27
  28 #include "onboard.h"
  29
  30 /* The wake gpio is SUS_GPIO[0]. */
  31 #define WAKE_GPIO_EN SUS_GPIO_EN0
  32
  33 int mainboard_io_trap_handler(int smif)
  34 {
  35         switch (smif) {
  36         case 0x99:
  37                 printk(BIOS_DEBUG, "Sample\n");
  38                 smm_get_gnvs()->smif = 0;
  39                 break;
  40         default:
  41                 return 0;
  42         }
  43
  44         /*
  45          * On success, the IO Trap Handler returns 0
  46          * On failure, the IO Trap Handler returns a value != 0
  47          *
  48          * For now, we force the return value to 0 and log all traps to
  49          * see what's going on.
  50          */
  51         //gnvs->smif = 0;
  52         return 1;
  53 }
  54
  55 #if CONFIG(EC_GOOGLE_CHROMEEC)
  56 static uint8_t mainboard_smi_ec(void)
  57 {
  58         uint8_t cmd = google_chromeec_get_event();
  59         uint16_t pmbase = get_pmbase();
  60         uint32_t pm1_cnt;
  61
  62         /* Log this event */
  63         if (cmd)
  64                 elog_gsmi_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
  65
  66         switch (cmd) {
  67         case EC_HOST_EVENT_LID_CLOSED:
  68                 printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
  69
  70                 /* Go to S5 */
  71                 pm1_cnt = inl(pmbase + PM1_CNT);
  72                 pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
  73                 outl(pm1_cnt, pmbase + PM1_CNT);
  74                 break;
  75         }
  76
  77         return cmd;
  78 }
  79 #endif
  80
  81 /*
  82  * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
  83  * this includes the enable bits in the lower 16 bits.
  84  */
  85 void mainboard_smi_gpi(uint32_t alt_gpio_smi)
  86 {
  87 #if CONFIG(EC_GOOGLE_CHROMEEC)
  88         if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
  89                 /* Process all pending events */
  90                 while (mainboard_smi_ec() != 0)
  91                         ;
  92         }
  93 #endif
  94 }
  95
  96 void mainboard_smi_sleep(uint8_t slp_typ)
  97 {
  98         /* Disable USB charging if required */
  99         switch (slp_typ) {
 100         case ACPI_S3:
 101 #if CONFIG(EC_GOOGLE_CHROMEEC)
 102                 if (smm_get_gnvs()->s3u0 == 0)
 103                         google_chromeec_set_usb_charge_mode(
 104                                 0, USB_CHARGE_MODE_DISABLED);
 105                 if (smm_get_gnvs()->s3u1 == 0)
 106                         google_chromeec_set_usb_charge_mode(
 107                                 1, USB_CHARGE_MODE_DISABLED);
 108
 109                 /* Enable wake events */
 110                 google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 111 #endif
 112                 /* Enable wake pin in GPE block. */
 113                 enable_gpe(WAKE_GPIO_EN);
 114                 break;
 115         case ACPI_S5:
 116 #if CONFIG(EC_GOOGLE_CHROMEEC)
 117                 if (smm_get_gnvs()->s5u0 == 0)
 118                         google_chromeec_set_usb_charge_mode(
 119                                 0, USB_CHARGE_MODE_DISABLED);
 120                 if (smm_get_gnvs()->s5u1 == 0)
 121                         google_chromeec_set_usb_charge_mode(
 122                                 1, USB_CHARGE_MODE_DISABLED);
 123
 124                 /* Enable wake events */
 125                 google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
 126 #endif
 127                 break;
 128         }
 129
 130 #if CONFIG(EC_GOOGLE_CHROMEEC)
 131         /* Disable SCI and SMI events */
 132         google_chromeec_set_smi_mask(0);
 133         google_chromeec_set_sci_mask(0);
 134
 135         /* Clear pending events that may trigger immediate wake */
 136         while (google_chromeec_get_event() != 0)
 137                 ;
 138
 139         /* Set LPC lines to low power in S3/S5. */
 140         if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
 141                 lpc_set_low_power();
 142 #endif
 143 }
 144
 145 int mainboard_smi_apmc(uint8_t apmc)
 146 {
 147         switch (apmc) {
 148         case APM_CNT_ACPI_ENABLE:
 149 #if CONFIG(EC_GOOGLE_CHROMEEC)
 150                 google_chromeec_set_smi_mask(0);
 151                 /* Clear all pending events */
 152                 while (google_chromeec_get_event() != 0)
 153                         ;
 154                 google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
 155 #endif
 156                 break;
 157         case APM_CNT_ACPI_DISABLE:
 158 #if CONFIG(EC_GOOGLE_CHROMEEC)
 159                 google_chromeec_set_sci_mask(0);
 160                 /* Clear all pending events */
 161                 while (google_chromeec_get_event() != 0)
 162                         ;
 163                 google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
 164 #endif
 165                 break;
 166         }
 167         return 0;
 168 }