src/mainboard/intel/leafhill/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <string.h>
  16 #include <soc/romstage.h>
  17 #include <fsp/api.h>
  18 #include <FspmUpd.h>
  19 #include "brd_gpio.h"
  20
  21 static const uint8_t Ch0_Bit_swizzling[] = {
  22         0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
  23         0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
  24         0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
  25         0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
  26 };
  27 static const uint8_t Ch1_Bit_swizzling[] = {
  28         0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
  29         0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
  30         0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
  31         0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
  32 };
  33 static const uint8_t Ch2_Bit_swizzling[] = {
  34         0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
  35         0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
  36         0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
  37         0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
  38 };
  39 static const uint8_t Ch3_Bit_swizzling[] = {
  40         0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
  41         0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
  42         0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
  43         0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
  44 };
  45
  46 void mainboard_memory_init_params(FSPM_UPD *memupd)
  47 {
  48         /* setup early gpio before memory */
  49         gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
  50
  51         /* DRAM Config settings */
  52         memupd->FspmConfig.Package = 0x1;
  53         memupd->FspmConfig.Profile = 0xB;
  54         memupd->FspmConfig.MemoryDown = 0x1;
  55         memupd->FspmConfig.DDR3LPageSize = 0x0;
  56         memupd->FspmConfig.DDR3LASR = 0x0;
  57         memupd->FspmConfig.ScramblerSupport = 0x1;
  58         memupd->FspmConfig.ChannelHashMask = 0x36;
  59         memupd->FspmConfig.SliceHashMask = 0x9;
  60         memupd->FspmConfig.InterleavedMode = 0x2;
  61         memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
  62         memupd->FspmConfig.MinRefRate2xEnable = 0x0;
  63         memupd->FspmConfig.DualRankSupportEnable = 0x1;
  64         memupd->FspmConfig.RmtMode = 0x0;
  65         memupd->FspmConfig.MemorySizeLimit = 0x1800;
  66         memupd->FspmConfig.LowMemoryMaxValue = 0x0;
  67         memupd->FspmConfig.DisableFastBoot = 0x0;
  68         memupd->FspmConfig.HighMemoryMaxValue = 0x0;
  69         memupd->FspmConfig.DIMM0SPDAddress = 0x0;
  70         memupd->FspmConfig.DIMM1SPDAddress = 0x0;
  71         memupd->FspmConfig.Ch0_RankEnable = 0x3;
  72         memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
  73         memupd->FspmConfig.Ch0_DramDensity = 0x2;
  74         memupd->FspmConfig.Ch0_Option = 0x3;
  75         memupd->FspmConfig.Ch0_OdtConfig = 0x0;
  76         memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
  77         memupd->FspmConfig.Ch0_Mode2N = 0x0;
  78         memupd->FspmConfig.Ch0_OdtLevels = 0x0;
  79         memupd->FspmConfig.Ch1_RankEnable = 0x3;
  80         memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
  81         memupd->FspmConfig.Ch1_DramDensity = 0x2;
  82         memupd->FspmConfig.Ch1_Option = 0x3;
  83         memupd->FspmConfig.Ch1_OdtConfig = 0x0;
  84         memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
  85         memupd->FspmConfig.Ch1_Mode2N = 0x0;
  86         memupd->FspmConfig.Ch1_OdtLevels = 0x0;
  87         memupd->FspmConfig.Ch2_RankEnable = 0x3;
  88         memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
  89         memupd->FspmConfig.Ch2_DramDensity = 0x2;
  90         memupd->FspmConfig.Ch2_Option = 0x3;
  91         memupd->FspmConfig.Ch2_OdtConfig = 0x0;
  92         memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
  93         memupd->FspmConfig.Ch2_Mode2N = 0x0;
  94         memupd->FspmConfig.Ch2_OdtLevels = 0x0;
  95         memupd->FspmConfig.Ch3_RankEnable = 0x3;
  96         memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
  97         memupd->FspmConfig.Ch3_DramDensity = 0x2;
  98         memupd->FspmConfig.Ch3_Option = 0x3;
  99         memupd->FspmConfig.Ch3_OdtConfig = 0x0;
 100         memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
 101         memupd->FspmConfig.Ch3_Mode2N = 0x0;
 102         memupd->FspmConfig.Ch3_OdtLevels = 0x0;
 103         memupd->FspmConfig.RmtCheckRun = 0x0;
 104         memupd->FspmConfig.MrcDataSaving = 0x0;
 105         memupd->FspmConfig.MrcFastBoot   = 0x0;
 106
 107         memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
 108                 sizeof(Ch0_Bit_swizzling));
 109         memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
 110                 sizeof(Ch1_Bit_swizzling));
 111         memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
 112                 sizeof(Ch2_Bit_swizzling));
 113         memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
 114                 sizeof(Ch3_Bit_swizzling));
 115
 116         memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
 117         memupd->FspmConfig.MsgLevelMask = 0x0;
 118 }