src/mainboard/intel/kunimitsu/cmos.layout

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ##
   5 ## This program is free software; you can redistribute it and/or modify
   6 ## it under the terms of the GNU General Public License as published by
   7 ## the Free Software Foundation; version 2 of the License.
   8 ##
   9 ## This program is distributed in the hope that it will be useful,
  10 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 ## GNU General Public License for more details.
  13 ##
  14
  15 # -----------------------------------------------------------------
  16 entries
  17
  18 #start-bit length  config config-ID    name
  19 #0            8       r       0        seconds
  20 #8            8       r       0        alarm_seconds
  21 #16           8       r       0        minutes
  22 #24           8       r       0        alarm_minutes
  23 #32           8       r       0        hours
  24 #40           8       r       0        alarm_hours
  25 #48           8       r       0        day_of_week
  26 #56           8       r       0        day_of_month
  27 #64           8       r       0        month
  28 #72           8       r       0        year
  29 # -----------------------------------------------------------------
  30 # Status Register A
  31 #80           4       r       0        rate_select
  32 #84           3       r       0        REF_Clock
  33 #87           1       r       0        UIP
  34 # -----------------------------------------------------------------
  35 # Status Register B
  36 #88           1       r       0        auto_switch_DST
  37 #89           1       r       0        24_hour_mode
  38 #90           1       r       0        binary_values_enable
  39 #91           1       r       0        square-wave_out_enable
  40 #92           1       r       0        update_finished_enable
  41 #93           1       r       0        alarm_interrupt_enable
  42 #94           1       r       0        periodic_interrupt_enable
  43 #95           1       r       0        disable_clock_updates
  44 # -----------------------------------------------------------------
  45 # Status Register C
  46 #96           4       r       0        status_c_rsvd
  47 #100          1       r       0        uf_flag
  48 #101          1       r       0        af_flag
  49 #102          1       r       0        pf_flag
  50 #103          1       r       0        irqf_flag
  51 # -----------------------------------------------------------------
  52 # Status Register D
  53 #104          7       r       0        status_d_rsvd
  54 #111          1       r       0        valid_cmos_ram
  55 # -----------------------------------------------------------------
  56 # Diagnostic Status Register
  57 #112          8       r       0        diag_rsvd1
  58
  59 # -----------------------------------------------------------------
  60 0          120       r       0        reserved_memory
  61 #120        264       r       0        unused
  62
  63 # -----------------------------------------------------------------
  64 # RTC_BOOT_BYTE (coreboot hardcoded)
  65 384          1       e       4        boot_option
  66 388          4       h       0        reboot_counter
  67 #390          2       r       0        unused?
  68
  69 # -----------------------------------------------------------------
  70 # coreboot config options: console
  71 #392          3       r       0        unused
  72 395          4       e       6        debug_level
  73 #399          1       r       0        unused
  74
  75 # coreboot config options: cpu
  76 400          1       e       2        hyper_threading
  77 #401          7       r       0        unused
  78
  79 # coreboot config options: southbridge
  80 408          1       e       1        nmi
  81 409          2       e       7        power_on_after_fail
  82 #411          5       r       0        unused
  83
  84 # coreboot config options: bootloader
  85 #Used by ChromeOS:
  86 416        128       r        0        vbnv
  87 #544        440       r       0        unused
  88
  89 # SandyBridge MRC Scrambler Seed values
  90 896         32        r       0        mrc_scrambler_seed
  91 928         32        r       0        mrc_scrambler_seed_s3
  92
  93 # coreboot config options: check sums
  94 984         16       h       0        check_sum
  95 #1000        24       r       0        amd_reserved
  96
  97 # -----------------------------------------------------------------
  98
  99 enumerations
 100
 101 #ID value   text
 102 1     0     Disable
 103 1     1     Enable
 104 2     0     Enable
 105 2     1     Disable
 106 4     0     Fallback
 107 4     1     Normal
 108 6     0     Emergency
 109 6     1     Alert
 110 6     2     Critical
 111 6     3     Error
 112 6     4     Warning
 113 6     5     Notice
 114 6     6     Info
 115 6     7     Debug
 116 6     8     Spew
 117 7     0     Disable
 118 7     1     Enable
 119 7     2     Keep
 120 # -----------------------------------------------------------------
 121 checksums
 122
 123 checksum 392 415 984