src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef _GPIORVP7_H
  16 #define _GPIORVP7_H
  17
  18 #include <soc/gpe.h>
  19 #include <soc/gpio.h>
  20
  21 /* TCA6424A  I/O Expander */
  22 #define IO_EXPANDER_BUS         4
  23 #define IO_EXPANDER_0_ADDR      0x22
  24 #define IO_EXPANDER_P0CONF      0x0C    /* Port 0 conf offset */
  25 #define IO_EXPANDER_P0DOUT      0x04    /* Port 0 data offset */
  26 #define IO_EXPANDER_P1CONF      0x0D
  27 #define IO_EXPANDER_P1DOUT      0x05
  28 #define IO_EXPANDER_P2CONF      0x0E
  29 #define IO_EXPANDER_P2DOUT      0x06
  30 #define IO_EXPANDER_1_ADDR      0x23
  31
  32
  33 /* GPE_EC_WAKE */
  34 #define GPE_EC_WAKE             GPE0_LAN_WAK
  35
  36 /* CHROMEEC in RVP */
  37 #define EC_SCI_GPI              GPP_E16
  38 #define EC_SMI_GPI              GPP_E15
  39 /*
  40  * Gpio based irq for touchpad, 18th index in North Bank
  41  * MAX_DIRECT_IRQ + GPSW_SIZE + 19
  42  */
  43 #define KBLRVP_TOUCHPAD_IRQ     33
  44
  45 #define KBLRVP_TOUCH_IRQ        31
  46
  47 #define BOARD_TOUCHPAD_NAME             "touchpad"
  48 #define BOARD_TOUCHPAD_IRQ              KBLRVP_TOUCHPAD_IRQ
  49 #define BOARD_TOUCHPAD_I2C_BUS          0
  50 #define BOARD_TOUCHPAD_I2C_ADDR         0x20
  51
  52 #define BOARD_TOUCHSCREEN_NAME          "touchscreen"
  53 #define BOARD_TOUCHSCREEN_IRQ           KBLRVP_TOUCH_IRQ
  54 #define BOARD_TOUCHSCREEN_I2C_BUS       0
  55 #define BOARD_TOUCHSCREEN_I2C_ADDR      0x4c
  56
  57 #ifndef __ACPI__
  58
  59 /* Pad configuration in ramstage. */
  60 static const struct pad_config gpio_table[] = {
  61 /* PM_SLP_S0ix_R_N*/    PAD_CFG_GPO(GPP_A7, 1, DEEP),
  62 /* LPC_CLKRUN */        PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
  63 /* PCH_CLK_PCI_TPM */   PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
  64 /* PCH_LPC_CLK */       PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
  65 /* ISH_KB_PROX_INT */   PAD_CFG_GPO(GPP_A12, 1, RSMRST),
  66 /* PCH_SUSPWRACB */     PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  67 /* PCH_SUSACK */        PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1),
  68 /* SD_1P8_SEL */        PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  69 /* SD_PWR_EN */         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  70 /* ACCEL INTERRUPT */   PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  71 /* ISH_GP1 */           PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
  72 /* GYRO_DRDY */         PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
  73 /* FLIP_ACCEL_INT */    PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
  74 /* GYRO_INT */          PAD_CFG_GPO(GPP_A22, 1, DEEP),
  75 /* ISH_GP5 */           PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
  76 /* CORE_VID0 */         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  77 /* CORE_VID1 */         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  78 /* HSJ_MIC_DET */       PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
  79 /* TRACKPAD_INT */      PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
  80 /* BT_RF_KILL */        PAD_CFG_GPO(GPP_B4, 1, DEEP),
  81 /* SRCCLKREQ0# */       PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP),
  82 /* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
  83 /* PM_SLP_S0 */         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  84 /* PCH_PLT_RST */       PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  85 /* GPP_B_14_SPKR */     PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
  86 /* WLAN_PCIE_WAKE */    PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES),
  87 /* TBT_CIO_PLUG_EVT */  PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES),
  88 /* PCH_SLOT1_WAKE_N */  PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES),
  89 /* CCODEC_SPI_CS */     PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
  90 /* CODEC_SPI_CLK */     PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1),
  91 /* CODEC_SPI_MISO */    PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1),
  92 /* CODEC_SPI_MOSI */    PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1),
  93 /* SM1ALERT# */         PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
  94 /* SMB_CLK */           PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
  95 /* SMB_DATA */          PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1),
  96 /* SMBALERT# */         PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
  97 /* M2_WWAN_PWREN */     PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
  98 /* SML0DATA */          PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
  99 /* SML0ALERT# */        PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP),
 100 /* EC_IN_RW */          PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
 101 /* USB_CTL */           PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1),
 102 /* UART0_RXD */         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 103 /* UART0_TXD */         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 104 /* NFC_RST* */          PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
 105 /* EN_PP3300_KEPLER */  PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
 106 /* PCH_MEM_CFG0 */      PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
 107 /* PCH_MEM_CFG1 */      PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 108 /* PCH_MEM_CFG2 */      PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
 109 /* PCH_MEM_CFG3 */      PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
 110 /* I2C0_SDA */          PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 111 /* I2C0_SCL */          PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 112 /* I2C1_SDA */          PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 113 /* I2C1_SCL */          PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 114 /* GD_UART2_RXD */      PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 115 /* GD_UART2_TXD */      PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 116 /* TCH_PNL_PWREN */     PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1),
 117 /* SPI_WP_STATUS */     PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1),
 118 /* ITCH_SPI_CS */       PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
 119 /* ITCH_SPI_CLK */      PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
 120 /* ITCH_SPI_MISO_1 */   PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
 121 /* ITCH_SPI_MISO_0 */   PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
 122 /* CAM_FLASH_STROBE */  PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
 123 /* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 124 /* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 125 /* SH_I2C1_SDA */       PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
 126 /* SH_I2C1_SCL */       PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 127                         PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, DEEP),
 128 /* SD_D3_WAKE */        PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, DEEP),
 129 /* USB_A1_ILIM_SEL */   PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, DEEP),
 130 /* EN_PP3300_DX_CAM */  PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, DEEP),
 131 /* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
 132 /* ISH_UART0_TXD */     PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
 133 /* ISH_UART0_RTS */     PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1),
 134 /* ISH_UART0_CTS */     PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
 135 /* DMIC_CLK_1 */        PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
 136 /* DMIC_DATA_1 */       PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1),
 137 /* DMIC_CLK_0 */        PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 138 /* DMIC_DATA_0 */       PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1),
 139 /* ITCH_SPI_D2 */       PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 140 /* ITCH_SPI_D3 */       PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
 141 /* I2S_MCLK */          PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 142 /* SPI_TPM_IRQ */       PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP),
 143 /* SATAXPCIE1 */        PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 144 /* SSD_PEDET */         PAD_CFG_GPI_GPIO_DRIVER(GPP_E2, NONE, DEEP),
 145 /* CPU_GP0 */           PAD_CFG_GPO(GPP_E3, 1, RSMRST),
 146 /* SATA_DEVSLP1 */      PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
 147 /* SATA_DEVSLP2 */      PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
 148                         PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
 149 /* USB2_OC_0 */         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
 150 /* USB2_OC_1 */         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
 151 /* USB2_OC_2 */         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 152 /* DDI1_HPD */          PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 153 /* DDI2_HPD */          PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 154 /* EC_SMI */            PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
 155 /* EC_SCI */            PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES),
 156 /* EDP_HPD */           PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 157 /* DDPB_CTRLCLK */      PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 158 /* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1),
 159 /* DDPC_CTRLCLK */      PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 160 /* DDPC_CTRLDATA */     PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 161 /* PCH_CODEC_IRQ */     PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
 162 /* TCH_PNL_RST */       PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP),
 163 /* I2S2_SCLK */         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 164 /* I2S2_SFRM */         PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1),
 165 /* I2S2_TXD */          PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
 166 /* I2S2_RXD */          PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1),
 167 /* I2C2_SDA */          PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 168 /* I2C2_SCL */          PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
 169 /* I2C3_SDA */          PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
 170 /* I2C3_SCL */          PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
 171 /* I2C4_SDA */          PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
 172 /* I2C4_SDA */          PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
 173 /* AUDIO_IRQ */         PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2),
 174 /* I2C5_SCL */          PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2),
 175 /* EMMC_CMD */          PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 176 /* EMMC_DATA0 */        PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 177 /* EMMC_DATA1 */        PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
 178 /* EMMC_DATA2 */        PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 179 /* EMMC_DATA3 */        PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 180 /* EMMC_DATA4 */        PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
 181 /* EMMC_DATA5 */        PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
 182 /* EMMC_DATA6 */        PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 183 /* EMMC_DATA7 */        PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 184 /* EMMC_RCLK */         PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 185 /* EMMC_CLK */          PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 186 /* WWAN_UIM_SIM_DET */  PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
 187 /* SD_CMD */            PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
 188 /* SD_DATA0 */          PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
 189 /* SD_DATA1 */          PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
 190 /* SD_DATA2 */          PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
 191 /* SD_DATA3 */          PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
 192 /* SD_CD# */            PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
 193 /* SD_CLK */            PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 194 /* SD_WP */             PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
 195 /* PCH_BATLOW */        PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 196 /* EC_PCH_ACPRESENT */  PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 197 /* EC_PCH_WAKE */       PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 198 /* EC_PCH_PWRBTN */     PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
 199 /* PM_SLP_S3# */        PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 200 /* PM_SLP_S4# */        PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 201 /* PM_SLP_SA# */        PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
 202                         PAD_CFG_NF(GPD7, NONE, DEEP, NF1),
 203 /* PM_SUSCLK */         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 204 /* PCH_SLP_WLAN# */     PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
 205 /* PM_SLP_S5# */        PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
 206 /* LANPHYC */           PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
 207 };
 208
 209 /* Early pad configuration in romstage. */
 210 static const struct pad_config early_gpio_table[] = {
 211 /* UART0_RXD */         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 212 /* UART0_TXD */         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 213 };
 214
 215
 216 #endif
 217
 218 #endif