src/mainboard/intel/harcuvar/devicetree.cb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ##
   5 ## This program is free software; you can redistribute it and/or modify
   6 ## it under the terms of the GNU General Public License as published by
   7 ## the Free Software Foundation; version 2 of the License.
   8 ##
   9 ## This program is distributed in the hope that it will be useful,
  10 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 ## GNU General Public License for more details.
  13 ##
  14
  15 chip soc/intel/denverton_ns
  16
  17         # configure pirq routing
  18         register "pirqa_routing" = "11"
  19         register "pirqb_routing" = "10"
  20         register "pirqc_routing" = "06"
  21         register "pirqd_routing" = "07"
  22         register "pirqe_routing" = "12"
  23         register "pirqf_routing" = "14"
  24         register "pirqg_routing" = "15"
  25         register "pirqh_routing" = "15"
  26         # configure device interrupt routing
  27         register "ir00_routing" = "0x3217" # IR00, Dev31
  28         register "ir01_routing" = "0x3210" # IR01, Dev22
  29         register "ir02_routing" = "0x3211" # IR02, Dev23
  30         register "ir03_routing" = "0x3217" # IR03, Dev5
  31         register "ir04_routing" = "0x3212" # IR04, Dev6
  32         register "ir05_routing" = "0x3210" # IR05, Dev24
  33         register "ir06_routing" = "0x3214" # IR06, Dev19
  34         register "ir07_routing" = "0x3210" # IR07, Dev9/10/11/12
  35         register "ir08_routing" = "0x7654" # IR08, Dev14/15/16/17
  36         register "ir09_routing" = "0x3213" # IR09, Dev21
  37         register "ir10_routing" = "0x3210" # IR10, Dev26/18
  38         register "ir11_routing" = "0x3215" # IR11, Dev20
  39         register "ir12_routing" = "0x3210" # IR12, Dev27
  40         # configure interrupt polarity control
  41         register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
  42         register "ipc1" = "0x00000000" # IPC1
  43         register "ipc2" = "0x00000000" # IPC2
  44         register "ipc3" = "0x00000000" # IPC3
  45
  46         device cpu_cluster 0 on
  47                 device lapic 0 on end
  48         end
  49
  50         device domain 0 on
  51                 device pci 00.0 on end # Host Bridge
  52                 device pci 04.0 on end # RAS
  53                 device pci 05.0 on end # RCEC(Root Complex Event Collector)
  54                 device pci 06.0 on end # Virtual root port 2 (QAT)
  55                 device pci 09.0 on end # PCI Express Port 0, cluster #0, x8
  56                 device pci 0e.0 on end # PCI Express Port 4, cluster #1, x4
  57                 device pci 10.0 on end # PCI Express Port 6, cluster #1, x4
  58                 device pci 12.0 on end # SMBus Controller 1
  59                 device pci 14.0 on end # SATA Controller 1
  60                 device pci 15.0 on end # XHCI USB Controller
  61                 device pci 16.0 on end # Virtual root port 0 (10GBE0)
  62                 device pci 17.0 on end # Virtual root port 1 (10GBE1)
  63                 device pci 18.0 on end # CSME HECI 1
  64                 device pci 1a.0 on end # UART 0
  65                 device pci 1a.1 on end # UART 1
  66                 device pci 1a.2 on end # UART 2
  67                 device pci 1c.0 on end # eMMC
  68                 device pci 1f.0 on end # LPC bridge
  69                 device pci 1f.2 on end # PMC/ACPI
  70                 device pci 1f.4 on end # SMBus Controller 0
  71                 device pci 1f.5 on end # SPI Controller
  72         end
  73 end