soc/intel/tigerlake: Add PMC mux control
[coreboot.git] / src / device / mmio.c
blobce0514256b82ac7ac1af0b5e71940d6988a72c5b
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* This file is part of the coreboot project. */
4 #include <assert.h>
5 #include <device/mmio.h>
7 /* Helper functions for various MMIO access patterns. */
9 void buffer_from_fifo32(void *buffer, size_t size, void *fifo,
10 int fifo_stride, int fifo_width)
12 u8 *p = buffer;
13 int i, j;
15 assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
16 fifo_stride % sizeof(u32) == 0);
18 for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) {
19 u32 val = read32(fifo);
20 for (j = 0; j < MIN(size - i, fifo_width); j++)
21 *p++ = (u8)(val >> (j * 8));
25 void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
26 void *fifo, int fifo_stride, int fifo_width)
28 u8 *p = buffer;
29 int i, j = prefsz;
31 assert(fifo_width > 0 && fifo_width <= sizeof(u32) &&
32 fifo_stride % sizeof(u32) == 0 && prefsz <= fifo_width);
34 uint32_t val = prefix;
35 for (i = 0; i < size; i += fifo_width, fifo += fifo_stride) {
36 for (; j < MIN(size - i, fifo_width); j++)
37 val |= *p++ << (j * 8);
38 write32(fifo, val);
39 val = 0;
40 j = 0;