src/include/spd.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * Serial Presence Detect (SPD) data stored on SDRAM modules.
   5  *
   6  * Datasheet:
   7  *   - Name: PC SDRAM Serial Presence Detect (SPD) Specification
   8  *           Revision 1.2A, December, 1997
   9  *   - PDF: http://www.intel.com/design/chipsets/memory/spdsd12a.pdf
  10  *
  11  * Datasheet (alternative):
  12  *   - Name: SERIAL PRESENCE DETECT STANDARD, General Standard
  13  *           JEDEC Standard No. 21-C
  14  *     Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3):
  15  *   - PDF: http://www.jedec.org/download/search/4_01_02_10R17.pdf
  16  */
  17
  18 #ifndef _SPD_H_
  19 #define _SPD_H_
  20
  21 /* Byte numbers. */
  22 /* Number of bytes used by module manufacturer */
  23 #define SPD_NUM_MANUFACTURER_BYTES          0
  24 #define SPD_TOTAL_SPD_MEMORY_SIZE           1  /* Total SPD memory size */
  25 #define SPD_MEMORY_TYPE                     2  /* (Fundamental) memory type */
  26 #define SPD_NUM_ROWS                        3  /* Number of row address bits */
  27 /* Number of column address bits */
  28 #define SPD_NUM_COLUMNS                     4
  29 /* Number of module rows (banks) */
  30 #define SPD_NUM_DIMM_BANKS                  5
  31 #define SPD_MODULE_DATA_WIDTH_LSB           6  /* Module data width (LSB) */
  32 #define SPD_MODULE_DATA_WIDTH_MSB           7  /* Module data width (MSB) */
  33 /* Module interface signal levels */
  34 #define SPD_MODULE_VOLTAGE                  8
  35 /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
  36 #define SPD_MIN_CYCLE_TIME_AT_CAS_MAX       9
  37 /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac,
  38  * tCAC)
  39  */
  40 #define SPD_ACCESS_TIME_FROM_CLOCK          10
  41 #define SPD_DIMM_CONFIG_TYPE                11 /* Module configuration type */
  42 #define SPD_REFRESH                         12 /* Refresh rate/type */
  43 #define SPD_PRIMARY_SDRAM_WIDTH             13 /* SDRAM width (primary SDRAM) */
  44 /* Error checking SDRAM (data) width */
  45 #define SPD_ERROR_CHECKING_SDRAM_WIDTH      14
  46 /* SDRAM device attributes, minimum clock delay for back to back random
  47  * column
  48  */
  49 #define SPD_MIN_CLOCK_DELAY_B2B_RAND_COLUMN 15
  50 /* SDRAM device attributes, burst lengths supported */
  51 #define SPD_SUPPORTED_BURST_LENGTHS         16
  52 /* SDRAM device attributes, number of banks on SDRAM device */
  53 #define SPD_NUM_BANKS_PER_SDRAM             17
  54 /* SDRAM device attributes, CAS latency */
  55 #define SPD_ACCEPTABLE_CAS_LATENCIES        18
  56 /* SDRAM device attributes, CS latency */
  57 #define SPD_CS_LATENCY                      19
  58 /* SDRAM device attributes, WE latency */
  59 #define SPD_WE_LATENCY                      20
  60 #define SPD_MODULE_ATTRIBUTES               21 /* SDRAM module attributes */
  61 /* SDRAM device attributes, general */
  62 #define SPD_DEVICE_ATTRIBUTES_GENERAL       22
  63 /* SDRAM cycle time (2nd highest CAS latency) */
  64 #define SPD_SDRAM_CYCLE_TIME_2ND            23
  65 /* SDRAM access from clock (2nd highest CAS latency) */
  66 #define SPD_ACCESS_TIME_FROM_CLOCK_2ND      24
  67 /* SDRAM cycle time (3rd highest CAS latency) */
  68 #define SPD_SDRAM_CYCLE_TIME_3RD            25
  69 /* SDRAM access from clock (3rd highest CAS latency) */
  70 #define SPD_ACCESS_TIME_FROM_CLOCK_3RD      26
  71 /* Minimum row precharge time (Trp) */
  72 #define SPD_MIN_ROW_PRECHARGE_TIME          27
  73 /* Minimum row active to row active (Trrd) */
  74 #define SPD_MIN_ROWACTIVE_TO_ROWACTIVE      28
  75 /* Minimum RAS to CAS delay (Trcd) */
  76 #define SPD_MIN_RAS_TO_CAS_DELAY            29
  77 /* Minimum RAS pulse width (Tras) */
  78 #define SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY   30
  79 /* Density of each row on module */
  80 #define SPD_DENSITY_OF_EACH_ROW_ON_MODULE   31
  81 /* Command and address signal input setup time */
  82 #define SPD_CMD_SIGNAL_INPUT_SETUP_TIME     32
  83 /* Command and address signal input hold time */
  84 #define SPD_CMD_SIGNAL_INPUT_HOLD_TIME      33
  85 /* Data signal input setup time */
  86 #define SPD_DATA_SIGNAL_INPUT_SETUP_TIME    34
  87 #define SPD_DATA_SIGNAL_INPUT_HOLD_TIME     35 /* Data signal input hold time */
  88 #define SPD_WRITE_RECOVERY_TIME             36 /* Write recovery time (tWR) */
  89 /* Internal write to read command delay (tWTR) */
  90 #define SPD_INT_WRITE_TO_READ_DELAY         37
  91 /* Internal read to precharge command delay (tRTP) */
  92 #define SPD_INT_READ_TO_PRECHARGE_DELAY     38
  93 /* Memory analysis probe characteristics */
  94 #define SPD_MEM_ANALYSIS_PROBE_PARAMS       39
  95 /* Extension of byte 41 (tRC) and byte 42 (tRFC) */
  96 #define SPD_BYTE_41_42_EXTENSION            40
  97 /* Minimum active to active auto refresh (tRCmin) */
  98 #define SPD_MIN_ACT_TO_ACT_AUTO_REFRESH     41
  99 /* Minimum auto refresh to active/auto refresh (tRFC) */
 100 #define SPD_MIN_AUTO_REFRESH_TO_ACT         42
 101 /* Maximum device cycle time (tCKmax) */
 102 #define SPD_MAX_DEVICE_CYCLE_TIME           43
 103 /* Maximum skew between DQS and DQ (tDQSQ) */
 104 #define SPD_MAX_DQS_DQ_SKEW                 44
 105 /* Maximum read data-hold skew factor (tQHS) */
 106 #define SPD_MAX_READ_DATAHOLD_SKEW          45
 107 #define SPD_PLL_RELOCK_TIME                 46 /* PLL relock time */
 108 #define SPD_SPD_DATA_REVISION_CODE          62 /* SPD data revision code */
 109 #define SPD_CHECKSUM_FOR_BYTES_0_TO_62      63 /* Checksum for bytes 0-62 */
 110 /* Manufacturer's JEDEC ID code, per EIA/JEP106 (bytes 64-71) */
 111 #define SPD_MANUFACTURER_JEDEC_ID_CODE      64
 112 #define SPD_MANUFACTURING_LOCATION          72 /* Manufacturing location */
 113 /* Manufacturer's part number, in 6-bit ASCII (bytes 73-90) */
 114 #define SPD_MANUFACTURER_PART_NUMBER        73
 115 #define SPD_REVISION_CODE                   91 /* Revision code (bytes 91-92) */
 116 /* Manufacturing date (byte 93: year, byte 94: week) */
 117 #define SPD_MANUFACTURING_DATE              93
 118 /* Assembly serial number (bytes 95-98) */
 119 #define SPD_ASSEMBLY_SERIAL_NUMBER          95
 120 /* Manufacturer specific data (bytes 99-125) */
 121 #define SPD_MANUFACTURER_SPECIFIC_DATA      99
 122 /* Intel specification for frequency */
 123 #define SPD_INTEL_SPEC_FOR_FREQUENCY       126
 124 /* Intel specification details for 100MHz support */
 125 #define SPD_INTEL_SPEC_100_MHZ             127
 126
 127 /* DRAM specifications use the following naming conventions for SPD locations */
 128 #define SPD_tRP                             SPD_MIN_ROW_PRECHARGE_TIME
 129 #define SPD_tRRD                            SPD_MIN_ROWACTIVE_TO_ROWACTIVE
 130 #define SPD_tRCD                            SPD_MIN_RAS_TO_CAS_DELAY
 131 #define SPD_tRAS                            SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY
 132 #define SPD_BANK_DENSITY                    SPD_DENSITY_OF_EACH_ROW_ON_MODULE
 133 #define SPD_ADDRESS_CMD_HOLD                SPD_CMD_SIGNAL_INPUT_HOLD_TIME
 134 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */
 135 #define SPD_tRC                             41
 136 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
 137 #define SPD_tRFC                            42
 138
 139 /* SPD_MEMORY_TYPE values. */
 140 enum spd_memory_type {
 141         SPD_MEMORY_TYPE_UNDEFINED               = 0x00,
 142         SPD_MEMORY_TYPE_FPM_DRAM                = 0x01,
 143         SPD_MEMORY_TYPE_EDO                     = 0x02,
 144         SPD_MEMORY_TYPE_PIPELINED_NIBBLE        = 0x03,
 145         SPD_MEMORY_TYPE_SDRAM                   = 0x04,
 146         SPD_MEMORY_TYPE_MULTIPLEXED_ROM         = 0x05,
 147         SPD_MEMORY_TYPE_SGRAM_DDR               = 0x06,
 148         SPD_MEMORY_TYPE_SDRAM_DDR               = 0x07,
 149         SPD_MEMORY_TYPE_SDRAM_DDR2              = 0x08,
 150         SPD_MEMORY_TYPE_FBDIMM_DDR2             = 0x09,
 151         SPD_MEMORY_TYPE_FB_PROBE_DDR2           = 0x0a,
 152         SPD_MEMORY_TYPE_SDRAM_DDR3              = 0x0b,
 153         SPD_MEMORY_TYPE_DDR4_SDRAM              = 0x0c,
 154         SPD_MEMORY_TYPE_DDR4E_SDRAM             = 0x0e,
 155         SPD_MEMORY_TYPE_LPDDR3_SDRAM            = 0x0f,
 156         SPD_MEMORY_TYPE_LPDDR4_SDRAM            = 0x10,
 157 };
 158
 159 /* SPD_MODULE_VOLTAGE values. */
 160 #define SPD_VOLTAGE_TTL                  0 /* 5.0 Volt/TTL */
 161 #define SPD_VOLTAGE_LVTTL                1 /* LVTTL */
 162 #define SPD_VOLTAGE_HSTL                 2 /* HSTL 1.5 */
 163 #define SPD_VOLTAGE_SSTL3                3 /* SSTL 3.3 */
 164 #define SPD_VOLTAGE_SSTL2                4 /* SSTL 2.5 */
 165 #define SPD_VOLTAGE_SSTL1                5 /* SSTL 1.8 */
 166
 167 /* SPD_DIMM_CONFIG_TYPE values. */
 168 #define ERROR_SCHEME_NONE                0
 169 #define ERROR_SCHEME_PARITY              1
 170 #define ERROR_SCHEME_ECC                 2
 171
 172 /* SPD_ACCEPTABLE_CAS_LATENCIES values. */
 173 // TODO: Check values.
 174 #define SPD_CAS_LATENCY_1_0              0x01
 175 #define SPD_CAS_LATENCY_1_5              0x02
 176 #define SPD_CAS_LATENCY_2_0              0x04
 177 #define SPD_CAS_LATENCY_2_5              0x08
 178 #define SPD_CAS_LATENCY_3_0              0x10
 179 #define SPD_CAS_LATENCY_3_5              0x20
 180 #define SPD_CAS_LATENCY_4_0              0x40
 181
 182 #define SPD_CAS_LATENCY_DDR2_2          (1 << 2)
 183 #define SPD_CAS_LATENCY_DDR2_3          (1 << 3)
 184 #define SPD_CAS_LATENCY_DDR2_4          (1 << 4)
 185 #define SPD_CAS_LATENCY_DDR2_5          (1 << 5)
 186 #define SPD_CAS_LATENCY_DDR2_6          (1 << 6)
 187 #define SPD_CAS_LATENCY_DDR2_7          (1 << 7)
 188
 189 /* SPD_SUPPORTED_BURST_LENGTHS values. */
 190 #define SPD_BURST_LENGTH_1               1
 191 #define SPD_BURST_LENGTH_2               2
 192 #define SPD_BURST_LENGTH_4               4
 193 #define SPD_BURST_LENGTH_8               8
 194 #define SPD_BURST_LENGTH_PAGE            (1 << 7)
 195
 196 /* SPD_MODULE_ATTRIBUTES values. */
 197 #define MODULE_BUFFERED                  1
 198 #define MODULE_REGISTERED                2
 199
 200 #define SPD_UNDEFINED 0x00
 201 #define SPD_ECC_8BIT (1<<3)
 202 #define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
 203
 204 /* Byte 3: Module type information */
 205 enum ddr2_module_type {
 206         DDR2_SPD_RDIMM = 0x01,
 207         DDR2_SPD_UDIMM = 0x02,
 208         DDR2_SPD_SODIMM = 0x04,
 209         DDR2_SPD_72B_SO_CDIMM = 0x06,
 210         DDR2_SPD_72B_SO_RDIMM = 0x07,
 211         DDR2_SPD_MICRO_DIMM = 0x08,
 212         DDR2_SPD_MINI_RDIMM = 0x10,
 213         DDR2_SPD_MINI_UDIMM = 0x20,
 214 };
 215
 216 enum ddr3_module_type {
 217         DDR3_SPD_RDIMM = 0x01,
 218         DDR3_SPD_UDIMM = 0x02,
 219         DDR3_SPD_SODIMM = 0x03,
 220         DDR3_SPD_MICRO_DIMM = 0x04,
 221         DDR3_SPD_MINI_RDIMM = 0x05,
 222         DDR3_SPD_MINI_UDIMM = 0x06,
 223         DDR3_SPD_MINI_CDIMM = 0x07,
 224         DDR3_SPD_72B_SO_UDIMM = 0x08,
 225         DDR3_SPD_72B_SO_RDIMM = 0x09,
 226         DDR3_SPD_72B_SO_CDIMM = 0x0a,
 227         DDR3_SPD_LRDIMM = 0x0b,
 228         DDR3_SPD_16B_SO_DIMM = 0x0c,
 229         DDR3_SPD_32B_SO_RDIMM = 0x0d,
 230 };
 231
 232 enum ddr4_module_type {
 233         DDR4_SPD_RDIMM = 0x01,
 234         DDR4_SPD_UDIMM = 0x02,
 235         DDR4_SPD_SODIMM = 0x03,
 236         DDR4_SPD_LRDIMM = 0x04,
 237         DDR4_SPD_MINI_RDIMM = 0x05,
 238         DDR4_SPD_MINI_UDIMM = 0x06,
 239         DDR4_SPD_72B_SO_UDIMM = 0x08,
 240         DDR4_SPD_72B_SO_RDIMM = 0x09,
 241         DDR4_SPD_16B_SO_DIMM = 0x0c,
 242         DDR4_SPD_32B_SO_RDIMM = 0x0d,
 243 };
 244
 245 enum ddr5_module_type {
 246         DDR5_SPD_RDIMM = 0x01,
 247         DDR5_SPD_UDIMM = 0x02,
 248         DDR5_SPD_SODIMM = 0x03,
 249         DDR5_SPD_LRDIMM = 0x04,
 250         DDR5_SPD_MINI_RDIMM = 0x05,
 251         DDR5_SPD_MINI_UDIMM = 0x06,
 252         DDR5_SPD_72B_SO_UDIMM = 0x08,
 253         DDR5_SPD_72B_SO_RDIMM = 0x09,
 254         DDR5_SPD_SOLDERED_DOWN = 0x0b,
 255         DDR5_SPD_16B_SO_DIMM = 0x0c,
 256         DDR5_SPD_32B_SO_RDIMM = 0x0d,
 257         DDR5_SPD_1DPC = 0x0e,
 258         DDR5_SPD_2DPC = 0x0f,
 259 };
 260
 261 enum lpx_module_type {
 262         LPX_SPD_LPDIMM = 0x07,
 263         LPX_SPD_NONDIMM = 0x0e,
 264 };
 265
 266 #endif