src/soc/intel/apollolake/chip.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <bootsplash.h>
   5 #include <bootstate.h>
   6 #include <cbmem.h>
   7 #include <console/console.h>
   8 #include <cpu/x86/mp.h>
   9 #include <device/mmio.h>
  10 #include <device/device.h>
  11 #include <device/pci.h>
  12 #include <device/pci_ops.h>
  13 #include <intelblocks/acpi.h>
  14 #include <intelblocks/cfg.h>
  15 #include <intelblocks/fast_spi.h>
  16 #include <intelblocks/msr.h>
  17 #include <intelblocks/p2sb.h>
  18 #include <intelblocks/power_limit.h>
  19 #include <intelblocks/xdci.h>
  20 #include <fsp/api.h>
  21 #include <fsp/util.h>
  22 #include <intelblocks/cpulib.h>
  23 #include <intelblocks/gpio.h>
  24 #include <intelblocks/itss.h>
  25 #include <intelblocks/pmclib.h>
  26 #include <soc/cpu.h>
  27 #include <soc/heci.h>
  28 #include <soc/intel/common/vbt.h>
  29 #include <soc/iomap.h>
  30 #include <soc/itss.h>
  31 #include <soc/msr.h>
  32 #include <soc/pci_devs.h>
  33 #include <soc/pm.h>
  34 #include <soc/systemagent.h>
  35 #include <spi-generic.h>
  36 #include <timer.h>
  37 #include <soc/ramstage.h>
  38 #include <soc/soc_chip.h>
  39 #include <types.h>
  40
  41 #include "chip.h"
  42
  43 #define DUAL_ROLE_CFG0          0x80d8
  44 #define SW_VBUS_VALID_MASK      (1 << 24)
  45 #define SW_IDPIN_EN_MASK        (1 << 21)
  46 #define SW_IDPIN_MASK           (1 << 20)
  47 #define SW_IDPIN_HOST           (0 << 20)
  48 #define DUAL_ROLE_CFG1          0x80dc
  49 #define DRD_MODE_MASK           (1 << 29)
  50 #define DRD_MODE_HOST           (1 << 29)
  51
  52 #define CFG_XHCLKGTEN           0x8650
  53 /* Naking USB2.0 EPs for Backbone Clock Gating and PLL Shutdown */
  54 #define NUEFBCGPS               (1 << 28)
  55 /* SRAM Power Gate Enable */
  56 #define SRAMPGTEN               (1 << 27)
  57 /* SS Link PLL Shutdown Enable */
  58 #define SSLSE                   (1 << 26)
  59 /* USB2 PLL Shutdown Enable */
  60 #define USB2PLLSE               (1 << 25)
  61 /* IOSF Sideband Trunk Clock Gating Enable */
  62 #define IOSFSTCGE               (1 << 24)
  63 /* BIT[23:20] HS Backbone PXP Trunk Clock Gate Enable */
  64 #define HSTCGE                  (1 << 23 | 1 << 22)
  65 /* BIT[19:16] SS Backbone PXP Trunk Clock Gate Enable */
  66 #define SSTCGE                  (1 << 19 | 1 << 18 | 1 << 17)
  67 /* XHC Ignore_EU3S */
  68 #define XHCIGEU3S               (1 << 15)
  69 /* XHC Frame Timer Clock Shutdown Enable */
  70 #define XHCFTCLKSE              (1 << 14)
  71 /* XHC Backbone PXP Trunk Clock Gate In Presence of ISOCH EP */
  72 #define XHCBBTCGIPISO           (1 << 13)
  73 /* XHC HS Backbone PXP Trunk Clock Gate U2 non RWE */
  74 #define XHCHSTCGU2NRWE          (1 << 12)
  75 /* BIT[11:10] XHC USB2 PLL Shutdown Lx Enable */
  76 #define XHCUSB2PLLSDLE          (1 << 11 | 1 << 10)
  77 /* BIT[9:8] HS Backbone PXP PLL Shutdown Ux Enable */
  78 #define HSUXDMIPLLSE            (1 << 9)
  79 /* BIT[7:5] SS Backbone PXP PLL shutdown Ux Enable */
  80 #define SSPLLSUE                (1 << 6)
  81 /* XHC Backbone Local Clock Gating Enable */
  82 #define XHCBLCGE                (1 << 4)
  83 /* HS Link Trunk Clock Gating Enable */
  84 #define HSLTCGE                 (1 << 3)
  85 /* SS Link Trunk Clock Gating Enable */
  86 #define SSLTCGE                 (1 << 2)
  87 /* IOSF Backbone Trunk Clock Gating Enable */
  88 #define IOSFBTCGE               (1 << 1)
  89 /* IOSF Gasket Backbone Local Clock Gating Enable */
  90 #define IOSFGBLCGE              (1 << 0)
  91
  92 #define CFG_XHCPMCTRL           0x80a4
  93 /* BIT[7:4] LFPS periodic sampling for USB3 Ports */
  94 #define LFPS_PM_DISABLE_MASK    0xFFFFFF0F
  95
  96 const char *soc_acpi_name(const struct device *dev)
  97 {
  98         if (dev->path.type == DEVICE_PATH_DOMAIN)
  99                 return "PCI0";
 100
 101         if (dev->path.type == DEVICE_PATH_USB) {
 102                 switch (dev->path.usb.port_type) {
 103                 case 0:
 104                         /* Root Hub */
 105                         return "RHUB";
 106                 case 2:
 107                         /* USB2 ports */
 108                         switch (dev->path.usb.port_id) {
 109                         case 0: return "HS01";
 110                         case 1: return "HS02";
 111                         case 2: return "HS03";
 112                         case 3: return "HS04";
 113                         case 4: return "HS05";
 114                         case 5: return "HS06";
 115                         case 6: return "HS07";
 116                         case 7: return "HS08";
 117                         case 8:
 118                                 if (CONFIG(SOC_INTEL_GEMINILAKE))
 119                                         return "HS09";
 120                         }
 121                         break;
 122                 case 3:
 123                         /* USB3 ports */
 124                         switch (dev->path.usb.port_id) {
 125                         case 0: return "SS01";
 126                         case 1: return "SS02";
 127                         case 2: return "SS03";
 128                         case 3: return "SS04";
 129                         case 4: return "SS05";
 130                         case 5: return "SS06";
 131                         }
 132                         break;
 133                 }
 134                 return NULL;
 135         }
 136
 137         if (dev->path.type != DEVICE_PATH_PCI)
 138                 return NULL;
 139
 140         switch (dev->path.pci.devfn) {
 141         /* DSDT: acpi/northbridge.asl */
 142         case SA_DEVFN_ROOT:
 143                 return "MCHC";
 144         /* DSDT: acpi/xhci.asl */
 145         case PCH_DEVFN_XHCI:
 146                 return "XHCI";
 147         /* DSDT: acpi/pch_hda.asl */
 148         case PCH_DEVFN_HDA:
 149                 return "HDAS";
 150         /* DSDT: acpi/lpss.asl */
 151         case PCH_DEVFN_UART0:
 152                 return "URT1";
 153         case PCH_DEVFN_UART1:
 154                 return "URT2";
 155         case PCH_DEVFN_UART2:
 156                 return "URT3";
 157         case PCH_DEVFN_UART3:
 158                 return "URT4";
 159         case PCH_DEVFN_SPI0:
 160                 return "SPI1";
 161         case PCH_DEVFN_SPI1:
 162                 return "SPI2";
 163         case PCH_DEVFN_SPI2:
 164                 return "SPI3";
 165         case PCH_DEVFN_PWM:
 166                 return "PWM";
 167         case PCH_DEVFN_I2C0:
 168                 return "I2C0";
 169         case PCH_DEVFN_I2C1:
 170                 return "I2C1";
 171         case PCH_DEVFN_I2C2:
 172                 return "I2C2";
 173         case PCH_DEVFN_I2C3:
 174                 return "I2C3";
 175         case PCH_DEVFN_I2C4:
 176                 return "I2C4";
 177         case PCH_DEVFN_I2C5:
 178                 return "I2C5";
 179         case PCH_DEVFN_I2C6:
 180                 return "I2C6";
 181         case PCH_DEVFN_I2C7:
 182                 return "I2C7";
 183         /* Storage */
 184         case PCH_DEVFN_SDCARD:
 185                 return "SDCD";
 186         case PCH_DEVFN_EMMC:
 187                 return "EMMC";
 188         case PCH_DEVFN_SDIO:
 189                 return "SDIO";
 190         /* PCIe */
 191         case PCH_DEVFN_PCIE1:
 192                 return "RP03";
 193         case PCH_DEVFN_PCIE5:
 194                 return "RP01";
 195         }
 196
 197         return NULL;
 198 }
 199
 200 static struct device_operations pci_domain_ops = {
 201         .read_resources = pci_domain_read_resources,
 202         .set_resources = pci_domain_set_resources,
 203         .scan_bus = pci_domain_scan_bus,
 204         .acpi_name = &soc_acpi_name,
 205 };
 206
 207 static struct device_operations cpu_bus_ops = {
 208         .read_resources = noop_read_resources,
 209         .set_resources = noop_set_resources,
 210         .init = apollolake_init_cpus,
 211         .acpi_fill_ssdt = generate_cpu_entries,
 212 };
 213
 214 static void enable_dev(struct device *dev)
 215 {
 216         /* Set the operations if it is a special bus type */
 217         if (dev->path.type == DEVICE_PATH_DOMAIN)
 218                 dev->ops = &pci_domain_ops;
 219         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
 220                 dev->ops = &cpu_bus_ops;
 221         else if (dev->path.type == DEVICE_PATH_GPIO)
 222                 block_gpio_enable(dev);
 223 }
 224
 225 /*
 226  * If the PCIe root port at function 0 is disabled,
 227  * the PCIe root ports might be coalesced after FSP silicon init.
 228  * The below function will swap the devfn of the first enabled device
 229  * in devicetree and function 0 resides a pci device
 230  * so that it won't confuse coreboot.
 231  */
 232 static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
 233 {
 234         struct device *func0;
 235         unsigned int devfn;
 236         int i;
 237         unsigned int inc = PCI_DEVFN(0, 1);
 238
 239         func0 = pcidev_path_on_root(devfn0);
 240         if (func0 == NULL)
 241                 return;
 242
 243         /* No more functions if function 0 is disabled. */
 244         if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff)
 245                 return;
 246
 247         devfn = devfn0 + inc;
 248
 249         /*
 250          * Increase function by 1.
 251          * Then find first enabled device to replace func0
 252          * as that port was move to func0.
 253          */
 254         for (i = 1; i < num_funcs; i++, devfn += inc) {
 255                 struct device *dev = pcidev_path_on_root(devfn);
 256                 if (dev == NULL)
 257                         continue;
 258
 259                 if (!dev->enabled)
 260                         continue;
 261                 /* Found the first enabled device in given dev number */
 262                 func0->path.pci.devfn = dev->path.pci.devfn;
 263                 dev->path.pci.devfn = devfn0;
 264                 break;
 265         }
 266 }
 267
 268 static void pcie_override_devicetree_after_silicon_init(void)
 269 {
 270         pcie_update_device_tree(PCH_DEVFN_PCIE1, 4);
 271         pcie_update_device_tree(PCH_DEVFN_PCIE5, 2);
 272 }
 273
 274 /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */
 275 static void set_sci_irq(void)
 276 {
 277         struct soc_intel_apollolake_config *cfg;
 278         uint32_t scis;
 279
 280         cfg = config_of_soc();
 281
 282         /* Change only if a device tree entry exists. */
 283         if (cfg->sci_irq) {
 284                 scis = soc_read_sci_irq_select();
 285                 scis &= ~SCI_IRQ_SEL;
 286                 scis |= (cfg->sci_irq << SCI_IRQ_ADJUST) & SCI_IRQ_SEL;
 287                 soc_write_sci_irq_select(scis);
 288         }
 289 }
 290
 291 static void soc_init(void *data)
 292 {
 293         struct soc_power_limits_config *soc_config;
 294         config_t *config;
 295
 296         /* Snapshot the current GPIO IRQ polarities. FSP is setting a
 297          * default policy that doesn't honor boards' requirements. */
 298         itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 299
 300         /*
 301          * Clear the GPI interrupt status and enable registers. These
 302          * registers do not get reset to default state when booting from S5.
 303          */
 304         gpi_clear_int_cfg();
 305
 306         fsp_silicon_init();
 307
 308         /* Restore GPIO IRQ polarities back to previous settings. */
 309         itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
 310
 311         /* override 'enabled' setting in device tree if needed */
 312         pcie_override_devicetree_after_silicon_init();
 313
 314         /*
 315          * Keep the P2SB device visible so it and the other devices are
 316          * visible in coreboot for driver support and PCI resource allocation.
 317          * There is a UPD setting for this, but it's more consistent to use
 318          * hide and unhide symmetrically.
 319          */
 320         p2sb_unhide();
 321
 322         if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
 323                 printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
 324         } else {
 325                 config = config_of_soc();
 326                 /* Set RAPL MSR for Package power limits */
 327                 soc_config = &config->power_limits_config;
 328                 set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
 329         }
 330
 331         /*
 332         * FSP-S routes SCI to IRQ 9. With the help of this function you can
 333         * select another IRQ for SCI.
 334         */
 335         set_sci_irq();
 336 }
 337
 338 static void soc_final(void *data)
 339 {
 340         /* Make sure payload/OS can't trigger global reset */
 341         pmc_global_reset_disable_and_lock();
 342 }
 343
 344 static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
 345 {
 346         switch (dev->path.pci.devfn) {
 347         case PCH_DEVFN_NPK:
 348                 /*
 349                  * Disable this device in the parse_devicetree_setting() function
 350                  * in romstage.c
 351                  */
 352                 break;
 353         case PCH_DEVFN_ISH:
 354                 silconfig->IshEnable = 0;
 355                 break;
 356         case PCH_DEVFN_SATA:
 357                 silconfig->EnableSata = 0;
 358                 break;
 359         case PCH_DEVFN_PCIE5:
 360                 silconfig->PcieRootPortEn[0] = 0;
 361                 silconfig->PcieRpHotPlug[0] = 0;
 362                 break;
 363         case PCH_DEVFN_PCIE6:
 364                 silconfig->PcieRootPortEn[1] = 0;
 365                 silconfig->PcieRpHotPlug[1] = 0;
 366                 break;
 367         case PCH_DEVFN_PCIE1:
 368                 silconfig->PcieRootPortEn[2] = 0;
 369                 silconfig->PcieRpHotPlug[2] = 0;
 370                 break;
 371         case PCH_DEVFN_PCIE2:
 372                 silconfig->PcieRootPortEn[3] = 0;
 373                 silconfig->PcieRpHotPlug[3] = 0;
 374                 break;
 375         case PCH_DEVFN_PCIE3:
 376                 silconfig->PcieRootPortEn[4] = 0;
 377                 silconfig->PcieRpHotPlug[4] = 0;
 378                 break;
 379         case PCH_DEVFN_PCIE4:
 380                 silconfig->PcieRootPortEn[5] = 0;
 381                 silconfig->PcieRpHotPlug[5] = 0;
 382                 break;
 383         case PCH_DEVFN_XHCI:
 384                 silconfig->Usb30Mode = 0;
 385                 break;
 386         case PCH_DEVFN_XDCI:
 387                 silconfig->UsbOtg = 0;
 388                 break;
 389         case PCH_DEVFN_I2C0:
 390                 silconfig->I2c0Enable = 0;
 391                 break;
 392         case PCH_DEVFN_I2C1:
 393                 silconfig->I2c1Enable = 0;
 394                 break;
 395         case PCH_DEVFN_I2C2:
 396                 silconfig->I2c2Enable = 0;
 397                 break;
 398         case PCH_DEVFN_I2C3:
 399                 silconfig->I2c3Enable = 0;
 400                 break;
 401         case PCH_DEVFN_I2C4:
 402                 silconfig->I2c4Enable = 0;
 403                 break;
 404         case PCH_DEVFN_I2C5:
 405                 silconfig->I2c5Enable = 0;
 406                 break;
 407         case PCH_DEVFN_I2C6:
 408                 silconfig->I2c6Enable = 0;
 409                 break;
 410         case PCH_DEVFN_I2C7:
 411                 silconfig->I2c7Enable = 0;
 412                 break;
 413         case PCH_DEVFN_UART0:
 414                 silconfig->Hsuart0Enable = 0;
 415                 break;
 416         case PCH_DEVFN_UART1:
 417                 silconfig->Hsuart1Enable = 0;
 418                 break;
 419         case PCH_DEVFN_UART2:
 420                 silconfig->Hsuart2Enable = 0;
 421                 break;
 422         case PCH_DEVFN_UART3:
 423                 silconfig->Hsuart3Enable = 0;
 424                 break;
 425         case PCH_DEVFN_SPI0:
 426                 silconfig->Spi0Enable = 0;
 427                 break;
 428         case PCH_DEVFN_SPI1:
 429                 silconfig->Spi1Enable = 0;
 430                 break;
 431         case PCH_DEVFN_SPI2:
 432                 silconfig->Spi2Enable = 0;
 433                 break;
 434         case PCH_DEVFN_SDCARD:
 435                 silconfig->SdcardEnabled = 0;
 436                 break;
 437         case PCH_DEVFN_EMMC:
 438                 silconfig->eMMCEnabled = 0;
 439                 break;
 440         case PCH_DEVFN_SDIO:
 441                 silconfig->SdioEnabled = 0;
 442                 break;
 443         case PCH_DEVFN_SMBUS:
 444                 silconfig->SmbusEnable = 0;
 445                 break;
 446 #if !CONFIG(SOC_INTEL_GEMINILAKE)
 447         case SA_DEVFN_IPU:
 448                 silconfig->IpuEn = 0;
 449                 break;
 450 #endif
 451         case PCH_DEVFN_HDA:
 452                 silconfig->HdaEnable = 0;
 453                 break;
 454         default:
 455                 printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n",
 456                         PCI_SLOT(dev->path.pci.devfn),
 457                         PCI_FUNC(dev->path.pci.devfn));
 458                 break;
 459         }
 460 }
 461
 462 static void parse_devicetree(FSP_S_CONFIG *silconfig)
 463 {
 464         struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 465
 466         if (!dev) {
 467                 printk(BIOS_ERR, "Could not find root device\n");
 468                 return;
 469         }
 470         /* Only disable bus 0 devices. */
 471         for (dev = dev->bus->children; dev; dev = dev->sibling) {
 472                 if (!dev->enabled)
 473                         disable_dev(dev, silconfig);
 474         }
 475 }
 476
 477 static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config
 478         *cfg, FSP_S_CONFIG *silconfig)
 479 {
 480 #if !CONFIG(SOC_INTEL_GEMINILAKE) /* GLK FSP does not have these fields in FspsUpd.h yet */
 481         uint8_t port;
 482
 483         for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
 484                 if (cfg->usb_config_override) {
 485                         if (!cfg->usb2_port[port].enable)
 486                                 continue;
 487
 488                         silconfig->PortUsb20Enable[port] = 1;
 489                         silconfig->PortUs20bOverCurrentPin[port] = cfg->usb2_port[port].oc_pin;
 490                 }
 491
 492                 if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0)
 493                         silconfig->PortUsb20PerPortTxPeHalf[port] =
 494                                 cfg->usb2eye[port].Usb20PerPortTxPeHalf;
 495
 496                 if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0)
 497                         silconfig->PortUsb20PerPortPeTxiSet[port] =
 498                                 cfg->usb2eye[port].Usb20PerPortPeTxiSet;
 499
 500                 if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0)
 501                         silconfig->PortUsb20PerPortTxiSet[port] =
 502                                 cfg->usb2eye[port].Usb20PerPortTxiSet;
 503
 504                 if (cfg->usb2eye[port].Usb20HsSkewSel != 0)
 505                         silconfig->PortUsb20HsSkewSel[port] =
 506                                 cfg->usb2eye[port].Usb20HsSkewSel;
 507
 508                 if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0)
 509                         silconfig->PortUsb20IUsbTxEmphasisEn[port] =
 510                                 cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
 511
 512                 if (cfg->usb2eye[port].Usb20PerPortRXISet != 0)
 513                         silconfig->PortUsb20PerPortRXISet[port] =
 514                                 cfg->usb2eye[port].Usb20PerPortRXISet;
 515
 516                 if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0)
 517                         silconfig->PortUsb20HsNpreDrvSel[port] =
 518                                 cfg->usb2eye[port].Usb20HsNpreDrvSel;
 519         }
 520
 521         if (cfg->usb_config_override) {
 522                 for (port = 0; port < APOLLOLAKE_USB3_PORT_MAX; port++) {
 523                         if (!cfg->usb3_port[port].enable)
 524                                 continue;
 525
 526                         silconfig->PortUsb30Enable[port] = 1;
 527                         silconfig->PortUs30bOverCurrentPin[port] = cfg->usb3_port[port].oc_pin;
 528                 }
 529         }
 530 #endif
 531 }
 532
 533 static void glk_fsp_silicon_init_params_cb(
 534         struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
 535 {
 536 #if CONFIG(SOC_INTEL_GEMINILAKE)
 537         uint8_t port;
 538
 539         for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
 540                 if (!cfg->usb2eye[port].Usb20OverrideEn)
 541                         continue;
 542
 543                 silconfig->Usb2AfePehalfbit[port] =
 544                         cfg->usb2eye[port].Usb20PerPortTxPeHalf;
 545                 silconfig->Usb2AfePetxiset[port] =
 546                         cfg->usb2eye[port].Usb20PerPortPeTxiSet;
 547                 silconfig->Usb2AfeTxiset[port] =
 548                         cfg->usb2eye[port].Usb20PerPortTxiSet;
 549                 silconfig->Usb2AfePredeemp[port] =
 550                         cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
 551         }
 552
 553         silconfig->Gmm = is_devfn_enabled(SA_GLK_DEVFN_GMM);
 554
 555         /* On Geminilake, we need to override the default FSP PCIe de-emphasis
 556          * settings using the device tree settings. This is because PCIe
 557          * de-emphasis is enabled by default and Thunderpeak PCIe WiFi detection
 558          * requires de-emphasis disabled. If we make this change common to both
 559          * Apollolake and Geminilake, then we need to add mainboard device tree
 560          * de-emphasis settings of 1 to Apollolake systems.
 561          */
 562         memcpy(silconfig->PcieRpSelectableDeemphasis,
 563                 cfg->pcie_rp_deemphasis_enable,
 564                 sizeof(silconfig->PcieRpSelectableDeemphasis));
 565         /*
 566          * FSP does not know what the clock requirements are for the
 567          * device on SPI bus, hence it should not modify what coreboot
 568          * has set up. Hence skipping in FSP.
 569          */
 570         silconfig->SkipSpiPCP = 1;
 571
 572         /*
 573          * FSP provides UPD interface to execute IPC command. In order to
 574          * improve boot performance, configure PmicPmcIpcCtrl for PMC to program
 575          * PMIC PCH_PWROK delay.
 576          */
 577         silconfig->PmicPmcIpcCtrl = cfg->PmicPmcIpcCtrl;
 578
 579         /*
 580          * Options to disable XHCI Link Compliance Mode.
 581          */
 582         silconfig->DisableComplianceMode = cfg->DisableComplianceMode;
 583
 584         /*
 585          * Options to change USB3 ModPhy setting for Integrated Filter value.
 586          */
 587         silconfig->ModPhyIfValue = cfg->ModPhyIfValue;
 588
 589         /*
 590          * Options to bump USB3 LDO voltage with 40mv.
 591          */
 592         silconfig->ModPhyVoltageBump = cfg->ModPhyVoltageBump;
 593
 594         /*
 595          * Options to adjust PMIC Vdd2 voltage.
 596          */
 597         silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage;
 598 #endif
 599 }
 600
 601 void __weak mainboard_devtree_update(struct device *dev)
 602 {
 603         /* Override dev tree settings per board */
 604 }
 605
 606 void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 607 {
 608         FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
 609         struct soc_intel_apollolake_config *cfg;
 610         struct device *dev;
 611
 612         /* Load VBT before devicetree-specific config. */
 613         silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get();
 614
 615         dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 616         cfg = config_of(dev);
 617
 618         mainboard_devtree_update(dev);
 619
 620         /* Parse device tree and disable unused device*/
 621         parse_devicetree(silconfig);
 622
 623         memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin,
 624                sizeof(silconfig->PcieRpClkReqNumber));
 625
 626         memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable,
 627                sizeof(silconfig->PcieRpHotPlug));
 628
 629         switch (cfg->serirq_mode) {
 630         case SERIRQ_QUIET:
 631                 silconfig->SirqEnable = 1;
 632                 silconfig->SirqMode = 0;
 633                 break;
 634         case SERIRQ_CONTINUOUS:
 635                 silconfig->SirqEnable = 1;
 636                 silconfig->SirqMode = 1;
 637                 break;
 638         case SERIRQ_OFF:
 639         default:
 640                 silconfig->SirqEnable = 0;
 641                 break;
 642         }
 643
 644         if (cfg->emmc_tx_cmd_cntl != 0)
 645                 silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl;
 646         if (cfg->emmc_tx_data_cntl1 != 0)
 647                 silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1;
 648         if (cfg->emmc_tx_data_cntl2 != 0)
 649                 silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2;
 650         if (cfg->emmc_rx_cmd_data_cntl1 != 0)
 651                 silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1;
 652         if (cfg->emmc_rx_strobe_cntl != 0)
 653                 silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl;
 654         if (cfg->emmc_rx_cmd_data_cntl2 != 0)
 655                 silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2;
 656         if (cfg->emmc_host_max_speed != 0)
 657                 silconfig->eMMCHostMaxSpeed = cfg->emmc_host_max_speed;
 658
 659         silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
 660
 661         /* Disable monitor mwait since it is broken due to a hardware bug
 662          * without a fix. Specific to Apollolake.
 663          */
 664         if (!CONFIG(SOC_INTEL_GEMINILAKE))
 665                 silconfig->MonitorMwaitEnable = 0;
 666
 667         silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
 668
 669         /* Disable setting of EISS bit in FSP. */
 670         silconfig->SpiEiss = 0;
 671
 672         /* Disable FSP from locking access to the RTC NVRAM */
 673         silconfig->RtcLock = 0;
 674
 675         /* Enable Audio clk gate and power gate */
 676         silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
 677         silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
 678         /* BIOS config lockdown Audio clk and power gate */
 679         silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
 680         if (CONFIG(SOC_INTEL_GEMINILAKE))
 681                 glk_fsp_silicon_init_params_cb(cfg, silconfig);
 682         else
 683                 apl_fsp_silicon_init_params_cb(cfg, silconfig);
 684
 685         silconfig->UsbOtg = xdci_can_enable(PCH_DEVFN_XDCI);
 686
 687         silconfig->VmxEnable = CONFIG(ENABLE_VMX);
 688
 689         /* Set VTD feature according to devicetree */
 690         silconfig->VtdEnable = cfg->enable_vtd;
 691
 692         silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
 693
 694         silconfig->PavpEnable = CONFIG(PAVP);
 695
 696         mainboard_silicon_init_params(silconfig);
 697 }
 698
 699 struct chip_operations soc_intel_apollolake_ops = {
 700         CHIP_NAME("Intel Apollolake SOC")
 701         .enable_dev = &enable_dev,
 702         .init = &soc_init,
 703         .final = &soc_final
 704 };
 705
 706 static void soc_enable_untrusted_mode(void *unused)
 707 {
 708         /*
 709          * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120
 710          * UCODE_PCR_POWER_MISC MSR to enter IA Untrusted Mode.
 711          */
 712         msr_set(MSR_POWER_MISC, ENABLE_IA_UNTRUSTED);
 713 }
 714
 715 static void drop_privilege_all(void)
 716 {
 717         /* Drop privilege level on all the CPUs */
 718         if (mp_run_on_all_cpus(&soc_enable_untrusted_mode, NULL) != CB_SUCCESS)
 719                 printk(BIOS_ERR, "failed to enable untrusted mode\n");
 720 }
 721
 722 static void configure_xhci_host_mode_port0(void)
 723 {
 724         uint32_t *cfg0;
 725         uint32_t *cfg1;
 726         const struct resource *res;
 727         uint32_t reg;
 728         struct stopwatch sw;
 729         struct device *xhci_dev = PCH_DEV_XHCI;
 730
 731         printk(BIOS_INFO, "Putting xHCI port 0 into host mode.\n");
 732         res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
 733         cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0);
 734         cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1);
 735         reg = read32(cfg0);
 736         if (!(reg & SW_IDPIN_EN_MASK))
 737                 return;
 738
 739         reg &= ~(SW_IDPIN_MASK | SW_VBUS_VALID_MASK);
 740         write32(cfg0, reg);
 741
 742         stopwatch_init_msecs_expire(&sw, 10);
 743         /* Wait for the host mode status bit. */
 744         while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) {
 745                 if (stopwatch_expired(&sw)) {
 746                         printk(BIOS_ERR, "Timed out waiting for host mode.\n");
 747                         return;
 748                 }
 749         }
 750
 751         printk(BIOS_INFO, "xHCI port 0 host switch over took %lu ms\n",
 752                 stopwatch_duration_msecs(&sw));
 753 }
 754
 755 static int check_xdci_enable(void)
 756 {
 757         return is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_XDCI));
 758 }
 759
 760 static void disable_xhci_lfps_pm(void)
 761 {
 762         struct soc_intel_apollolake_config *cfg;
 763
 764         cfg = config_of_soc();
 765
 766         if (cfg->disable_xhci_lfps_pm) {
 767                 void *addr;
 768                 const struct resource *res;
 769                 uint32_t reg;
 770                 struct device *xhci_dev = PCH_DEV_XHCI;
 771
 772                 res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
 773                 addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL);
 774                 reg = read32(addr);
 775                 printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg);
 776                 if (reg) {
 777                         reg &= LFPS_PM_DISABLE_MASK;
 778                         write32(addr, reg);
 779                         printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n");
 780                 }
 781         }
 782 }
 783
 784 void platform_fsp_notify_status(enum fsp_notify_phase phase)
 785 {
 786         if (phase == END_OF_FIRMWARE) {
 787
 788                 /*
 789                  * Before hiding P2SB device and dropping privilege level,
 790                  * dump CSE status and disable HECI1 interface.
 791                  */
 792                 heci_cse_lockdown();
 793
 794                 /* Hide the P2SB device to align with previous behavior. */
 795                 p2sb_hide();
 796
 797                 /*
 798                  * As per guidelines BIOS is recommended to drop CPU privilege
 799                  * level to IA_UNTRUSTED. After that certain device registers
 800                  * and MSRs become inaccessible supposedly increasing system
 801                  * security.
 802                  */
 803                 drop_privilege_all();
 804
 805                 /*
 806                  * When USB OTG is set, GLK FSP enables xHCI SW ID pin and
 807                  * configures USB-C as device mode. Force USB-C into host mode.
 808                  */
 809                 if (check_xdci_enable())
 810                         configure_xhci_host_mode_port0();
 811
 812                 /*
 813                  * Override GLK xhci clock gating register(XHCLKGTEN) to
 814                  * mitigate USB device suspend and resume failure.
 815                  */
 816                 if (CONFIG(SOC_INTEL_GEMINILAKE)) {
 817                         uint32_t *cfg;
 818                         const struct resource *res;
 819                         uint32_t reg;
 820                         struct device *xhci_dev = PCH_DEV_XHCI;
 821
 822                         res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0);
 823                         cfg = (void *)(uintptr_t)(res->base + CFG_XHCLKGTEN);
 824                         reg = SRAMPGTEN | SSLSE | USB2PLLSE | IOSFSTCGE |
 825                                 HSTCGE | HSUXDMIPLLSE | SSTCGE | XHCFTCLKSE |
 826                                 XHCBBTCGIPISO | XHCUSB2PLLSDLE | SSPLLSUE |
 827                                 XHCBLCGE | HSLTCGE | SSLTCGE | IOSFBTCGE |
 828                                 IOSFGBLCGE;
 829                         write32(cfg, reg);
 830                 }
 831
 832                 /* Disable XHCI LFPS power management if the option in dev tree is set. */
 833                 disable_xhci_lfps_pm();
 834         }
 835 }
 836
 837 /*
 838  * spi_flash init() needs to run unconditionally on every boot (including
 839  * resume) to allow write protect to be disabled for eventlog and nvram
 840  * updates. This needs to be done as early as possible in ramstage. Thus, add a
 841  * callback for entry into BS_PRE_DEVICE.
 842  */
 843 static void spi_flash_init_cb(void *unused)
 844 {
 845         fast_spi_init();
 846 }
 847
 848 __weak
 849 void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig)
 850 {
 851         printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 852 }
 853
 854 /* Handle FSP logo params */
 855 void soc_load_logo(FSPS_UPD *supd)
 856 {
 857         bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize);
 858 }
 859
 860 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL);