src/mainboard/intel/d945gclf/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  17
  18 #include <stdint.h>
  19 #include <string.h>
  20 #include <arch/io.h>
  21 #include <device/pci_def.h>
  22 #include <device/pnp_def.h>
  23 #include <cpu/x86/lapic.h>
  24 #include <lib.h>
  25 #include <arch/acpi.h>
  26 #include <cbmem.h>
  27 #include <superio/smsc/lpc47m15x/lpc47m15x.h>
  28 #include <pc80/mc146818rtc.h>
  29 #include <console/console.h>
  30 #include <cpu/x86/bist.h>
  31 #include <northbridge/intel/i945/i945.h>
  32 #include <northbridge/intel/i945/raminit.h>
  33 #include <southbridge/intel/i82801gx/i82801gx.h>
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
  36 #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
  37
  38 void setup_ich7_gpios(void)
  39 {
  40         /* TODO: This is highly board specific and should be moved */
  41         printk(BIOS_DEBUG, " GPIOS...");
  42         /* General Registers */
  43         outl(0x3f3df7c1, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
  44         outl(0xc6fcbfc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
  45         outl(0xecfefdff, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
  46         /* Output Control Registers */
  47         outl(0x00040000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
  48         /* Input Control Registers */
  49         outl(0x0000a000, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
  50         outl(0x000000ff, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
  51         outl(0x000000bf, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
  52         outl(0x000300fd, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
  53 }
  54
  55 static void ich7_enable_lpc(void)
  56 {
  57         // Enable Serial IRQ
  58         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
  59         // Set COM1/COM2 decode range
  60         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
  61         // Enable COM1
  62         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x140d);
  63         // Enable SuperIO Power Management Events
  64         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
  65 }
  66
  67 static void rcba_config(void)
  68 {
  69         /* Set up virtual channel 0 */
  70         //RCBA32(0x0014) = 0x80000001;
  71         //RCBA32(0x001c) = 0x03128010;
  72
  73         /* Device 1f interrupt pin register */
  74         RCBA32(0x3100) = 0x00042210;
  75         /* Device 1d interrupt pin register */
  76         RCBA32(0x310c) = 0x00214321;
  77
  78         /* dev irq route register */
  79         RCBA16(0x3140) = 0x0132;
  80         RCBA16(0x3142) = 0x0146;
  81         RCBA16(0x3144) = 0x0237;
  82         RCBA16(0x3146) = 0x3201;
  83         RCBA16(0x3148) = 0x0146;
  84
  85         /* Enable IOAPIC */
  86         RCBA8(0x31ff) = 0x03;
  87
  88         /* Disable unused devices */
  89         //RCBA32(0x3418) = FD_PCIE6|FD_PCIE5|FD_PCIE4|FD_ACMOD|FD_ACAUD|FD_PATA;
  90         // RCBA32(0x3418) |= (1 << 0); // Required.
  91         // FIXME look me up!
  92         RCBA32(0x3418) = 0x003204e1;
  93
  94         /* Enable PCIe Root Port Clock Gate */
  95         // RCBA32(0x341c) = 0x00000001;
  96 }
  97
  98 static void early_ich7_init(void)
  99 {
 100         uint8_t reg8;
 101         uint32_t reg32;
 102
 103         // program secondary mlt XXX byte?
 104         pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 105
 106         // reset rtc power status
 107         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 108         reg8 &= ~(1 << 2);
 109         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 110
 111         // usb transient disconnect
 112         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 113         reg8 |= (3 << 0);
 114         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
 115
 116         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
 117         reg32 |= (1 << 29) | (1 << 17);
 118         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
 119
 120         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
 121         reg32 |= (1 << 31) | (1 << 27);
 122         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 123
 124         RCBA32(0x0088) = 0x0011d000;
 125         RCBA16(0x01fc) = 0x060f;
 126         RCBA32(0x01f4) = 0x86000040;
 127         RCBA32(0x0214) = 0x10030549;
 128         RCBA32(0x0218) = 0x00020504;
 129         RCBA8(0x0220) = 0xc5;
 130         reg32 = RCBA32(0x3410);
 131         reg32 |= (1 << 6);
 132         RCBA32(0x3410) = reg32;
 133         reg32 = RCBA32(0x3430);
 134         reg32 &= ~(3 << 0);
 135         reg32 |= (1 << 0);
 136         RCBA32(0x3430) = reg32;
 137         RCBA32(0x3418) |= (1 << 0);
 138         RCBA16(0x0200) = 0x2008;
 139         RCBA8(0x2027) = 0x0d;
 140         RCBA16(0x3e08) |= (1 << 7);
 141         RCBA16(0x3e48) |= (1 << 7);
 142         RCBA32(0x3e0e) |= (1 << 7);
 143         RCBA32(0x3e4e) |= (1 << 7);
 144
 145         // next step only on ich7m b0 and later:
 146         reg32 = RCBA32(0x2034);
 147         reg32 &= ~(0x0f << 16);
 148         reg32 |= (5 << 16);
 149         RCBA32(0x2034) = reg32;
 150 }
 151
 152 #include <cpu/intel/romstage.h>
 153 void main(unsigned long bist)
 154 {
 155         int s3resume = 0, boot_mode = 0;
 156
 157         if (bist == 0)
 158                 enable_lapic();
 159
 160         ich7_enable_lpc();
 161         /* Enable SuperIO PM */
 162         lpc47m15x_enable_serial(PME_DEV, 0x680);
 163         lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
 164
 165         /* Set up the console */
 166         console_init();
 167
 168         /* Halt if there was a built in self test failure */
 169         report_bist_failure(bist);
 170
 171         if (MCHBAR16(SSKPD) == 0xCAFE) {
 172                 printk(BIOS_DEBUG, "soft reset detected.\n");
 173                 boot_mode = 1;
 174         }
 175
 176         /* Perform some early chipset initialization required
 177          * before RAM initialization can work
 178          */
 179         i945_early_initialization();
 180
 181         s3resume = southbridge_detect_s3_resume();
 182
 183         /* Enable SPD ROMs and DDR-II DRAM */
 184         enable_smbus();
 185
 186 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 187         dump_spd_registers();
 188 #endif
 189
 190         sdram_initialize(s3resume ? 2 : boot_mode, NULL);
 191
 192         /* Perform some initialization that must run before stage2 */
 193         early_ich7_init();
 194
 195         /* This should probably go away. Until now it is required
 196          * and mainboard specific
 197          */
 198         rcba_config();
 199
 200         /* Chipset Errata! */
 201         fixup_i945_errata();
 202
 203         /* Initialize the internal PCIe links before we go into stage2 */
 204         i945_late_initialization(s3resume);
 205 }