src/mainboard/amd/dinar/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <string.h>
  18 #include <device/pci_def.h>
  19 #include <device/pci_ids.h>
  20 #include <arch/io.h>
  21 #include <arch/cpu.h>
  22 #include <arch/stages.h>
  23 #include <device/pnp_def.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <console/console.h>
  26 #include <commonlib/loglevel.h>
  27 #include <cpu/amd/car.h>
  28 #include <northbridge/amd/agesa/agesawrapper.h>
  29 #include <cpu/x86/bist.h>
  30 #include <superio/smsc/sch4037/sch4037.h>
  31 #include <superio/smsc/sio1036/sio1036.h>
  32 #include <cpu/x86/lapic.h>
  33 #include "nb_cimx.h"
  34 #include <sb_cimx.h>
  35
  36 #define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1)
  37
  38 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  39 {
  40         u32 val;
  41
  42         amd_initmmio();
  43
  44         if (!cpu_init_detectedx && boot_cpu()) {
  45
  46                 post_code(0x30);
  47
  48                 sch4037_early_init(0x2e);
  49
  50                 sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  51
  52                 post_code(0x31);
  53                 console_init();
  54
  55                 /*
  56                  * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
  57                  * Disable all Pcie Bridges to work around It.
  58                  */
  59                 sr56x0_rd890_disable_pcie_bridge();
  60
  61         }
  62
  63         /* Halt if there was a built in self test failure */
  64         post_code(0x33);
  65         report_bist_failure(bist);
  66
  67         // Load MPB
  68         val = cpuid_eax(1);
  69         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
  70         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
  71
  72         if(boot_cpu()) {
  73                 post_code(0x34);
  74                 sb_Poweron_Init();
  75         }
  76
  77         post_code(0x35);
  78         agesawrapper_amdinitreset();
  79
  80         post_code(0x36);
  81         agesawrapper_amdinitearly();
  82
  83         post_code(0x37);
  84         nb_Poweron_Init();
  85         post_code(0x38);
  86         nb_Ht_Init();
  87
  88
  89         post_code(0x39);
  90         agesawrapper_amdinitpost();
  91
  92         post_code(0x40);
  93         agesawrapper_amdinitenv();
  94
  95
  96         post_code(0x43);
  97         printk(BIOS_DEBUG, "Disabling cache as ram ");
  98         disable_cache_as_ram();
  99         printk(BIOS_DEBUG, "done\n");
 100
 101         post_code(0x44);
 102         copy_and_run();
 103
 104         post_code(0x45);  // Should never see this post code.
 105 }