src/mainboard/amd/dinar/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "Filecode.h"
  17 #include "Hudson-2.h"
  18 #include "AmdSbLib.h"
  19 #include "gpio.h"
  20
  21 #define FILECODE UNASSIGNED_FILE_FILECODE
  22
  23 #ifndef SB_GPIO_REG01
  24 #define SB_GPIO_REG01   1
  25 #endif
  26
  27 #ifndef SB_GPIO_REG07
  28 #define SB_GPIO_REG07   7
  29 #endif
  30
  31 #ifndef SB_GPIO_REG25
  32 #define SB_GPIO_REG25   25
  33 #endif
  34
  35 #ifndef SB_GPIO_REG26
  36 #define SB_GPIO_REG26   26
  37 #endif
  38
  39 #ifndef SB_GPIO_REG27
  40 #define SB_GPIO_REG27   27
  41 #endif
  42
  43 void gpioEarlyInit (void);
  44
  45 void
  46 gpioEarlyInit(
  47                 void
  48              )
  49 {
  50         u8  Flags;
  51         u8      Data8 = 0;
  52         u8      StripInfo = 0;
  53         u8      BoardType = 1;
  54         u8      RegIndex8 = 0;
  55         u8      boardRevC = 0x2;
  56         u16     Data16 = 0;
  57         u32     Index = 0;
  58         u32     AcpiMmioAddr = 0;
  59         u32     GpioMmioAddr = 0;
  60         u32     IoMuxMmioAddr = 0;
  61         u32     MiscMmioAddr = 0;
  62         u32     SmiMmioAddr = 0;
  63         u32     andMask32 = 0;
  64
  65         // Enable HUDSON MMIO Base (AcpiMmioAddr)
  66         ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
  67         Data8 |= BIT0;
  68         WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
  69         // Get HUDSON MMIO Base (AcpiMmioAddr)
  70         ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
  71         Data16 = Data8 << 8;
  72         ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
  73         Data16 |= Data8;
  74         AcpiMmioAddr = (u32)Data16 << 16;
  75         GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
  76         IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
  77         MiscMmioAddr =  AcpiMmioAddr + MISC_BASE;
  78         Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
  79         if ((Data8 & BIT4) == 0) {
  80                 BoardType = 0; // external clock board
  81         }
  82         Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
  83         StripInfo = (Data8 & BIT7) >> 7;
  84         Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
  85         StripInfo |= (Data8 & BIT7) >> 6;
  86         if (StripInfo < boardRevC) {            // for old board. Rev B
  87                 Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);                // function 3
  88                 Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);                // function 0
  89         }
  90         for (Index = 0; Index < MAX_GPIO_NO; Index++) {
  91                 if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
  92                         if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
  93                                 // Configure multi-function
  94                                 Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
  95                         }
  96                         // Configure GPIO
  97                         if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
  98                                 Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
  99                                 Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
 100                         }
 101                         if (Index == GPIO_65) {
 102                                 if ( BoardType == 0 ) {
 103                                         Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3);         // function 3
 104                                 }
 105                         }
 106                 }
 107                 // Configure GEVENT
 108                 if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
 109                         SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
 110
 111                         andMask32 = ~(1 << (Index - GEVENT_00));
 112
 113                         //EventEnable: 0-Disable, 1-Enable
 114                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
 115
 116                         //SciTrig: 0-Falling Edge, 1-Rising Edge
 117                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
 118
 119                         //SciLevl: 0-Edge trigger, 1-Level Trigger
 120                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
 121
 122                         //SmiSciEn: 0-Not send SMI, 1-Send SMI
 123                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
 124
 125                         //SciS0En: 0-Disable, 1-Enable
 126                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
 127
 128                         //SciMap: 00000b ~ 11111b
 129                         RegIndex8=(u8)((Index - GEVENT_00) >> 2);
 130                         Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
 131                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
 132
 133                         //SmiTrig: 0-Active Low, 1-Active High
 134                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
 135
 136                         //SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
 137                         RegIndex8=(u8)((Index - GEVENT_00) >> 4);
 138                         Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
 139                         Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
 140                 }
 141         }
 142
 143         //
 144         // config MXM
 145         //      GPIO9: Input for MXM_PRESENT2#
 146         //      GPIO10: Input for MXM_PRESENT1#
 147         //      GPIO28: Input for MXM_PWRGD
 148         //      GPIO35: Output for MXM Reset
 149         //      GPIO45: Output for MXM Power Enable, active HIGH
 150         //      GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
 151         //      GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
 152         //
 153         // set INTE#/GPIO32 as GPO for PCIE_SW
 154         RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1);      // GPIO
 155         RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0);       // GPO
 156         RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
 157
 158         // set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
 159         RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2);      // GPIO
 160         RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0);       // GPO
 161
 162         // set AD9/GPIO9 as GPI for MXM_PRESENT2#
 163         RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1);      // GPIO
 164         RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5);    // GPI
 165
 166         // set AD10/GPIO10 as GPI for MXM_PRESENT1#
 167         RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1);      // GPIO
 168         RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5);    // GPI
 169
 170         // set GNT1#/GPIO44 as GPO for MXM Reset
 171         RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1);      // GPIO
 172         RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0);       // GPO
 173
 174         // set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
 175         RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2);      // GPIO
 176         RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0);       // GPO
 177
 178         // set AD28/GPIO28 as GPI for MXM_PWRGD
 179         RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1);      // GPIO
 180         RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5);    // GPI
 181
 182         // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
 183         RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
 184         RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
 185         RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
 186         RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
 187         RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
 188         RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
 189
 190         //
 191         // [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
 192         //
 193         //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
 194         //Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
 195
 196         // check if there any GFX card
 197         Flags = 0;
 198         // Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
 199         // Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
 200         ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
 201         if (!(Data8 & BIT7))
 202         {
 203                 //Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
 204                 ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
 205                 if (!(Data8 & BIT7))
 206                 {
 207                         Flags = 1;
 208                 }
 209         }
 210         if (  Flags )
 211         {
 212                 // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
 213                 RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
 214
 215                 // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
 216                 RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
 217
 218                 //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
 219                 SbStall (10000);
 220
 221                 // Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
 222                 RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
 223
 224                 //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
 225                 // WAIT POWER READY: GPIO28 (MXM_PWRGD)
 226                 //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
 227                 ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
 228                 while (!(Data8 & BIT7))
 229                 {
 230                         ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
 231                 }
 232                 // [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
 233                 //      RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
 234         }
 235         else
 236         {
 237                 // Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
 238                 RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
 239
 240                 //PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
 241                 SbStall (10000);
 242
 243                 // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
 244                 RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
 245         }
 246
 247         //
 248         // APU GPP0: On board LAN
 249         //      GPIO25: PCIE_RST#_LAN, LOW active
 250         //      GPIO63: LAN_CLKREQ#
 251         //      GPIO197: LOM_POWER, HIGH Active
 252         //      Clock: GPP_CLK3
 253         //
 254         // Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
 255         RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2);         // GPIO
 256         //              RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0);          // GPO
 257         RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6);       // output HIGH
 258         RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
 259
 260         // Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
 261         RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1);          // GPIO
 262         //              RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0);           // GPO
 263         RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6);        // output HIGH
 264         RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3);        // pullup DISABLE
 265
 266
 267         // set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
 268         RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0);          // CLK_REQ3#
 269         RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0);       // Enable GPP_CLK3
 270
 271         //
 272         // APU GPP1: WUSB
 273         //      GPIO1: MPCIE_RST2#, LOW active
 274         //      GPIO13: WU_DISABLE#, LOW active
 275         //      GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
 276         //
 277         // Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
 278         RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2);     // GPIO
 279         //              RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // GPO
 280         RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // output LOW
 281         RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
 282
 283         // Setup AD01/GPIO01 as GPO for MPCIE_RST2#
 284         RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1);      // GPIO
 285         //              RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0);       // GPO
 286         RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6);    // output LOW
 287         RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
 288
 289         // Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
 290         //              RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1);      // GPIO
 291         //              RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0);       // GPO
 292         //              RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6);    // output HIGH
 293         //              RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
 294
 295         //
 296         // APU GPP2: WWAN
 297         //      GPIO0: MPCIE_RST1#, LOW active
 298         //      GPIO14: WP_DISABLE#, LOW active
 299         //      GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
 300         //
 301         // Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
 302         RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1);     // GPIO
 303         //              RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // GPO
 304         RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // output LOW
 305         RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
 306
 307         // Set AD00/GPIO00 as GPO for MPCIE_RST1#
 308         RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1);      // GPIO
 309         //              RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0);       // GPO
 310         //              RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6);    // output LOW
 311         RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
 312
 313         // Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
 314         //              RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1);      // GPIO
 315         //              RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0);       // GPO
 316         //              RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
 317         //              RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
 318
 319         //
 320         // APU GPP3: 1394
 321         //      GPIO59: Power control, HIGH active
 322         //      GPIO27: PCIE_RST#_1394, LOW active
 323         //      GPIO41: CLKREQ#
 324         //      Clock: GPP_CLK8
 325         //
 326         // Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
 327         RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2);         // GPIO
 328         //              RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0);          // GPO
 329         RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);       // output HIGH
 330         RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
 331
 332         // Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
 333         RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1);         // GPIO
 334         //              RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0);          // GPO
 335         RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);       // output HIGH
 336         RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
 337
 338         // set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
 339         RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1);         // CLK_REQ2#
 340
 341         // set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
 342         RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1);        // GPIO
 343         RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0);         // GPO
 344         RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6);       // output HIGH
 345         RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
 346         //  To fix glitch issue
 347         RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
 348         //
 349         // Enable/Disable OnBoard LAN
 350         //
 351         if (!CONFIG_ONBOARD_LAN)
 352         { // 1 - DISABLED
 353                 RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0);      // LOM_POWER off
 354                 RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
 355                 RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED
 356                 RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0);     // Disable GPP_CLK3
 357         }
 358         //              else
 359         //              { // 0 - AUTO
 360         //                      // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
 361         //                      RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
 362         //                      RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
 363         //              }
 364
 365
 366         //
 367         // Enable/Disable 1394
 368         //
 369         if (!CONFIG_ONBOARD_1394)
 370         { // 1 - DISABLED
 371                 //                      RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
 372                 RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0);       // 1394 power off
 373                 RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
 374                 RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3);    // pullup DISABLE
 375                 RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0);       // DISABLE GPP_CLK8
 376                 //                      RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6);   // set GPIO_GATE_C to HIGH
 377         }
 378         //              else
 379         //              { // 0 - AUTO
 380         //                      // set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
 381         //                      RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
 382         //                      RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
 383         //
 384         //                      RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
 385         //                      RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
 386         //              }
 387
 388         //
 389         // external USB 3.0 control:
 390         //    amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
 391         //                      GPIO26: PCIE_RST#_USB3.0
 392         //                      GPIO46: PCIE_USB30_CLKREQ#
 393         //                     GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
 394         //                       Clock: GPP_CLK7
 395         //                     GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
 396         //      if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
 397         // disable Onboard NEC USB3.0 controller
 398         if (!CONFIG_ONBOARD_USB30) {
 399                 RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
 400                 RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
 401                 RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3);   // PULL_UP DISABLE
 402                 RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7
 403                 RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0);  // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
 404         }
 405         //      }
 406
 407         //
 408         // BlueTooth control: BT_ON
 409         //    amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
 410         //          GPIO07: BT_ON, 0 - OFF, 1 - ON
 411         //
 412         if (!CONFIG_ONBOARD_BLUETOOTH) {
 413                 //-     if (SystemConfiguration.amdBlueTooth == 1) {
 414                 RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
 415                 //-     }
 416         }
 417
 418         //
 419         // WebCam control:
 420         //    amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
 421         //       GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
 422         //
 423         if (!CONFIG_ONBOARD_WEBCAM) {
 424                 //-     if (SystemConfiguration.amdWebCam == 1) {
 425                 RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
 426                 //-     }
 427         }
 428
 429         //
 430         // Travis enable:
 431         //    amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
 432         //           GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
 433         //
 434         if (!CONFIG_ONBOARD_TRAVIS) {
 435                 //-     if (SystemConfiguration.amdTravisCtrl == 0) {
 436                 RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
 437                 //-     }
 438         }
 439
 440         //
 441         // Disable Light Sensor if needed
 442         //
 443         if (CONFIG_ONBOARD_LIGHTSENSOR) {
 444                 //-    if (SystemConfiguration.amdLightSensor == 1) {
 445                 RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
 446                 //-    }
 447         }
 448
 449 }