1 ## SPDX-License-Identifier: GPL-2.0-only
3 mainmenu "coreboot configuration"
12 string "Local version string"
14 Append an extra string to the end of the coreboot version.
16 This can be useful if, for instance, you want to append the
17 respective board's hostname or some other identifying string to
18 the coreboot version number, so that you can easily distinguish
19 boot logs of different boards from each other.
21 config CONFIGURABLE_CBFS_PREFIX
24 Select this to prompt to use to configure the prefix for cbfs files.
27 prompt "CBFS prefix to use"
28 depends on CONFIGURABLE_CBFS_PREFIX
29 default CBFS_PREFIX_FALLBACK
31 config CBFS_PREFIX_FALLBACK
34 config CBFS_PREFIX_NORMAL
37 config CBFS_PREFIX_DIY
38 bool "Define your own cbfs prefix"
43 string "CBFS prefix to use" if CBFS_PREFIX_DIY
44 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
45 default "normal" if CBFS_PREFIX_NORMAL
47 Select the prefix to all files put into the image. It's "fallback"
48 by default, "normal" is a common alternative.
51 prompt "Compiler to use"
54 This option allows you to select the compiler used for building
56 You must build the coreboot crosscompiler for the board that you
59 To build all the GCC crosscompilers (takes a LONG time), run:
62 For help on individual architectures, run the command:
68 Use the GNU Compiler Collection (GCC) to build coreboot.
70 For details see http://gcc.gnu.org.
72 config COMPILER_LLVM_CLANG
73 bool "LLVM/clang (TESTING ONLY - Not currently working)"
75 Use LLVM/clang to build coreboot. To use this, you must build the
76 coreboot version of the clang compiler. Run the command
78 Note that this option is not currently working correctly and should
79 really only be selected if you're trying to work on getting clang
82 For details see http://clang.llvm.org.
87 bool "Allow building with any toolchain"
90 Many toolchains break when building coreboot since it uses quite
91 unusual linker features. Unless developers explicitely request it,
92 we'll have to assume that they use their distro compiler by mistake.
93 Make sure that using patched compilers is a conscious decision.
96 bool "Use ccache to speed up (re)compilation"
99 Enables the use of ccache for faster builds.
101 Requires the ccache utility in your system $PATH.
103 For details see https://ccache.samba.org.
106 bool "Generate flashmap descriptor parser using flex and bison"
109 Enable this option if you are working on the flashmap descriptor
110 parser and made changes to fmd_scanner.l or fmd_parser.y.
112 Otherwise, say N to use the provided pregenerated scanner/parser.
114 config UTIL_GENPARSER
115 bool "Generate SCONFIG & BINCFG parser using flex and bison"
118 Enable this option if you are working on the sconfig device tree
119 parser or bincfg and made changes to the .l or .y files.
121 Otherwise, say N to use the provided pregenerated scanner/parser.
123 config USE_OPTION_TABLE
124 bool "Use CMOS for configuration values"
125 depends on HAVE_OPTION_TABLE
127 Enable this option if coreboot shall read options from the "CMOS"
128 NVRAM instead of using hard-coded values.
130 config STATIC_OPTION_TABLE
131 bool "Load default configuration values into CMOS on each boot"
132 depends on USE_OPTION_TABLE
134 Enable this option to reset "CMOS" NVRAM values to default on
135 every boot. Use this if you want the NVRAM configuration to
136 never be modified from its default values.
138 config COMPRESS_RAMSTAGE
139 bool "Compress ramstage with LZMA"
140 depends on HAVE_RAMSTAGE
141 # Default value set at the end of the file
143 Compress ramstage to save memory in the flash image.
145 config COMPRESS_PRERAM_STAGES
146 bool "Compress romstage and verstage with LZ4"
147 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
148 # Default value set at the end of the file
150 Compress romstage and (if it exists) verstage with LZ4 to save flash
151 space and speed up boot, since the time for reading the image from SPI
152 (and in the vboot case verifying it) is usually much greater than the
153 time spent decompressing. Doesn't work for XIP stages (assume all
154 ARCH_X86 for now) for obvious reasons.
156 config COMPRESS_BOOTBLOCK
158 depends on HAVE_BOOTBLOCK
160 This option can be used to compress the bootblock with LZ4 and attach
161 a small self-decompression stub to its front. This can drastically
162 reduce boot time on platforms where the bootblock is loaded over a
163 very slow connection and bootblock size trumps all other factors for
164 speed. Since using this option usually requires changes to the
165 SoC memlayout and possibly extra support code, it should not be
166 user-selectable. (There's no real point in offering this to the user
167 anyway... if it works and saves boot time, you would always want it.)
169 config INCLUDE_CONFIG_FILE
170 bool "Include the coreboot .config file into the ROM image"
171 # Default value set at the end of the file
173 Include the .config file that was used to compile coreboot
174 in the (CBFS) ROM image. This is useful if you want to know which
175 options were used to build a specific coreboot.rom image.
177 Saying Y here will increase the image size by 2-3KB.
179 You can use the following command to easily list the options:
181 grep -a CONFIG_ coreboot.rom
183 Alternatively, you can also use cbfstool to print the image
184 contents (including the raw 'config' item we're looking for).
188 $ cbfstool coreboot.rom print
189 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
193 Name Offset Type Size
194 cmos_layout.bin 0x0 CMOS layout 1159
195 fallback/romstage 0x4c0 stage 339756
196 fallback/ramstage 0x53440 stage 186664
197 fallback/payload 0x80dc0 payload 51526
198 config 0x8d740 raw 3324
199 (empty) 0x8e480 null 3610440
201 config COLLECT_TIMESTAMPS
202 bool "Create a table of timestamps collected during boot"
203 default y if ARCH_X86
205 Make coreboot create a table of timer-ID/timer-value pairs to
206 allow measuring time spent at different phases of the boot process.
208 config TIMESTAMPS_ON_CONSOLE
209 bool "Print the timestamp values on the console"
211 depends on COLLECT_TIMESTAMPS
213 Print the timestamps to the debug console if enabled at level info.
216 bool "Allow use of binary-only repository"
219 This draws in the blobs repository, which contains binary files that
220 might be required for some chipsets or boards.
221 This flag ensures that a "Free" option remains available for users.
224 bool "Allow AMD blobs repository (with license agreement)"
227 This draws in the amd_blobs repository, which contains binary files
228 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
229 etc. Selecting this item to download or clone the repo implies your
230 agreement to the AMD license agreement. A copy of the license text
231 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
232 and your copy of the license is present in the repo once downloaded.
234 Note that for some products, omitting PSP, SMU images, or other items
235 may result in a nonbooting coreboot.rom.
238 bool "Code coverage support"
239 depends on COMPILER_GCC
241 Add code coverage support for coreboot. This will store code
242 coverage information in CBMEM for extraction from user space.
246 bool "Undefined behavior sanitizer support"
249 Instrument the code with checks for undefined behavior. If unsure,
250 say N because it adds a small performance penalty and may abort
251 on code that happens to work in spite of the UB.
253 config RELOCATABLE_RAMSTAGE
255 default y if ARCH_X86
256 select RELOCATABLE_MODULES
258 The reloctable ramstage support allows for the ramstage to be built
259 as a relocatable module. The stage loader can identify a place
260 out of the OS way so that copying memory is unnecessary during an S3
261 wake. When selecting this option the romstage is responsible for
262 determing a stack location to use for loading the ramstage.
265 prompt "Stage Cache for ACPI S3 resume"
266 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
267 default TSEG_STAGE_CACHE if SMM_TSEG
269 config NO_STAGE_CACHE
272 Do not save any component in stage cache for resume path. On resume,
273 all components would be read back from CBFS again.
275 config TSEG_STAGE_CACHE
279 The option enables stage cache support for platform. Platform
280 can stash copies of postcar, ramstage and raw runtime data
281 inside SMM TSEG, to be restored on S3 resume path.
283 config CBMEM_STAGE_CACHE
287 The option enables stage cache support for platform. Platform
288 can stash copies of postcar, ramstage and raw runtime data
291 While the approach is faster than reloading stages from boot media
292 it is also a possible attack scenario via which OS can possibly
293 circumvent SMM locks and SPI write protections.
295 If unsure, select 'N'
300 bool "Update existing coreboot.rom image"
302 If this option is enabled, no new coreboot.rom file
303 is created. Instead it is expected that there already
304 is a suitable file for further processing.
305 The bootblock will not be modified.
307 If unsure, select 'N'
309 config BOOTSPLASH_IMAGE
310 bool "Add a bootsplash image"
312 Select this option if you have a bootsplash image that you would
313 like to add to your ROM.
315 This will only add the image to the ROM. To actually run it check
316 options under 'Display' section.
318 config BOOTSPLASH_FILE
319 string "Bootsplash path and filename"
320 depends on BOOTSPLASH_IMAGE
321 # Default value set at the end of the file
323 The path and filename of the file to use as graphical bootsplash
324 screen. The file format has to be jpg.
326 config HAVE_RAMPAYLOAD
330 bool "Enable coreboot flow without executing ramstage"
331 default y if ARCH_X86
332 depends on HAVE_RAMPAYLOAD
334 If this option is enabled, coreboot flow will skip ramstage
335 loading and execution of ramstage to load payload.
337 Instead it is expected to load payload from postcar stage itself.
339 In this flow coreboot will perform basic x86 initialization
340 (DRAM resource allocation), MTRR programming,
341 Skip PCI enumeration logic and only allocate BAR for fixed devices
342 (bootable devices, TPM over GSPI).
344 config HAVE_CONFIGURABLE_RAMSTAGE
347 config CONFIGURABLE_RAMSTAGE
348 bool "Enable a configurable ramstage."
349 default y if ARCH_X86
350 depends on HAVE_CONFIGURABLE_RAMSTAGE
352 A configurable ramstage allows you to select which parts of the ramstage
353 to run. Currently, we can only select a minimal PCI scanning step.
354 The minimal PCI scanning will only check those parts that are enabled
355 in the devicetree.cb. By convention none of those devices should be bridges.
357 config MINIMAL_PCI_SCANNING
358 bool "Enable minimal PCI scanning"
359 depends on CONFIGURABLE_RAMSTAGE && PCI
361 If this option is enabled, coreboot will scan only PCI devices
362 marked as mandatory in devicetree.cb
367 source "src/mainboard/Kconfig"
371 default "devicetree.cb"
373 This symbol allows mainboards to select a different file under their
374 mainboard directory for the devicetree.cb file. This allows the board
375 variants that need different devicetrees to be in the same directory.
377 Examples: "devicetree.variant.cb"
378 "variant/devicetree.cb"
380 config OVERRIDE_DEVICETREE
384 This symbol allows variants to provide an override devicetree file to
385 override the registers and/or add new devices on top of the ones
386 provided by baseboard devicetree using CONFIG_DEVICETREE.
388 Examples: "devicetree.variant-override.cb"
389 "variant/devicetree-override.cb"
392 string "fmap description file in fmd format"
393 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
396 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
397 but in some cases more complex setups are required.
398 When an fmd is specified, it overrides the default format.
401 hex "Size of CBFS filesystem in ROM"
402 depends on FMDFILE = ""
403 # Default value set at the end of the file
405 This is the part of the ROM actually managed by CBFS, located at the
406 end of the ROM (passed through cbfstool -o) on x86 and at at the start
407 of the ROM (passed through cbfstool -s) everywhere else. It defaults
408 to span the whole ROM on all but Intel systems that use an Intel Firmware
409 Descriptor. It can be overridden to make coreboot live alongside other
410 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
411 binaries. This symbol should only be used to generate a default FMAP and
412 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
416 # load site-local kconfig to allow user specific defaults and overrides
417 source "site-local/Kconfig"
419 config SYSTEM_TYPE_LAPTOP
423 config SYSTEM_TYPE_TABLET
427 config SYSTEM_TYPE_DETACHABLE
431 config SYSTEM_TYPE_CONVERTIBLE
435 config CBFS_AUTOGEN_ATTRIBUTES
439 If this option is selected, every file in cbfs which has a constraint
440 regarding position or alignment will get an additional file attribute
441 which describes this constraint.
446 source "src/soc/*/Kconfig"
448 source "src/cpu/Kconfig"
449 comment "Northbridge"
450 source "src/northbridge/*/*/Kconfig"
451 comment "Southbridge"
452 source "src/southbridge/*/*/Kconfig"
454 source "src/superio/*/*/Kconfig"
455 comment "Embedded Controllers"
456 source "src/ec/acpi/Kconfig"
457 source "src/ec/*/*/Kconfig"
459 source "src/southbridge/intel/common/firmware/Kconfig"
460 source "src/vendorcode/*/Kconfig"
462 source "src/arch/*/Kconfig"
466 source "src/device/Kconfig"
468 menu "Generic Drivers"
469 source "src/drivers/*/Kconfig"
470 source "src/drivers/*/*/Kconfig"
471 source "src/commonlib/storage/Kconfig"
476 source "src/security/Kconfig"
477 source "src/vendorcode/eltan/security/Kconfig"
481 source "src/acpi/Kconfig"
483 # This option is for the current boards/chipsets where SPI flash
484 # is not the boot device. Currently nearly all boards/chipsets assume
485 # SPI flash is the boot device.
486 config BOOT_DEVICE_NOT_SPI_FLASH
490 config BOOT_DEVICE_SPI_FLASH
492 default y if !BOOT_DEVICE_NOT_SPI_FLASH
495 config BOOT_DEVICE_MEMORY_MAPPED
497 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
500 Inform system if SPI is memory-mapped or not.
502 config BOOT_DEVICE_SUPPORTS_WRITES
506 Indicate that the platform has writable boot device
515 default 0x100000 if FLATTENED_DEVICE_TREE
520 default 0x1000 if ARCH_X86
527 source "src/console/Kconfig"
529 config HAVE_ACPI_RESUME
532 depends on RELOCATABLE_RAMSTAGE
534 config DISABLE_ACPI_HIBERNATE
538 Removes S4 from the available sleepstates
540 config RESUME_PATH_SAME_AS_BOOT
542 default y if ARCH_X86
543 depends on HAVE_ACPI_RESUME
545 This option indicates that when a system resumes it takes the
546 same path as a regular boot. e.g. an x86 system runs from the
547 reset vector at 0xfffffff0 on both resume and warm/cold boot.
549 config NO_MONOTONIC_TIMER
552 config HAVE_MONOTONIC_TIMER
554 depends on !NO_MONOTONIC_TIMER
557 The board/chipset provides a monotonic timer.
559 config GENERIC_UDELAY
561 depends on HAVE_MONOTONIC_TIMER
562 default y if !ARCH_X86
564 The board/chipset uses a generic udelay function utilizing the
569 depends on HAVE_MONOTONIC_TIMER
571 Provide a timer queue for performing time-based callbacks.
573 config COOP_MULTITASKING
575 depends on TIMER_QUEUE && ARCH_X86
577 Cooperative multitasking allows callbacks to be multiplexed on the
578 main thread of ramstage. With this enabled it allows for multiple
579 execution paths to take place when they have udelay() calls within
585 depends on COOP_MULTITASKING
587 How many execution threads to cooperatively multitask with.
589 config HAVE_OPTION_TABLE
593 This variable specifies whether a given board has a cmos.layout
594 file containing NVRAM/CMOS bit definitions.
595 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
597 config PCI_IO_CFG_EXT
605 config USE_WATCHDOG_ON_BOOT
613 Enable Unified Memory Architecture for graphics.
618 This variable specifies whether a given board has MP table support.
619 It is usually set in mainboard/*/Kconfig.
620 Whether or not the MP table is actually generated by coreboot
621 is configurable by the user via GENERATE_MP_TABLE.
623 config HAVE_PIRQ_TABLE
626 This variable specifies whether a given board has PIRQ table support.
627 It is usually set in mainboard/*/Kconfig.
628 Whether or not the PIRQ table is actually generated by coreboot
629 is configurable by the user via GENERATE_PIRQ_TABLE.
639 Build support for NHLT (non HD Audio) ACPI table generation.
641 #These Options are here to avoid "undefined" warnings.
642 #The actual selection and help texts are in the following menu.
646 config GENERATE_MP_TABLE
647 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
649 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
651 Generate an MP table (conforming to the Intel MultiProcessor
652 specification 1.4) for this board.
656 config GENERATE_PIRQ_TABLE
657 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
659 default HAVE_PIRQ_TABLE
661 Generate a PIRQ table for this board.
665 config GENERATE_SMBIOS_TABLES
667 bool "Generate SMBIOS tables"
670 Generate SMBIOS tables for this board.
674 config SMBIOS_PROVIDED_BY_MOBO
678 config MAINBOARD_SERIAL_NUMBER
679 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
681 depends on GENERATE_SMBIOS_TABLES
684 The Serial Number to store in SMBIOS structures.
686 config MAINBOARD_VERSION
687 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
689 depends on GENERATE_SMBIOS_TABLES
692 The Version Number to store in SMBIOS structures.
694 config MAINBOARD_SMBIOS_MANUFACTURER
695 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
697 depends on GENERATE_SMBIOS_TABLES
698 default MAINBOARD_VENDOR
700 Override the default Manufacturer stored in SMBIOS structures.
702 config MAINBOARD_SMBIOS_PRODUCT_NAME
703 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
705 depends on GENERATE_SMBIOS_TABLES
706 default MAINBOARD_PART_NUMBER
708 Override the default Product name stored in SMBIOS structures.
710 config SMBIOS_ENCLOSURE_TYPE
712 depends on GENERATE_SMBIOS_TABLES
713 default 0x09 if SYSTEM_TYPE_LAPTOP
714 default 0x1e if SYSTEM_TYPE_TABLET
715 default 0x1f if SYSTEM_TYPE_CONVERTIBLE
716 default 0x20 if SYSTEM_TYPE_DETACHABLE
719 System Enclosure or Chassis Types as defined in SMBIOS specification.
720 The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop,
721 convertible, or tablet enclosure will be used if the appropriate
722 system type is selected.
726 source "payloads/Kconfig"
730 comment "CPU Debug Settings"
731 source "src/cpu/*/Kconfig.debug_cpu"
733 comment "BLOB Debug Settings"
734 source "src/drivers/intel/fsp*/Kconfig.debug_blob"
736 comment "General Debug Settings"
738 # TODO: Better help text and detailed instructions.
740 bool "GDB debugging support"
742 depends on DRIVERS_UART
744 If enabled, you will be able to set breakpoints for gdb debugging.
745 See src/arch/x86/lib/c_start.S for details.
748 bool "Wait for a GDB connection in the ramstage"
752 If enabled, coreboot will wait for a GDB connection in the ramstage.
756 bool "Halt when hitting a BUG() or assertion error"
759 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
761 config HAVE_DEBUG_GPIO
765 bool "Output verbose GPIO debug messages"
766 depends on HAVE_DEBUG_GPIO
769 bool "Output verbose CBFS debug messages"
772 This option enables additional CBFS related debug messages.
774 config HAVE_DEBUG_RAM_SETUP
777 config DEBUG_RAM_SETUP
778 bool "Output verbose RAM init debug messages"
780 depends on HAVE_DEBUG_RAM_SETUP
782 This option enables additional RAM init related debug messages.
783 It is recommended to enable this when debugging issues on your
784 board which might be RAM init related.
786 Note: This option will increase the size of the coreboot image.
791 bool "Check PIRQ table consistency"
793 depends on GENERATE_PIRQ_TABLE
797 config HAVE_DEBUG_SMBUS
801 bool "Output verbose SMBus debug messages"
803 depends on HAVE_DEBUG_SMBUS
805 This option enables additional SMBus (and SPD) debug messages.
807 Note: This option will increase the size of the coreboot image.
812 bool "Output verbose SMI debug messages"
814 depends on HAVE_SMI_HANDLER
815 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
817 This option enables additional SMI related debug messages.
819 Note: This option will increase the size of the coreboot image.
823 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
824 # printk(BIOS_DEBUG, ...) calls.
826 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
830 This option enables additional malloc related debug messages.
832 Note: This option will increase the size of the coreboot image.
836 config DEBUG_CONSOLE_INIT
837 bool "Debug console initialisation code"
840 With this option printk()'s are attempted before console hardware
841 initialisation has been completed. Your mileage may vary.
843 Typically you will need to modify source in console_hw_init() such
844 that a working console appears before the one you want to debug.
848 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
849 # printk(BIOS_DEBUG, ...) calls.
850 config REALMODE_DEBUG
851 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
854 depends on PCI_OPTION_ROM_RUN_REALMODE
856 This option enables additional x86emu related debug messages.
858 Note: This option will increase the time to emulate a ROM.
863 bool "Output verbose x86emu debug messages"
865 depends on PCI_OPTION_ROM_RUN_YABEL
867 This option enables additional x86emu related debug messages.
869 Note: This option will increase the size of the coreboot image.
873 config X86EMU_DEBUG_JMP
874 bool "Trace JMP/RETF"
876 depends on X86EMU_DEBUG
878 Print information about JMP and RETF opcodes from x86emu.
880 Note: This option will increase the size of the coreboot image.
884 config X86EMU_DEBUG_TRACE
885 bool "Trace all opcodes"
887 depends on X86EMU_DEBUG
889 Print _all_ opcodes that are executed by x86emu.
891 WARNING: This will produce a LOT of output and take a long time.
893 Note: This option will increase the size of the coreboot image.
897 config X86EMU_DEBUG_PNP
898 bool "Log Plug&Play accesses"
900 depends on X86EMU_DEBUG
902 Print Plug And Play accesses made by option ROMs.
904 Note: This option will increase the size of the coreboot image.
908 config X86EMU_DEBUG_DISK
911 depends on X86EMU_DEBUG
913 Print Disk I/O related messages.
915 Note: This option will increase the size of the coreboot image.
919 config X86EMU_DEBUG_PMM
922 depends on X86EMU_DEBUG
924 Print messages related to POST Memory Manager (PMM).
926 Note: This option will increase the size of the coreboot image.
931 config X86EMU_DEBUG_VBE
932 bool "Debug VESA BIOS Extensions"
934 depends on X86EMU_DEBUG
936 Print messages related to VESA BIOS Extension (VBE) functions.
938 Note: This option will increase the size of the coreboot image.
942 config X86EMU_DEBUG_INT10
943 bool "Redirect INT10 output to console"
945 depends on X86EMU_DEBUG
947 Let INT10 (i.e. character output) calls print messages to debug output.
949 Note: This option will increase the size of the coreboot image.
953 config X86EMU_DEBUG_INTERRUPTS
954 bool "Log intXX calls"
956 depends on X86EMU_DEBUG
958 Print messages related to interrupt handling.
960 Note: This option will increase the size of the coreboot image.
964 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
965 bool "Log special memory accesses"
967 depends on X86EMU_DEBUG
969 Print messages related to accesses to certain areas of the virtual
970 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
972 Note: This option will increase the size of the coreboot image.
976 config X86EMU_DEBUG_MEM
977 bool "Log all memory accesses"
979 depends on X86EMU_DEBUG
981 Print memory accesses made by option ROM.
982 Note: This also includes accesses to fetch instructions.
984 Note: This option will increase the size of the coreboot image.
988 config X86EMU_DEBUG_IO
989 bool "Log IO accesses"
991 depends on X86EMU_DEBUG
993 Print I/O accesses made by option ROM.
995 Note: This option will increase the size of the coreboot image.
999 config X86EMU_DEBUG_TIMINGS
1000 bool "Output timing information"
1002 depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
1004 Print timing information needed by i915tool.
1008 config DEBUG_SPI_FLASH
1009 bool "Output verbose SPI flash debug messages"
1011 depends on SPI_FLASH
1013 This option enables additional SPI flash related debug messages.
1015 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1016 # Only visible with the right southbridge and loglevel.
1017 config DEBUG_INTEL_ME
1018 bool "Verbose logging for Intel Management Engine"
1021 Enable verbose logging for Intel Management Engine driver that
1022 is present on Intel 6-series chipsets.
1026 bool "Trace function calls"
1029 If enabled, every function will print information to console once
1030 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1031 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1032 of calling function. Please note some printk related functions
1033 are omitted from trace to have good looking console dumps.
1035 config DEBUG_COVERAGE
1036 bool "Debug code coverage"
1040 If enabled, the code coverage hooks in coreboot will output some
1041 information about the coverage data that is dumped.
1043 config DEBUG_BOOT_STATE
1044 bool "Debug boot state machine"
1047 Control debugging of the boot state machine. When selected displays
1048 the state boundaries in ramstage.
1050 config DEBUG_ADA_CODE
1051 bool "Compile debug code in Ada sources"
1054 Add the compiler switch `-gnata` to compile code guarded by
1057 config HAVE_EM100_SUPPORT
1058 bool "Platform can support the Dediprog EM100 SPI emulator"
1060 This is enabled by platforms which can support using the EM100.
1063 bool "Configure image for EM100 usage"
1064 depends on HAVE_EM100_SUPPORT
1066 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1067 over USB. However it only supports a maximum SPI clock of 20MHz and
1068 single data output. Enable this option to use a 20MHz SPI clock and
1069 disable "Dual Output Fast Read" Support.
1071 On AMD platforms this changes the SPI speed at run-time if the
1072 mainboard code supports this. On supported Intel platforms this works
1073 by changing the settings in the descriptor.bin file.
1078 ###############################################################################
1079 # Set variables with no prompt - these can be set anywhere, and putting at
1080 # the end of this file gives the most flexibility.
1082 source "src/lib/Kconfig"
1084 config WARNINGS_ARE_ERRORS
1088 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1089 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1090 # mutually exclusive. One of these options must be selected in the
1091 # mainboard Kconfig if the chipset supports enabling and disabling of
1092 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1093 # in mainboard/Kconfig to know if the button should be enabled or not.
1095 config POWER_BUTTON_DEFAULT_ENABLE
1098 Select when the board has a power button which can optionally be
1099 disabled by the user.
1101 config POWER_BUTTON_DEFAULT_DISABLE
1104 Select when the board has a power button which can optionally be
1105 enabled by the user, e.g. when the board ships with a jumper over
1106 the power switch contacts.
1108 config POWER_BUTTON_FORCE_ENABLE
1111 Select when the board requires that the power button is always
1114 config POWER_BUTTON_FORCE_DISABLE
1117 Select when the board requires that the power button is always
1118 disabled, e.g. when it has been hardwired to ground.
1120 config POWER_BUTTON_IS_OPTIONAL
1122 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1123 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1125 Internal option that controls ENABLE_POWER_BUTTON visibility.
1131 Internal option that controls whether we compile in register scripts.
1133 config MAX_REBOOT_CNT
1137 Internal option that sets the maximum number of bootblock executions allowed
1138 with the normal image enabled before assuming the normal image is defective
1139 and switching to the fallback image.
1141 config UNCOMPRESSED_RAMSTAGE
1144 config NO_XIP_EARLY_STAGES
1146 default n if ARCH_X86
1149 Identify if early stages are eXecute-In-Place(XIP).
1151 config EARLY_CBMEM_LIST
1155 Enable display of CBMEM during romstage and postcar.
1157 config RELOCATABLE_MODULES
1160 If RELOCATABLE_MODULES is selected then support is enabled for
1161 building relocatable modules in the RAM stage. Those modules can be
1162 loaded anywhere and all the relocations are handled automatically.
1164 config GENERIC_GPIO_LIB
1167 If enabled, compile the generic GPIO library. A "generic" GPIO
1168 implies configurability usually found on SoCs, particularly the
1169 ability to control internal pull resistors.
1171 config BOOTBLOCK_CUSTOM
1172 # To be selected by arch, SoC or mainboard if it does not want use the normal
1173 # src/lib/bootblock.c#main() C entry point.
1176 ###############################################################################
1177 # Set default values for symbols created before mainboards. This allows the
1178 # option to be displayed in the general menu, but the default to be loaded in
1179 # the mainboard if desired.
1180 config COMPRESS_RAMSTAGE
1181 default y if !UNCOMPRESSED_RAMSTAGE
1183 config COMPRESS_PRERAM_STAGES
1184 depends on !ARCH_X86
1187 config INCLUDE_CONFIG_FILE
1190 config BOOTSPLASH_FILE
1191 depends on BOOTSPLASH_IMAGE
1192 default "bootsplash.jpg"
1197 config HAVE_BOOTBLOCK
1201 config HAVE_VERSTAGE
1203 depends on VBOOT_SEPARATE_VERSTAGE
1206 config HAVE_ROMSTAGE
1210 config HAVE_RAMSTAGE
1212 default n if RAMPAYLOAD