src/mainboard/lenovo/x220/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
   6  * Copyright (C) 2014 Vladimir Serbinenko
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20  */
  21
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <lib.h>
  25 #include <timestamp.h>
  26 #include <arch/byteorder.h>
  27 #include <arch/io.h>
  28 #include <device/pci_def.h>
  29 #include <device/pnp_def.h>
  30 #include <cpu/x86/lapic.h>
  31 #include <arch/acpi.h>
  32 #include <console/console.h>
  33 #include "northbridge/intel/sandybridge/sandybridge.h"
  34 #include "northbridge/intel/sandybridge/raminit_native.h"
  35 #include "southbridge/intel/bd82x6x/pch.h"
  36 #include "southbridge/intel/bd82x6x/gpio.h"
  37 #include <arch/cpu.h>
  38 #include <cpu/x86/bist.h>
  39 #include <cpu/x86/msr.h>
  40
  41 static void pch_enable_lpc(void)
  42 {
  43         /* X230 EC Decode Range Port60/64, Port62/66 */
  44         /* Enable EC, PS/2 Keyboard/Mouse */
  45         pci_write_config16(PCH_LPC_DEV, LPC_EN,
  46                            CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
  47                            COMA_LPC_EN);
  48
  49         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
  50         pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
  51         pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
  52
  53         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
  54
  55         pci_write_config32(PCH_LPC_DEV, 0xac,
  56                            0x80010000);
  57 }
  58
  59 static void rcba_config(void)
  60 {
  61         /*
  62          *             GFX    INTA -> PIRQA (MSI)
  63          * D28IP_P1IP  WLAN   INTA -> PIRQB
  64          * D28IP_P2IP  ETH0   INTB -> PIRQF
  65          * D28IP_P3IP  SDCARD INTC -> PIRQD
  66          * D29IP_E1P   EHCI1  INTA -> PIRQD
  67          * D26IP_E2P   EHCI2  INTA -> PIRQF
  68          * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
  69          * D31IP_SMIP  SMBUS  INTB -> PIRQH
  70          * D31IP_TTIP  THRT   INTC -> PIRQA
  71          * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
  72          *
  73          * Trackpad interrupt is edge triggered and cannot be shared.
  74          * TRACKPAD                -> PIRQG
  75
  76          */
  77
  78         /* Device interrupt pin register (board specific) */
  79         RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  80                         (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  81         RCBA32(D29IP) = (INTA << D29IP_E1P);
  82         RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
  83                         (INTC << D28IP_P3IP);
  84         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  85         RCBA32(D26IP) = (INTA << D26IP_E2P);
  86         RCBA32(D25IP) = (NOINT << D25IP_LIP);
  87         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  88
  89         /* Device interrupt route registers */
  90         DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
  91         DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
  92         DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
  93         DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
  94         DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
  95         DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
  96         DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
  97
  98         /* Enable IOAPIC (generic) */
  99         RCBA16(OIC) = 0x0100;
 100         /* PCH BWG says to read back the IOAPIC enable register */
 101         (void) RCBA16(OIC);
 102
 103         /* Disable unused devices (board specific) */
 104         RCBA32(FD) = 0x1fe41fe3;
 105         RCBA32(BUC) = 0;
 106 }
 107
 108 static void
 109 init_usb (void)
 110 {
 111         const u32 rcba_dump[64] = {
 112                 /* 3500 */ 0x20000153, 0x20000f57, 0x20000f57, 0x20000f57,
 113                 /* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x20000153,
 114                 /* 3520 */ 0x20000f57, 0x20000f57, 0x20000f57, 0x20000f57,
 115                 /* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000,
 116                 /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 117                 /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 118                 /* 3560 */ 0x020c0001, 0x000024a3, 0x00040002, 0x01000050,
 119                 /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
 120                 /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 121                 /* 3590 */ 0x00000003, 0x000000c0, 0x00000000, 0x00000000,
 122                 /* 35a0 */ 0x0fc00201, 0x102d0200, 0x00000000, 0x00000000,
 123                 /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 124                 /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 125                 /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 126                 /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 127                 /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 128         };
 129         int i;
 130         /* Activate PMBAR.  */
 131         pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
 132         pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
 133         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
 134
 135         /* Unlock registers.  */
 136         outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
 137
 138         for (i = 0; i < 64; i++)
 139                 write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
 140
 141         pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
 142
 143         /* Relock registers.  */
 144         outw (0x0000, DEFAULT_PMBASE | 0x003c);
 145 }
 146
 147 #include <cpu/intel/romstage.h>
 148 void main(unsigned long bist)
 149 {
 150         int s3resume = 0;
 151         spd_raw_data spd[4];
 152
 153         if (MCHBAR16(SSKPD) == 0xCAFE) {
 154                 outb(0x6, 0xcf9);
 155                 hlt ();
 156         }
 157
 158         timestamp_init(get_initial_timestamp());
 159         timestamp_add_now(TS_START_ROMSTAGE);
 160
 161         if (bist == 0)
 162                 enable_lapic();
 163
 164         pch_enable_lpc();
 165
 166         /* Enable GPIOs */
 167         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
 168         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 169
 170         outl(0x3963a5ff, DEFAULT_GPIOBASE);
 171         outl(0x9ebf6aff, DEFAULT_GPIOBASE + 4);
 172         outl(0x66ff7ffb, DEFAULT_GPIOBASE + 0xc);
 173         outl(0x00000000, DEFAULT_GPIOBASE + 0x18);
 174         outl(0x00002043, DEFAULT_GPIOBASE + 0x2c);
 175         outl(0x02ff04fe, DEFAULT_GPIOBASE + 0x30);
 176         outl(0x1f47fbf5, DEFAULT_GPIOBASE + 0x34);
 177         outl(0xbdecff87, DEFAULT_GPIOBASE + 0x38);
 178         outl(0x000000f0, DEFAULT_GPIOBASE + 0x40);
 179         outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44);
 180         outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48);
 181
 182         init_usb();
 183
 184         /* Initialize console device(s) */
 185         console_init();
 186
 187         /* Halt if there was a built in self test failure */
 188         report_bist_failure(bist);
 189
 190         /* Perform some early chipset initialization required
 191          * before RAM initialization can work
 192          */
 193         sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 194         printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 195
 196         s3resume = southbridge_detect_s3_resume();
 197
 198         post_code(0x38);
 199         /* Enable SPD ROMs and DDR-III DRAM */
 200         enable_smbus();
 201
 202         post_code(0x39);
 203
 204         post_code(0x3a);
 205         timestamp_add_now(TS_BEFORE_INITRAM);
 206
 207         memset (spd, 0, sizeof (spd));
 208         read_spd (&spd[0], 0x50);
 209         read_spd (&spd[2], 0x51);
 210
 211         init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume);
 212
 213         timestamp_add_now(TS_AFTER_INITRAM);
 214         post_code(0x3c);
 215
 216         rcba_config();
 217         post_code(0x3d);
 218
 219         northbridge_romstage_finalize(s3resume);
 220
 221         post_code(0x3f);
 222         timestamp_add_now(TS_END_ROMSTAGE);
 223 }