Combine Broadwell Chromeboxes using variant board scheme
[coreboot.git] / src / mainboard / google / jecht / acpi_tables.c
blob0c6a37222decf204612cedd1140dfd7672defd1c
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2014 Google Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <types.h>
17 #include <string.h>
18 #include <cbmem.h>
19 #include <console/console.h>
20 #include <arch/acpi.h>
21 #include <arch/ioapic.h>
22 #include <arch/acpigen.h>
23 #include <arch/smp/mpspec.h>
24 #include <device/device.h>
25 #include <device/pci.h>
26 #include <device/pci_ids.h>
27 #include <soc/acpi.h>
28 #include <soc/nvs.h>
29 #include <variant/thermal.h>
32 static void acpi_update_thermal_table(global_nvs_t *gnvs)
34 gnvs->tmps = TEMPERATURE_SENSOR_ID;
35 gnvs->tcrt = CRITICAL_TEMPERATURE;
36 gnvs->tpsv = PASSIVE_TEMPERATURE;
37 gnvs->tmax = MAX_TEMPERATURE;
38 gnvs->flvl = 1;
41 void acpi_create_gnvs(global_nvs_t *gnvs)
43 acpi_init_gnvs(gnvs);
45 /* Enable USB ports in S3 */
46 gnvs->s3u0 = 1;
48 /* Disable USB ports in S5 */
49 gnvs->s5u0 = 0;
51 acpi_update_thermal_table(gnvs);
54 unsigned long acpi_fill_madt(unsigned long current)
56 /* Local APICs */
57 current = acpi_create_madt_lapics(current);
59 /* IOAPIC */
60 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
61 2, IO_APIC_ADDR, 0);
63 return acpi_madt_irq_overrides(current);