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split dev_queue
[cor.git] / drivers / gpio / gpio-mxs.c
blobc4a314c68555df12f21aec2e1544e6f138bd1d67
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 //
6 // Based on code from Freescale,
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8
9 #include <linux/err.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/module.h>
22
23 #define MXS_SET 0x4
24 #define MXS_CLR 0x8
25
26 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
27 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
28 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
29 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
30 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
31 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
32 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
33 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
34
35 #define GPIO_INT_FALL_EDGE 0x0
36 #define GPIO_INT_LOW_LEV 0x1
37 #define GPIO_INT_RISE_EDGE 0x2
38 #define GPIO_INT_HIGH_LEV 0x3
39 #define GPIO_INT_LEV_MASK (1 << 0)
40 #define GPIO_INT_POL_MASK (1 << 1)
41
42 enum mxs_gpio_id {
43 IMX23_GPIO,
44 IMX28_GPIO,
45 };
46
47 struct mxs_gpio_port {
48 void __iomem *base;
49 int id;
50 int irq;
51 struct irq_domain *domain;
52 struct gpio_chip gc;
53 struct device *dev;
54 enum mxs_gpio_id devid;
55 u32 both_edges;
56 };
57
58 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
59 {
60 return port->devid == IMX23_GPIO;
61 }
62
63 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
64 {
65 return port->devid == IMX28_GPIO;
66 }
67
68 /* Note: This driver assumes 32 GPIOs are handled in one register */
69
70 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
71 {
72 u32 val;
73 u32 pin_mask = 1 << d->hwirq;
74 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
75 struct irq_chip_type *ct = irq_data_get_chip_type(d);
76 struct mxs_gpio_port *port = gc->private;
77 void __iomem *pin_addr;
78 int edge;
79
80 if (!(ct->type & type))
81 if (irq_setup_alt_chip(d, type))
82 return -EINVAL;
83
84 port->both_edges &= ~pin_mask;
85 switch (type) {
86 case IRQ_TYPE_EDGE_BOTH:
87 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask;
88 if (val)
89 edge = GPIO_INT_FALL_EDGE;
90 else
91 edge = GPIO_INT_RISE_EDGE;
92 port->both_edges |= pin_mask;
93 break;
94 case IRQ_TYPE_EDGE_RISING:
95 edge = GPIO_INT_RISE_EDGE;
96 break;
97 case IRQ_TYPE_EDGE_FALLING:
98 edge = GPIO_INT_FALL_EDGE;
99 break;
100 case IRQ_TYPE_LEVEL_LOW:
101 edge = GPIO_INT_LOW_LEV;
102 break;
103 case IRQ_TYPE_LEVEL_HIGH:
104 edge = GPIO_INT_HIGH_LEV;
105 break;
106 default:
107 return -EINVAL;
108 }
109
110 /* set level or edge */
111 pin_addr = port->base + PINCTRL_IRQLEV(port);
112 if (edge & GPIO_INT_LEV_MASK) {
113 writel(pin_mask, pin_addr + MXS_SET);
114 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET);
115 } else {
116 writel(pin_mask, pin_addr + MXS_CLR);
117 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET);
118 }
119
120 /* set polarity */
121 pin_addr = port->base + PINCTRL_IRQPOL(port);
122 if (edge & GPIO_INT_POL_MASK)
123 writel(pin_mask, pin_addr + MXS_SET);
124 else
125 writel(pin_mask, pin_addr + MXS_CLR);
126
127 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
128
129 return 0;
130 }
131
132 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
133 {
134 u32 bit, val, edge;
135 void __iomem *pin_addr;
136
137 bit = 1 << gpio;
138
139 pin_addr = port->base + PINCTRL_IRQPOL(port);
140 val = readl(pin_addr);
141 edge = val & bit;
142
143 if (edge)
144 writel(bit, pin_addr + MXS_CLR);
145 else
146 writel(bit, pin_addr + MXS_SET);
147 }
148
149 /* MXS has one interrupt *per* gpio port */
150 static void mxs_gpio_irq_handler(struct irq_desc *desc)
151 {
152 u32 irq_stat;
153 struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
154
155 desc->irq_data.chip->irq_ack(&desc->irq_data);
156
157 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
158 readl(port->base + PINCTRL_IRQEN(port));
159
160 while (irq_stat != 0) {
161 int irqoffset = fls(irq_stat) - 1;
162 if (port->both_edges & (1 << irqoffset))
163 mxs_flip_edge(port, irqoffset);
164
165 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
166 irq_stat &= ~(1 << irqoffset);
167 }
168 }
169
170 /*
171 * Set interrupt number "irq" in the GPIO as a wake-up source.
172 * While system is running, all registered GPIO interrupts need to have
173 * wake-up enabled. When system is suspended, only selected GPIO interrupts
174 * need to have wake-up enabled.
175 * @param irq interrupt source number
176 * @param enable enable as wake-up if equal to non-zero
177 * @return This function returns 0 on success.
178 */
179 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
180 {
181 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
182 struct mxs_gpio_port *port = gc->private;
183
184 if (enable)
185 enable_irq_wake(port->irq);
186 else
187 disable_irq_wake(port->irq);
188
189 return 0;
190 }
191
192 static int mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
193 {
194 struct irq_chip_generic *gc;
195 struct irq_chip_type *ct;
196 int rv;
197
198 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
199 port->base, handle_level_irq);
200 if (!gc)
201 return -ENOMEM;
202
203 gc->private = port;
204
205 ct = &gc->chip_types[0];
206 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
207 ct->chip.irq_ack = irq_gc_ack_set_bit;
208 ct->chip.irq_mask = irq_gc_mask_disable_reg;
209 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
210 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
211 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
212 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
213 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
214 ct->regs.enable = PINCTRL_PIN2IRQ(port) + MXS_SET;
215 ct->regs.disable = PINCTRL_PIN2IRQ(port) + MXS_CLR;
216
217 ct = &gc->chip_types[1];
218 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
219 ct->chip.irq_ack = irq_gc_ack_set_bit;
220 ct->chip.irq_mask = irq_gc_mask_disable_reg;
221 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
222 ct->chip.irq_set_type = mxs_gpio_set_irq_type;
223 ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
224 ct->chip.flags = IRQCHIP_SET_TYPE_MASKED;
225 ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
226 ct->regs.enable = PINCTRL_IRQEN(port) + MXS_SET;
227 ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
228 ct->handler = handle_level_irq;
229
230 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
231 IRQ_GC_INIT_NESTED_LOCK,
232 IRQ_NOREQUEST, 0);
233
234 return rv;
235 }
236
237 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
238 {
239 struct mxs_gpio_port *port = gpiochip_get_data(gc);
240
241 return irq_find_mapping(port->domain, offset);
242 }
243
244 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
245 {
246 struct mxs_gpio_port *port = gpiochip_get_data(gc);
247 u32 mask = 1 << offset;
248 u32 dir;
249
250 dir = readl(port->base + PINCTRL_DOE(port));
251 if (dir & mask)
252 return GPIO_LINE_DIRECTION_OUT;
253
254 return GPIO_LINE_DIRECTION_IN;
255 }
256
257 static const struct platform_device_id mxs_gpio_ids[] = {
258 {
259 .name = "imx23-gpio",
260 .driver_data = IMX23_GPIO,
261 }, {
262 .name = "imx28-gpio",
263 .driver_data = IMX28_GPIO,
264 }, {
265 /* sentinel */
266 }
267 };
268 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
269
270 static const struct of_device_id mxs_gpio_dt_ids[] = {
271 { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
272 { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
273 { /* sentinel */ }
274 };
275 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
276
277 static int mxs_gpio_probe(struct platform_device *pdev)
278 {
279 struct device_node *np = pdev->dev.of_node;
280 struct device_node *parent;
281 static void __iomem *base;
282 struct mxs_gpio_port *port;
283 int irq_base;
284 int err;
285
286 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
287 if (!port)
288 return -ENOMEM;
289
290 port->id = of_alias_get_id(np, "gpio");
291 if (port->id < 0)
292 return port->id;
293 port->devid = (enum mxs_gpio_id)of_device_get_match_data(&pdev->dev);
294 port->dev = &pdev->dev;
295 port->irq = platform_get_irq(pdev, 0);
296 if (port->irq < 0)
297 return port->irq;
298
299 /*
300 * map memory region only once, as all the gpio ports
301 * share the same one
302 */
303 if (!base) {
304 parent = of_get_parent(np);
305 base = of_iomap(parent, 0);
306 of_node_put(parent);
307 if (!base)
308 return -EADDRNOTAVAIL;
309 }
310 port->base = base;
311
312 /* initially disable the interrupts */
313 writel(0, port->base + PINCTRL_PIN2IRQ(port));
314 writel(0, port->base + PINCTRL_IRQEN(port));
315
316 /* clear address has to be used to clear IRQSTAT bits */
317 writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
318
319 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
320 if (irq_base < 0) {
321 err = irq_base;
322 goto out_iounmap;
323 }
324
325 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
326 &irq_domain_simple_ops, NULL);
327 if (!port->domain) {
328 err = -ENODEV;
329 goto out_iounmap;
330 }
331
332 /* gpio-mxs can be a generic irq chip */
333 err = mxs_gpio_init_gc(port, irq_base);
334 if (err < 0)
335 goto out_irqdomain_remove;
336
337 /* setup one handler for each entry */
338 irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
339 port);
340
341 err = bgpio_init(&port->gc, &pdev->dev, 4,
342 port->base + PINCTRL_DIN(port),
343 port->base + PINCTRL_DOUT(port) + MXS_SET,
344 port->base + PINCTRL_DOUT(port) + MXS_CLR,
345 port->base + PINCTRL_DOE(port), NULL, 0);
346 if (err)
347 goto out_irqdomain_remove;
348
349 port->gc.to_irq = mxs_gpio_to_irq;
350 port->gc.get_direction = mxs_gpio_get_direction;
351 port->gc.base = port->id * 32;
352
353 err = gpiochip_add_data(&port->gc, port);
354 if (err)
355 goto out_irqdomain_remove;
356
357 return 0;
358
359 out_irqdomain_remove:
360 irq_domain_remove(port->domain);
361 out_iounmap:
362 iounmap(port->base);
363 return err;
364 }
365
366 static struct platform_driver mxs_gpio_driver = {
367 .driver = {
368 .name = "gpio-mxs",
369 .of_match_table = mxs_gpio_dt_ids,
370 .suppress_bind_attrs = true,
371 },
372 .probe = mxs_gpio_probe,
373 .id_table = mxs_gpio_ids,
374 };
375
376 static int __init mxs_gpio_init(void)
377 {
378 return platform_driver_register(&mxs_gpio_driver);
379 }
380 postcore_initcall(mxs_gpio_init);
381
382 MODULE_AUTHOR("Freescale Semiconductor, "
383 "Daniel Mack <danielncaiaq.de>, "
384 "Juergen Beisert <kernel@pengutronix.de>");
385 MODULE_DESCRIPTION("Freescale MXS GPIO");
386 MODULE_LICENSE("GPL");
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