?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
split dev_queue
[cor.git] / drivers / clk / sunxi-ng / ccu-sun8i-v3s.c
blob5c779eec454b6edc734ced3a9fd7d5b1a020f4de
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
4 *
5 * Based on ccu-sun8i-h3.c, which is:
6 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/io.h>
11 #include <linux/of_address.h>
12
13 #include "ccu_common.h"
14 #include "ccu_reset.h"
15
16 #include "ccu_div.h"
17 #include "ccu_gate.h"
18 #include "ccu_mp.h"
19 #include "ccu_mult.h"
20 #include "ccu_nk.h"
21 #include "ccu_nkm.h"
22 #include "ccu_nkmp.h"
23 #include "ccu_nm.h"
24 #include "ccu_phase.h"
25
26 #include "ccu-sun8i-v3s.h"
27
28 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
29 "osc24M", 0x000,
30 8, 5, /* N */
31 4, 2, /* K */
32 0, 2, /* M */
33 16, 2, /* P */
34 BIT(31), /* gate */
35 BIT(28), /* lock */
36 0);
37
38 /*
39 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
40 * the base (2x, 4x and 8x), and one variable divider (the one true
41 * pll audio).
42 *
43 * We don't have any need for the variable divider for now, so we just
44 * hardcode it to match with the clock names
45 */
46 #define SUN8I_V3S_PLL_AUDIO_REG 0x008
47
48 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
49 "osc24M", 0x008,
50 8, 7, /* N */
51 0, 5, /* M */
52 BIT(31), /* gate */
53 BIT(28), /* lock */
54 0);
55
56 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
57 "osc24M", 0x0010,
58 8, 7, /* N */
59 0, 4, /* M */
60 BIT(24), /* frac enable */
61 BIT(25), /* frac select */
62 270000000, /* frac rate 0 */
63 297000000, /* frac rate 1 */
64 BIT(31), /* gate */
65 BIT(28), /* lock */
66 0);
67
68 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
69 "osc24M", 0x0018,
70 8, 7, /* N */
71 0, 4, /* M */
72 BIT(24), /* frac enable */
73 BIT(25), /* frac select */
74 270000000, /* frac rate 0 */
75 297000000, /* frac rate 1 */
76 BIT(31), /* gate */
77 BIT(28), /* lock */
78 0);
79
80 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
81 "osc24M", 0x020,
82 8, 5, /* N */
83 4, 2, /* K */
84 0, 2, /* M */
85 BIT(31), /* gate */
86 BIT(28), /* lock */
87 0);
88
89 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
90 "osc24M", 0x028,
91 8, 5, /* N */
92 4, 2, /* K */
93 BIT(31), /* gate */
94 BIT(28), /* lock */
95 2, /* post-div */
96 0);
97
98 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp",
99 "osc24M", 0x002c,
100 8, 7, /* N */
101 0, 4, /* M */
102 BIT(24), /* frac enable */
103 BIT(25), /* frac select */
104 270000000, /* frac rate 0 */
105 297000000, /* frac rate 1 */
106 BIT(31), /* gate */
107 BIT(28), /* lock */
108 0);
109
110 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
111 "osc24M", 0x044,
112 8, 5, /* N */
113 4, 2, /* K */
114 BIT(31), /* gate */
115 BIT(28), /* lock */
116 2, /* post-div */
117 0);
118
119 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
120 "osc24M", 0x04c,
121 8, 7, /* N */
122 0, 2, /* M */
123 BIT(31), /* gate */
124 BIT(28), /* lock */
125 0);
126
127 static const char * const cpu_parents[] = { "osc32k", "osc24M",
128 "pll-cpu", "pll-cpu" };
129 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
130 0x050, 16, 2, CLK_IS_CRITICAL);
131
132 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
133
134 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
135 "axi", "pll-periph0" };
136 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
137 { .index = 3, .shift = 6, .width = 2 },
138 };
139 static struct ccu_div ahb1_clk = {
140 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
141
142 .mux = {
143 .shift = 12,
144 .width = 2,
145
146 .var_predivs = ahb1_predivs,
147 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
148 },
149
150 .common = {
151 .reg = 0x054,
152 .features = CCU_FEATURE_VARIABLE_PREDIV,
153 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
154 ahb1_parents,
155 &ccu_div_ops,
156 0),
157 },
158 };
159
160 static struct clk_div_table apb1_div_table[] = {
161 { .val = 0, .div = 2 },
162 { .val = 1, .div = 2 },
163 { .val = 2, .div = 4 },
164 { .val = 3, .div = 8 },
165 { /* Sentinel */ },
166 };
167 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
168 0x054, 8, 2, apb1_div_table, 0);
169
170 static const char * const apb2_parents[] = { "osc32k", "osc24M",
171 "pll-periph0", "pll-periph0" };
172 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
173 0, 5, /* M */
174 16, 2, /* P */
175 24, 2, /* mux */
176 0);
177
178 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" };
179 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
180 { .index = 1, .div = 2 },
181 };
182 static struct ccu_mux ahb2_clk = {
183 .mux = {
184 .shift = 0,
185 .width = 1,
186 .fixed_predivs = ahb2_fixed_predivs,
187 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs),
188 },
189
190 .common = {
191 .reg = 0x05c,
192 .features = CCU_FEATURE_FIXED_PREDIV,
193 .hw.init = CLK_HW_INIT_PARENTS("ahb2",
194 ahb2_parents,
195 &ccu_mux_ops,
196 0),
197 },
198 };
199
200 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
201 0x060, BIT(5), 0);
202 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
203 0x060, BIT(6), 0);
204 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
205 0x060, BIT(8), 0);
206 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
207 0x060, BIT(9), 0);
208 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
209 0x060, BIT(10), 0);
210 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
211 0x060, BIT(14), 0);
212 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
213 0x060, BIT(17), 0);
214 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
215 0x060, BIT(19), 0);
216 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
217 0x060, BIT(20), 0);
218 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
219 0x060, BIT(24), 0);
220 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
221 0x060, BIT(26), 0);
222 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
223 0x060, BIT(29), 0);
224
225 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
226 0x064, BIT(0), 0);
227 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
228 0x064, BIT(4), 0);
229 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
230 0x064, BIT(8), 0);
231 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
232 0x064, BIT(12), 0);
233
234 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
235 0x068, BIT(0), 0);
236 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
237 0x068, BIT(5), 0);
238 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
239 0x068, BIT(12), 0);
240
241 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
242 0x06c, BIT(0), 0);
243 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
244 0x06c, BIT(1), 0);
245 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
246 0x06c, BIT(16), 0);
247 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
248 0x06c, BIT(17), 0);
249 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
250 0x06c, BIT(18), 0);
251
252 static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
253 0x070, BIT(0), 0);
254 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
255 0x070, BIT(7), 0);
256
257 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
258 "pll-periph1" };
259 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
260 0, 4, /* M */
261 16, 2, /* P */
262 24, 2, /* mux */
263 BIT(31), /* gate */
264 0);
265
266 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
267 0x088, 20, 3, 0);
268 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
269 0x088, 8, 3, 0);
270
271 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
272 0, 4, /* M */
273 16, 2, /* P */
274 24, 2, /* mux */
275 BIT(31), /* gate */
276 0);
277
278 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
279 0x08c, 20, 3, 0);
280 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
281 0x08c, 8, 3, 0);
282
283 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
284 0, 4, /* M */
285 16, 2, /* P */
286 24, 2, /* mux */
287 BIT(31), /* gate */
288 0);
289
290 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
291 0x090, 20, 3, 0);
292 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
293 0x090, 8, 3, 0);
294
295 static const char * const ce_parents[] = { "osc24M", "pll-periph0", };
296
297 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
298 0, 4, /* M */
299 16, 2, /* P */
300 24, 2, /* mux */
301 BIT(31), /* gate */
302 0);
303
304 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
305 0, 4, /* M */
306 16, 2, /* P */
307 24, 2, /* mux */
308 BIT(31), /* gate */
309 0);
310
311 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
312 "pll-audio-2x", "pll-audio" };
313 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
314 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
315
316 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
317 0x0cc, BIT(8), 0);
318 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
319 0x0cc, BIT(16), 0);
320
321 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1",
322 "pll-periph0-2x" };
323 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
324 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
325
326 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
327 0x100, BIT(0), 0);
328 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
329 0x100, BIT(1), 0);
330 static SUNXI_CCU_GATE(dram_ehci_clk, "dram-ehci", "dram",
331 0x100, BIT(17), 0);
332 static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram",
333 0x100, BIT(18), 0);
334
335 static const char * const de_parents[] = { "pll-video", "pll-periph0" };
336 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
337 0x104, 0, 4, 24, 2, BIT(31),
338 CLK_SET_RATE_PARENT);
339
340 static const char * const tcon_parents[] = { "pll-video" };
341 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
342 0x118, 0, 4, 24, 3, BIT(31), 0);
343
344 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M",
345 0x130, BIT(31), 0);
346
347 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
348 "pll-periph0", "pll-periph1" };
349 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
350 0x130, 0, 5, 8, 3, BIT(15), 0);
351
352 static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
353 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
354 0x134, 16, 4, 24, 3, BIT(31), 0);
355
356 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
357 0x134, 0, 5, 8, 3, BIT(15), 0);
358
359 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
360 0x13c, 16, 3, BIT(31), 0);
361
362 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
363 0x140, BIT(31), CLK_SET_RATE_PARENT);
364 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
365 0x144, BIT(31), 0);
366
367 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
368 "pll-ddr" };
369 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
370 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
371
372 static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0",
373 "pll-isp" };
374 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
375 0x16c, 0, 3, 24, 2, BIT(31), 0);
376
377 static struct ccu_common *sun8i_v3s_ccu_clks[] = {
378 &pll_cpu_clk.common,
379 &pll_audio_base_clk.common,
380 &pll_video_clk.common,
381 &pll_ve_clk.common,
382 &pll_ddr0_clk.common,
383 &pll_periph0_clk.common,
384 &pll_isp_clk.common,
385 &pll_periph1_clk.common,
386 &pll_ddr1_clk.common,
387 &cpu_clk.common,
388 &axi_clk.common,
389 &ahb1_clk.common,
390 &apb1_clk.common,
391 &apb2_clk.common,
392 &ahb2_clk.common,
393 &bus_ce_clk.common,
394 &bus_dma_clk.common,
395 &bus_mmc0_clk.common,
396 &bus_mmc1_clk.common,
397 &bus_mmc2_clk.common,
398 &bus_dram_clk.common,
399 &bus_emac_clk.common,
400 &bus_hstimer_clk.common,
401 &bus_spi0_clk.common,
402 &bus_otg_clk.common,
403 &bus_ehci0_clk.common,
404 &bus_ohci0_clk.common,
405 &bus_ve_clk.common,
406 &bus_tcon0_clk.common,
407 &bus_csi_clk.common,
408 &bus_de_clk.common,
409 &bus_codec_clk.common,
410 &bus_pio_clk.common,
411 &bus_i2c0_clk.common,
412 &bus_i2c1_clk.common,
413 &bus_uart0_clk.common,
414 &bus_uart1_clk.common,
415 &bus_uart2_clk.common,
416 &bus_ephy_clk.common,
417 &bus_dbg_clk.common,
418 &mmc0_clk.common,
419 &mmc0_sample_clk.common,
420 &mmc0_output_clk.common,
421 &mmc1_clk.common,
422 &mmc1_sample_clk.common,
423 &mmc1_output_clk.common,
424 &mmc2_clk.common,
425 &mmc2_sample_clk.common,
426 &mmc2_output_clk.common,
427 &ce_clk.common,
428 &spi0_clk.common,
429 &usb_phy0_clk.common,
430 &usb_ohci0_clk.common,
431 &dram_clk.common,
432 &dram_ve_clk.common,
433 &dram_csi_clk.common,
434 &dram_ohci_clk.common,
435 &dram_ehci_clk.common,
436 &de_clk.common,
437 &tcon_clk.common,
438 &csi_misc_clk.common,
439 &csi0_mclk_clk.common,
440 &csi1_sclk_clk.common,
441 &csi1_mclk_clk.common,
442 &ve_clk.common,
443 &ac_dig_clk.common,
444 &avs_clk.common,
445 &mbus_clk.common,
446 &mipi_csi_clk.common,
447 };
448
449 static const struct clk_hw *clk_parent_pll_audio[] = {
450 &pll_audio_base_clk.common.hw
451 };
452
453 static struct ccu_common *sun8i_v3_ccu_clks[] = {
454 &pll_cpu_clk.common,
455 &pll_audio_base_clk.common,
456 &pll_video_clk.common,
457 &pll_ve_clk.common,
458 &pll_ddr0_clk.common,
459 &pll_periph0_clk.common,
460 &pll_isp_clk.common,
461 &pll_periph1_clk.common,
462 &pll_ddr1_clk.common,
463 &cpu_clk.common,
464 &axi_clk.common,
465 &ahb1_clk.common,
466 &apb1_clk.common,
467 &apb2_clk.common,
468 &ahb2_clk.common,
469 &bus_ce_clk.common,
470 &bus_dma_clk.common,
471 &bus_mmc0_clk.common,
472 &bus_mmc1_clk.common,
473 &bus_mmc2_clk.common,
474 &bus_dram_clk.common,
475 &bus_emac_clk.common,
476 &bus_hstimer_clk.common,
477 &bus_spi0_clk.common,
478 &bus_otg_clk.common,
479 &bus_ehci0_clk.common,
480 &bus_ohci0_clk.common,
481 &bus_ve_clk.common,
482 &bus_tcon0_clk.common,
483 &bus_csi_clk.common,
484 &bus_de_clk.common,
485 &bus_codec_clk.common,
486 &bus_pio_clk.common,
487 &bus_i2s0_clk.common,
488 &bus_i2c0_clk.common,
489 &bus_i2c1_clk.common,
490 &bus_uart0_clk.common,
491 &bus_uart1_clk.common,
492 &bus_uart2_clk.common,
493 &bus_ephy_clk.common,
494 &bus_dbg_clk.common,
495 &mmc0_clk.common,
496 &mmc0_sample_clk.common,
497 &mmc0_output_clk.common,
498 &mmc1_clk.common,
499 &mmc1_sample_clk.common,
500 &mmc1_output_clk.common,
501 &mmc2_clk.common,
502 &mmc2_sample_clk.common,
503 &mmc2_output_clk.common,
504 &ce_clk.common,
505 &spi0_clk.common,
506 &i2s0_clk.common,
507 &usb_phy0_clk.common,
508 &usb_ohci0_clk.common,
509 &dram_clk.common,
510 &dram_ve_clk.common,
511 &dram_csi_clk.common,
512 &dram_ohci_clk.common,
513 &dram_ehci_clk.common,
514 &de_clk.common,
515 &tcon_clk.common,
516 &csi_misc_clk.common,
517 &csi0_mclk_clk.common,
518 &csi1_sclk_clk.common,
519 &csi1_mclk_clk.common,
520 &ve_clk.common,
521 &ac_dig_clk.common,
522 &avs_clk.common,
523 &mbus_clk.common,
524 &mipi_csi_clk.common,
525 };
526
527 /* We hardcode the divider to 4 for now */
528 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
529 clk_parent_pll_audio,
530 4, 1, CLK_SET_RATE_PARENT);
531 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
532 clk_parent_pll_audio,
533 2, 1, CLK_SET_RATE_PARENT);
534 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
535 clk_parent_pll_audio,
536 1, 1, CLK_SET_RATE_PARENT);
537 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
538 clk_parent_pll_audio,
539 1, 2, CLK_SET_RATE_PARENT);
540 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
541 &pll_periph0_clk.common.hw,
542 1, 2, 0);
543
544 static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
545 .hws = {
546 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
547 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
548 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
549 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
550 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
551 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
552 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
553 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
554 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
555 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
556 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
557 [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
558 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
559 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
560 [CLK_CPU] = &cpu_clk.common.hw,
561 [CLK_AXI] = &axi_clk.common.hw,
562 [CLK_AHB1] = &ahb1_clk.common.hw,
563 [CLK_APB1] = &apb1_clk.common.hw,
564 [CLK_APB2] = &apb2_clk.common.hw,
565 [CLK_AHB2] = &ahb2_clk.common.hw,
566 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
567 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
568 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
569 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
570 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
571 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
572 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
573 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
574 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
575 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
576 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
577 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
578 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
579 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
580 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
581 [CLK_BUS_DE] = &bus_de_clk.common.hw,
582 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
583 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
584 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
585 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
586 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
587 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
588 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
589 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
590 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
591 [CLK_MMC0] = &mmc0_clk.common.hw,
592 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
593 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
594 [CLK_MMC1] = &mmc1_clk.common.hw,
595 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
596 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
597 [CLK_MMC2] = &mmc2_clk.common.hw,
598 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
599 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
600 [CLK_CE] = &ce_clk.common.hw,
601 [CLK_SPI0] = &spi0_clk.common.hw,
602 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
603 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
604 [CLK_DRAM] = &dram_clk.common.hw,
605 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
606 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
607 [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
608 [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
609 [CLK_DE] = &de_clk.common.hw,
610 [CLK_TCON0] = &tcon_clk.common.hw,
611 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
612 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
613 [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
614 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
615 [CLK_VE] = &ve_clk.common.hw,
616 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
617 [CLK_AVS] = &avs_clk.common.hw,
618 [CLK_MBUS] = &mbus_clk.common.hw,
619 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
620 },
621 .num = CLK_NUMBER,
622 };
623
624 static struct clk_hw_onecell_data sun8i_v3_hw_clks = {
625 .hws = {
626 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
627 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
628 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
629 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
630 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
631 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
632 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
633 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
634 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
635 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
636 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
637 [CLK_PLL_ISP] = &pll_isp_clk.common.hw,
638 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
639 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
640 [CLK_CPU] = &cpu_clk.common.hw,
641 [CLK_AXI] = &axi_clk.common.hw,
642 [CLK_AHB1] = &ahb1_clk.common.hw,
643 [CLK_APB1] = &apb1_clk.common.hw,
644 [CLK_APB2] = &apb2_clk.common.hw,
645 [CLK_AHB2] = &ahb2_clk.common.hw,
646 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
647 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
648 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
649 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
650 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
651 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
652 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
653 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
654 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
655 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
656 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
657 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
658 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
659 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
660 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
661 [CLK_BUS_DE] = &bus_de_clk.common.hw,
662 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
663 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
664 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
665 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
666 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
667 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
668 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
669 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
670 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
671 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
672 [CLK_MMC0] = &mmc0_clk.common.hw,
673 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
674 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
675 [CLK_MMC1] = &mmc1_clk.common.hw,
676 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
677 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
678 [CLK_MMC2] = &mmc2_clk.common.hw,
679 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
680 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
681 [CLK_CE] = &ce_clk.common.hw,
682 [CLK_SPI0] = &spi0_clk.common.hw,
683 [CLK_I2S0] = &i2s0_clk.common.hw,
684 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
685 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
686 [CLK_DRAM] = &dram_clk.common.hw,
687 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
688 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
689 [CLK_DRAM_EHCI] = &dram_ehci_clk.common.hw,
690 [CLK_DRAM_OHCI] = &dram_ohci_clk.common.hw,
691 [CLK_DE] = &de_clk.common.hw,
692 [CLK_TCON0] = &tcon_clk.common.hw,
693 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
694 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
695 [CLK_CSI1_SCLK] = &csi1_sclk_clk.common.hw,
696 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
697 [CLK_VE] = &ve_clk.common.hw,
698 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
699 [CLK_AVS] = &avs_clk.common.hw,
700 [CLK_MBUS] = &mbus_clk.common.hw,
701 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
702 },
703 .num = CLK_NUMBER,
704 };
705
706 static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
707 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
708
709 [RST_MBUS] = { 0x0fc, BIT(31) },
710
711 [RST_BUS_CE] = { 0x2c0, BIT(5) },
712 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
713 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
714 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
715 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
716 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
717 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
718 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
719 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
720 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
721 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
722 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
723
724 [RST_BUS_VE] = { 0x2c4, BIT(0) },
725 [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
726 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
727 [RST_BUS_DE] = { 0x2c4, BIT(12) },
728 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
729
730 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
731
732 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
733
734 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
735 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
736 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
737 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
738 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
739 };
740
741 static struct ccu_reset_map sun8i_v3_ccu_resets[] = {
742 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
743
744 [RST_MBUS] = { 0x0fc, BIT(31) },
745
746 [RST_BUS_CE] = { 0x2c0, BIT(5) },
747 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
748 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
749 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
750 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
751 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
752 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
753 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
754 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
755 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
756 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
757 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
758
759 [RST_BUS_VE] = { 0x2c4, BIT(0) },
760 [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
761 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
762 [RST_BUS_DE] = { 0x2c4, BIT(12) },
763 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
764
765 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
766
767 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
768 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
769
770 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
771 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
772 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
773 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
774 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
775 };
776
777 static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
778 .ccu_clks = sun8i_v3s_ccu_clks,
779 .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
780
781 .hw_clks = &sun8i_v3s_hw_clks,
782
783 .resets = sun8i_v3s_ccu_resets,
784 .num_resets = ARRAY_SIZE(sun8i_v3s_ccu_resets),
785 };
786
787 static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
788 .ccu_clks = sun8i_v3_ccu_clks,
789 .num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks),
790
791 .hw_clks = &sun8i_v3_hw_clks,
792
793 .resets = sun8i_v3_ccu_resets,
794 .num_resets = ARRAY_SIZE(sun8i_v3_ccu_resets),
795 };
796
797 static void __init sun8i_v3_v3s_ccu_init(struct device_node *node,
798 const struct sunxi_ccu_desc *ccu_desc)
799 {
800 void __iomem *reg;
801 u32 val;
802
803 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
804 if (IS_ERR(reg)) {
805 pr_err("%pOF: Could not map the clock registers\n", node);
806 return;
807 }
808
809 /* Force the PLL-Audio-1x divider to 4 */
810 val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
811 val &= ~GENMASK(19, 16);
812 writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
813
814 sunxi_ccu_probe(node, reg, ccu_desc);
815 }
816
817 static void __init sun8i_v3s_ccu_setup(struct device_node *node)
818 {
819 sun8i_v3_v3s_ccu_init(node, &sun8i_v3s_ccu_desc);
820 }
821
822 static void __init sun8i_v3_ccu_setup(struct device_node *node)
823 {
824 sun8i_v3_v3s_ccu_init(node, &sun8i_v3_ccu_desc);
825 }
826
827 CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
828 sun8i_v3s_ccu_setup);
829
830 CLK_OF_DECLARE(sun8i_v3_ccu, "allwinner,sun8i-v3-ccu",
831 sun8i_v3_ccu_setup);
connection oriented routing