drivers/clk/clk-versaclock5.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for IDT Versaclock 5
   4  *
   5  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
   6  */
   7
   8 /*
   9  * Possible optimizations:
  10  * - Use spread spectrum
  11  * - Use integer divider in FOD if applicable
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/delay.h>
  17 #include <linux/i2c.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/mod_devicetable.h>
  20 #include <linux/module.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/rational.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26
  27 /* VersaClock5 registers */
  28 #define VC5_OTP_CONTROL                         0x00
  29
  30 /* Factory-reserved register block */
  31 #define VC5_RSVD_DEVICE_ID                      0x01
  32 #define VC5_RSVD_ADC_GAIN_7_0                   0x02
  33 #define VC5_RSVD_ADC_GAIN_15_8                  0x03
  34 #define VC5_RSVD_ADC_OFFSET_7_0                 0x04
  35 #define VC5_RSVD_ADC_OFFSET_15_8                0x05
  36 #define VC5_RSVD_TEMPY                          0x06
  37 #define VC5_RSVD_OFFSET_TBIN                    0x07
  38 #define VC5_RSVD_GAIN                           0x08
  39 #define VC5_RSVD_TEST_NP                        0x09
  40 #define VC5_RSVD_UNUSED                         0x0a
  41 #define VC5_RSVD_BANDGAP_TRIM_UP                0x0b
  42 #define VC5_RSVD_BANDGAP_TRIM_DN                0x0c
  43 #define VC5_RSVD_CLK_R_12_CLK_AMP_4             0x0d
  44 #define VC5_RSVD_CLK_R_34_CLK_AMP_4             0x0e
  45 #define VC5_RSVD_CLK_AMP_123                    0x0f
  46
  47 /* Configuration register block */
  48 #define VC5_PRIM_SRC_SHDN                       0x10
  49 #define VC5_PRIM_SRC_SHDN_EN_XTAL               BIT(7)
  50 #define VC5_PRIM_SRC_SHDN_EN_CLKIN              BIT(6)
  51 #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ   BIT(3)
  52 #define VC5_PRIM_SRC_SHDN_SP                    BIT(1)
  53 #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN           BIT(0)
  54
  55 #define VC5_VCO_BAND                            0x11
  56 #define VC5_XTAL_X1_LOAD_CAP                    0x12
  57 #define VC5_XTAL_X2_LOAD_CAP                    0x13
  58 #define VC5_REF_DIVIDER                         0x15
  59 #define VC5_REF_DIVIDER_SEL_PREDIV2             BIT(7)
  60 #define VC5_REF_DIVIDER_REF_DIV(n)              ((n) & 0x3f)
  61
  62 #define VC5_VCO_CTRL_AND_PREDIV                 0x16
  63 #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV   BIT(7)
  64
  65 #define VC5_FEEDBACK_INT_DIV                    0x17
  66 #define VC5_FEEDBACK_INT_DIV_BITS               0x18
  67 #define VC5_FEEDBACK_FRAC_DIV(n)                (0x19 + (n))
  68 #define VC5_RC_CONTROL0                         0x1e
  69 #define VC5_RC_CONTROL1                         0x1f
  70 /* Register 0x20 is factory reserved */
  71
  72 /* Output divider control for divider 1,2,3,4 */
  73 #define VC5_OUT_DIV_CONTROL(idx)        (0x21 + ((idx) * 0x10))
  74 #define VC5_OUT_DIV_CONTROL_RESET       BIT(7)
  75 #define VC5_OUT_DIV_CONTROL_SELB_NORM   BIT(3)
  76 #define VC5_OUT_DIV_CONTROL_SEL_EXT     BIT(2)
  77 #define VC5_OUT_DIV_CONTROL_INT_MODE    BIT(1)
  78 #define VC5_OUT_DIV_CONTROL_EN_FOD      BIT(0)
  79
  80 #define VC5_OUT_DIV_FRAC(idx, n)        (0x22 + ((idx) * 0x10) + (n))
  81 #define VC5_OUT_DIV_FRAC4_OD_SCEE       BIT(1)
  82
  83 #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
  84 #define VC5_OUT_DIV_SPREAD_MOD(idx, n)  (0x29 + ((idx) * 0x10) + (n))
  85 #define VC5_OUT_DIV_SKEW_INT(idx, n)    (0x2b + ((idx) * 0x10) + (n))
  86 #define VC5_OUT_DIV_INT(idx, n)         (0x2d + ((idx) * 0x10) + (n))
  87 #define VC5_OUT_DIV_SKEW_FRAC(idx)      (0x2f + ((idx) * 0x10))
  88 /* Registers 0x30, 0x40, 0x50 are factory reserved */
  89
  90 /* Clock control register for clock 1,2 */
  91 #define VC5_CLK_OUTPUT_CFG(idx, n)      (0x60 + ((idx) * 0x2) + (n))
  92 #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF   BIT(0)
  93
  94 #define VC5_CLK_OE_SHDN                         0x68
  95 #define VC5_CLK_OS_SHDN                         0x69
  96
  97 #define VC5_GLOBAL_REGISTER                     0x76
  98 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET        BIT(5)
  99
 100 /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
 101 #define VC5_PLL_VCO_MIN                         2500000000UL
 102 #define VC5_PLL_VCO_MAX                         3000000000UL
 103
 104 /* VC5 Input mux settings */
 105 #define VC5_MUX_IN_XIN          BIT(0)
 106 #define VC5_MUX_IN_CLKIN        BIT(1)
 107
 108 /* Maximum number of clk_out supported by this driver */
 109 #define VC5_MAX_CLK_OUT_NUM     5
 110
 111 /* Maximum number of FODs supported by this driver */
 112 #define VC5_MAX_FOD_NUM 4
 113
 114 /* flags to describe chip features */
 115 /* chip has built-in oscilator */
 116 #define VC5_HAS_INTERNAL_XTAL   BIT(0)
 117 /* chip has PFD requency doubler */
 118 #define VC5_HAS_PFD_FREQ_DBL    BIT(1)
 119
 120 /* Supported IDT VC5 models. */
 121 enum vc5_model {
 122         IDT_VC5_5P49V5923,
 123         IDT_VC5_5P49V5925,
 124         IDT_VC5_5P49V5933,
 125         IDT_VC5_5P49V5935,
 126         IDT_VC6_5P49V6901,
 127 };
 128
 129 /* Structure to describe features of a particular VC5 model */
 130 struct vc5_chip_info {
 131         const enum vc5_model    model;
 132         const unsigned int      clk_fod_cnt;
 133         const unsigned int      clk_out_cnt;
 134         const u32               flags;
 135 };
 136
 137 struct vc5_driver_data;
 138
 139 struct vc5_hw_data {
 140         struct clk_hw           hw;
 141         struct vc5_driver_data  *vc5;
 142         u32                     div_int;
 143         u32                     div_frc;
 144         unsigned int            num;
 145 };
 146
 147 struct vc5_driver_data {
 148         struct i2c_client       *client;
 149         struct regmap           *regmap;
 150         const struct vc5_chip_info      *chip_info;
 151
 152         struct clk              *pin_xin;
 153         struct clk              *pin_clkin;
 154         unsigned char           clk_mux_ins;
 155         struct clk_hw           clk_mux;
 156         struct clk_hw           clk_mul;
 157         struct clk_hw           clk_pfd;
 158         struct vc5_hw_data      clk_pll;
 159         struct vc5_hw_data      clk_fod[VC5_MAX_FOD_NUM];
 160         struct vc5_hw_data      clk_out[VC5_MAX_CLK_OUT_NUM];
 161 };
 162
 163 static const char * const vc5_mux_names[] = {
 164         "mux"
 165 };
 166
 167 static const char * const vc5_dbl_names[] = {
 168         "dbl"
 169 };
 170
 171 static const char * const vc5_pfd_names[] = {
 172         "pfd"
 173 };
 174
 175 static const char * const vc5_pll_names[] = {
 176         "pll"
 177 };
 178
 179 static const char * const vc5_fod_names[] = {
 180         "fod0", "fod1", "fod2", "fod3",
 181 };
 182
 183 static const char * const vc5_clk_out_names[] = {
 184         "out0_sel_i2cb", "out1", "out2", "out3", "out4",
 185 };
 186
 187 /*
 188  * VersaClock5 i2c regmap
 189  */
 190 static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg)
 191 {
 192         /* Factory reserved regs, make them read-only */
 193         if (reg <= 0xf)
 194                 return false;
 195
 196         /* Factory reserved regs, make them read-only */
 197         if (reg == 0x14 || reg == 0x1c || reg == 0x1d)
 198                 return false;
 199
 200         return true;
 201 }
 202
 203 static const struct regmap_config vc5_regmap_config = {
 204         .reg_bits = 8,
 205         .val_bits = 8,
 206         .cache_type = REGCACHE_RBTREE,
 207         .max_register = 0x76,
 208         .writeable_reg = vc5_regmap_is_writeable,
 209 };
 210
 211 /*
 212  * VersaClock5 input multiplexer between XTAL and CLKIN divider
 213  */
 214 static unsigned char vc5_mux_get_parent(struct clk_hw *hw)
 215 {
 216         struct vc5_driver_data *vc5 =
 217                 container_of(hw, struct vc5_driver_data, clk_mux);
 218         const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
 219         unsigned int src;
 220
 221         regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &src);
 222         src &= mask;
 223
 224         if (src == VC5_PRIM_SRC_SHDN_EN_XTAL)
 225                 return 0;
 226
 227         if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN)
 228                 return 1;
 229
 230         dev_warn(&vc5->client->dev,
 231                  "Invalid clock input configuration (%02x)\n", src);
 232         return 0;
 233 }
 234
 235 static int vc5_mux_set_parent(struct clk_hw *hw, u8 index)
 236 {
 237         struct vc5_driver_data *vc5 =
 238                 container_of(hw, struct vc5_driver_data, clk_mux);
 239         const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
 240         u8 src;
 241
 242         if ((index > 1) || !vc5->clk_mux_ins)
 243                 return -EINVAL;
 244
 245         if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
 246                 if (index == 0)
 247                         src = VC5_PRIM_SRC_SHDN_EN_XTAL;
 248                 if (index == 1)
 249                         src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
 250         } else {
 251                 if (index != 0)
 252                         return -EINVAL;
 253
 254                 if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
 255                         src = VC5_PRIM_SRC_SHDN_EN_XTAL;
 256                 else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
 257                         src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
 258                 else /* Invalid; should have been caught by vc5_probe() */
 259                         return -EINVAL;
 260         }
 261
 262         return regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, mask, src);
 263 }
 264
 265 static const struct clk_ops vc5_mux_ops = {
 266         .set_parent     = vc5_mux_set_parent,
 267         .get_parent     = vc5_mux_get_parent,
 268 };
 269
 270 static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
 271                                          unsigned long parent_rate)
 272 {
 273         struct vc5_driver_data *vc5 =
 274                 container_of(hw, struct vc5_driver_data, clk_mul);
 275         unsigned int premul;
 276
 277         regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul);
 278         if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ)
 279                 parent_rate *= 2;
 280
 281         return parent_rate;
 282 }
 283
 284 static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
 285                                unsigned long *parent_rate)
 286 {
 287         if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
 288                 return rate;
 289         else
 290                 return -EINVAL;
 291 }
 292
 293 static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
 294                             unsigned long parent_rate)
 295 {
 296         struct vc5_driver_data *vc5 =
 297                 container_of(hw, struct vc5_driver_data, clk_mul);
 298         u32 mask;
 299
 300         if ((parent_rate * 2) == rate)
 301                 mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ;
 302         else
 303                 mask = 0;
 304
 305         regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN,
 306                            VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ,
 307                            mask);
 308
 309         return 0;
 310 }
 311
 312 static const struct clk_ops vc5_dbl_ops = {
 313         .recalc_rate    = vc5_dbl_recalc_rate,
 314         .round_rate     = vc5_dbl_round_rate,
 315         .set_rate       = vc5_dbl_set_rate,
 316 };
 317
 318 static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
 319                                          unsigned long parent_rate)
 320 {
 321         struct vc5_driver_data *vc5 =
 322                 container_of(hw, struct vc5_driver_data, clk_pfd);
 323         unsigned int prediv, div;
 324
 325         regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv);
 326
 327         /* The bypass_prediv is set, PLL fed from Ref_in directly. */
 328         if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
 329                 return parent_rate;
 330
 331         regmap_read(vc5->regmap, VC5_REF_DIVIDER, &div);
 332
 333         /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
 334         if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
 335                 return parent_rate / 2;
 336         else
 337                 return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
 338 }
 339
 340 static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
 341                                unsigned long *parent_rate)
 342 {
 343         unsigned long idiv;
 344
 345         /* PLL cannot operate with input clock above 50 MHz. */
 346         if (rate > 50000000)
 347                 return -EINVAL;
 348
 349         /* CLKIN within range of PLL input, feed directly to PLL. */
 350         if (*parent_rate <= 50000000)
 351                 return *parent_rate;
 352
 353         idiv = DIV_ROUND_UP(*parent_rate, rate);
 354         if (idiv > 127)
 355                 return -EINVAL;
 356
 357         return *parent_rate / idiv;
 358 }
 359
 360 static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate,
 361                             unsigned long parent_rate)
 362 {
 363         struct vc5_driver_data *vc5 =
 364                 container_of(hw, struct vc5_driver_data, clk_pfd);
 365         unsigned long idiv;
 366         u8 div;
 367
 368         /* CLKIN within range of PLL input, feed directly to PLL. */
 369         if (parent_rate <= 50000000) {
 370                 regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
 371                                    VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
 372                                    VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
 373                 regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, 0x00);
 374                 return 0;
 375         }
 376
 377         idiv = DIV_ROUND_UP(parent_rate, rate);
 378
 379         /* We have dedicated div-2 predivider. */
 380         if (idiv == 2)
 381                 div = VC5_REF_DIVIDER_SEL_PREDIV2;
 382         else
 383                 div = VC5_REF_DIVIDER_REF_DIV(idiv);
 384
 385         regmap_update_bits(vc5->regmap, VC5_REF_DIVIDER, 0xff, div);
 386         regmap_update_bits(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV,
 387                            VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
 388
 389         return 0;
 390 }
 391
 392 static const struct clk_ops vc5_pfd_ops = {
 393         .recalc_rate    = vc5_pfd_recalc_rate,
 394         .round_rate     = vc5_pfd_round_rate,
 395         .set_rate       = vc5_pfd_set_rate,
 396 };
 397
 398 /*
 399  * VersaClock5 PLL/VCO
 400  */
 401 static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
 402                                          unsigned long parent_rate)
 403 {
 404         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 405         struct vc5_driver_data *vc5 = hwdata->vc5;
 406         u32 div_int, div_frc;
 407         u8 fb[5];
 408
 409         regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
 410
 411         div_int = (fb[0] << 4) | (fb[1] >> 4);
 412         div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
 413
 414         /* The PLL divider has 12 integer bits and 24 fractional bits */
 415         return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
 416 }
 417
 418 static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 419                                unsigned long *parent_rate)
 420 {
 421         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 422         u32 div_int;
 423         u64 div_frc;
 424
 425         if (rate < VC5_PLL_VCO_MIN)
 426                 rate = VC5_PLL_VCO_MIN;
 427         if (rate > VC5_PLL_VCO_MAX)
 428                 rate = VC5_PLL_VCO_MAX;
 429
 430         /* Determine integer part, which is 12 bit wide */
 431         div_int = rate / *parent_rate;
 432         if (div_int > 0xfff)
 433                 rate = *parent_rate * 0xfff;
 434
 435         /* Determine best fractional part, which is 24 bit wide */
 436         div_frc = rate % *parent_rate;
 437         div_frc *= BIT(24) - 1;
 438         do_div(div_frc, *parent_rate);
 439
 440         hwdata->div_int = div_int;
 441         hwdata->div_frc = (u32)div_frc;
 442
 443         return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24);
 444 }
 445
 446 static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 447                             unsigned long parent_rate)
 448 {
 449         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 450         struct vc5_driver_data *vc5 = hwdata->vc5;
 451         u8 fb[5];
 452
 453         fb[0] = hwdata->div_int >> 4;
 454         fb[1] = hwdata->div_int << 4;
 455         fb[2] = hwdata->div_frc >> 16;
 456         fb[3] = hwdata->div_frc >> 8;
 457         fb[4] = hwdata->div_frc;
 458
 459         return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);
 460 }
 461
 462 static const struct clk_ops vc5_pll_ops = {
 463         .recalc_rate    = vc5_pll_recalc_rate,
 464         .round_rate     = vc5_pll_round_rate,
 465         .set_rate       = vc5_pll_set_rate,
 466 };
 467
 468 static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
 469                                          unsigned long parent_rate)
 470 {
 471         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 472         struct vc5_driver_data *vc5 = hwdata->vc5;
 473         /* VCO frequency is divided by two before entering FOD */
 474         u32 f_in = parent_rate / 2;
 475         u32 div_int, div_frc;
 476         u8 od_int[2];
 477         u8 od_frc[4];
 478
 479         regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0),
 480                          od_int, 2);
 481         regmap_bulk_read(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
 482                          od_frc, 4);
 483
 484         div_int = (od_int[0] << 4) | (od_int[1] >> 4);
 485         div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
 486                   (od_frc[2] << 6) | (od_frc[3] >> 2);
 487
 488         /* Avoid division by zero if the output is not configured. */
 489         if (div_int == 0 && div_frc == 0)
 490                 return 0;
 491
 492         /* The PLL divider has 12 integer bits and 30 fractional bits */
 493         return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
 494 }
 495
 496 static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
 497                                unsigned long *parent_rate)
 498 {
 499         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 500         /* VCO frequency is divided by two before entering FOD */
 501         u32 f_in = *parent_rate / 2;
 502         u32 div_int;
 503         u64 div_frc;
 504
 505         /* Determine integer part, which is 12 bit wide */
 506         div_int = f_in / rate;
 507         /*
 508          * WARNING: The clock chip does not output signal if the integer part
 509          *          of the divider is 0xfff and fractional part is non-zero.
 510          *          Clamp the divider at 0xffe to keep the code simple.
 511          */
 512         if (div_int > 0xffe) {
 513                 div_int = 0xffe;
 514                 rate = f_in / div_int;
 515         }
 516
 517         /* Determine best fractional part, which is 30 bit wide */
 518         div_frc = f_in % rate;
 519         div_frc <<= 24;
 520         do_div(div_frc, rate);
 521
 522         hwdata->div_int = div_int;
 523         hwdata->div_frc = (u32)div_frc;
 524
 525         return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
 526 }
 527
 528 static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate,
 529                             unsigned long parent_rate)
 530 {
 531         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 532         struct vc5_driver_data *vc5 = hwdata->vc5;
 533         u8 data[14] = {
 534                 hwdata->div_frc >> 22, hwdata->div_frc >> 14,
 535                 hwdata->div_frc >> 6, hwdata->div_frc << 2,
 536                 0, 0, 0, 0, 0,
 537                 0, 0,
 538                 hwdata->div_int >> 4, hwdata->div_int << 4,
 539                 0
 540         };
 541
 542         regmap_bulk_write(vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0),
 543                           data, 14);
 544
 545         /*
 546          * Toggle magic bit in undocumented register for unknown reason.
 547          * This is what the IDT timing commander tool does and the chip
 548          * datasheet somewhat implies this is needed, but the register
 549          * and the bit is not documented.
 550          */
 551         regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
 552                            VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
 553         regmap_update_bits(vc5->regmap, VC5_GLOBAL_REGISTER,
 554                            VC5_GLOBAL_REGISTER_GLOBAL_RESET,
 555                            VC5_GLOBAL_REGISTER_GLOBAL_RESET);
 556         return 0;
 557 }
 558
 559 static const struct clk_ops vc5_fod_ops = {
 560         .recalc_rate    = vc5_fod_recalc_rate,
 561         .round_rate     = vc5_fod_round_rate,
 562         .set_rate       = vc5_fod_set_rate,
 563 };
 564
 565 static int vc5_clk_out_prepare(struct clk_hw *hw)
 566 {
 567         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 568         struct vc5_driver_data *vc5 = hwdata->vc5;
 569         const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 570                         VC5_OUT_DIV_CONTROL_SEL_EXT |
 571                         VC5_OUT_DIV_CONTROL_EN_FOD;
 572         unsigned int src;
 573         int ret;
 574
 575         /*
 576          * If the input mux is disabled, enable it first and
 577          * select source from matching FOD.
 578          */
 579         regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
 580         if ((src & mask) == 0) {
 581                 src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
 582                 ret = regmap_update_bits(vc5->regmap,
 583                                          VC5_OUT_DIV_CONTROL(hwdata->num),
 584                                          mask | VC5_OUT_DIV_CONTROL_RESET, src);
 585                 if (ret)
 586                         return ret;
 587         }
 588
 589         /* Enable the clock buffer */
 590         regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
 591                            VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
 592                            VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
 593         return 0;
 594 }
 595
 596 static void vc5_clk_out_unprepare(struct clk_hw *hw)
 597 {
 598         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 599         struct vc5_driver_data *vc5 = hwdata->vc5;
 600
 601         /* Disable the clock buffer */
 602         regmap_update_bits(vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
 603                            VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
 604 }
 605
 606 static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw)
 607 {
 608         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 609         struct vc5_driver_data *vc5 = hwdata->vc5;
 610         const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 611                         VC5_OUT_DIV_CONTROL_SEL_EXT |
 612                         VC5_OUT_DIV_CONTROL_EN_FOD;
 613         const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM |
 614                               VC5_OUT_DIV_CONTROL_EN_FOD;
 615         const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
 616                           VC5_OUT_DIV_CONTROL_SEL_EXT;
 617         unsigned int src;
 618
 619         regmap_read(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), &src);
 620         src &= mask;
 621
 622         if (src == 0)   /* Input mux set to DISABLED */
 623                 return 0;
 624
 625         if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD)
 626                 return 0;
 627
 628         if (src == extclk)
 629                 return 1;
 630
 631         dev_warn(&vc5->client->dev,
 632                  "Invalid clock output configuration (%02x)\n", src);
 633         return 0;
 634 }
 635
 636 static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index)
 637 {
 638         struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
 639         struct vc5_driver_data *vc5 = hwdata->vc5;
 640         const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
 641                         VC5_OUT_DIV_CONTROL_SELB_NORM |
 642                         VC5_OUT_DIV_CONTROL_SEL_EXT |
 643                         VC5_OUT_DIV_CONTROL_EN_FOD;
 644         const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
 645                           VC5_OUT_DIV_CONTROL_SEL_EXT;
 646         u8 src = VC5_OUT_DIV_CONTROL_RESET;
 647
 648         if (index == 0)
 649                 src |= VC5_OUT_DIV_CONTROL_EN_FOD;
 650         else
 651                 src |= extclk;
 652
 653         return regmap_update_bits(vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num),
 654                                   mask, src);
 655 }
 656
 657 static const struct clk_ops vc5_clk_out_ops = {
 658         .prepare        = vc5_clk_out_prepare,
 659         .unprepare      = vc5_clk_out_unprepare,
 660         .set_parent     = vc5_clk_out_set_parent,
 661         .get_parent     = vc5_clk_out_get_parent,
 662 };
 663
 664 static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
 665                                      void *data)
 666 {
 667         struct vc5_driver_data *vc5 = data;
 668         unsigned int idx = clkspec->args[0];
 669
 670         if (idx >= vc5->chip_info->clk_out_cnt)
 671                 return ERR_PTR(-EINVAL);
 672
 673         return &vc5->clk_out[idx].hw;
 674 }
 675
 676 static int vc5_map_index_to_output(const enum vc5_model model,
 677                                    const unsigned int n)
 678 {
 679         switch (model) {
 680         case IDT_VC5_5P49V5933:
 681                 return (n == 0) ? 0 : 3;
 682         case IDT_VC5_5P49V5923:
 683         case IDT_VC5_5P49V5925:
 684         case IDT_VC5_5P49V5935:
 685         case IDT_VC6_5P49V6901:
 686         default:
 687                 return n;
 688         }
 689 }
 690
 691 static const struct of_device_id clk_vc5_of_match[];
 692
 693 static int vc5_probe(struct i2c_client *client,
 694                      const struct i2c_device_id *id)
 695 {
 696         struct vc5_driver_data *vc5;
 697         struct clk_init_data init;
 698         const char *parent_names[2];
 699         unsigned int n, idx = 0;
 700         int ret;
 701
 702         vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
 703         if (vc5 == NULL)
 704                 return -ENOMEM;
 705
 706         i2c_set_clientdata(client, vc5);
 707         vc5->client = client;
 708         vc5->chip_info = of_device_get_match_data(&client->dev);
 709
 710         vc5->pin_xin = devm_clk_get(&client->dev, "xin");
 711         if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
 712                 return -EPROBE_DEFER;
 713
 714         vc5->pin_clkin = devm_clk_get(&client->dev, "clkin");
 715         if (PTR_ERR(vc5->pin_clkin) == -EPROBE_DEFER)
 716                 return -EPROBE_DEFER;
 717
 718         vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config);
 719         if (IS_ERR(vc5->regmap)) {
 720                 dev_err(&client->dev, "failed to allocate register map\n");
 721                 return PTR_ERR(vc5->regmap);
 722         }
 723
 724         /* Register clock input mux */
 725         memset(&init, 0, sizeof(init));
 726
 727         if (!IS_ERR(vc5->pin_xin)) {
 728                 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
 729                 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
 730         } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
 731                 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
 732                                                        "internal-xtal", NULL,
 733                                                        0, 25000000);
 734                 if (IS_ERR(vc5->pin_xin))
 735                         return PTR_ERR(vc5->pin_xin);
 736                 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
 737                 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
 738         }
 739
 740         if (!IS_ERR(vc5->pin_clkin)) {
 741                 vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN;
 742                 parent_names[init.num_parents++] =
 743                         __clk_get_name(vc5->pin_clkin);
 744         }
 745
 746         if (!init.num_parents) {
 747                 dev_err(&client->dev, "no input clock specified!\n");
 748                 return -EINVAL;
 749         }
 750
 751         init.name = vc5_mux_names[0];
 752         init.ops = &vc5_mux_ops;
 753         init.flags = 0;
 754         init.parent_names = parent_names;
 755         vc5->clk_mux.init = &init;
 756         ret = devm_clk_hw_register(&client->dev, &vc5->clk_mux);
 757         if (ret) {
 758                 dev_err(&client->dev, "unable to register %s\n", init.name);
 759                 goto err_clk;
 760         }
 761
 762         if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) {
 763                 /* Register frequency doubler */
 764                 memset(&init, 0, sizeof(init));
 765                 init.name = vc5_dbl_names[0];
 766                 init.ops = &vc5_dbl_ops;
 767                 init.flags = CLK_SET_RATE_PARENT;
 768                 init.parent_names = vc5_mux_names;
 769                 init.num_parents = 1;
 770                 vc5->clk_mul.init = &init;
 771                 ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul);
 772                 if (ret) {
 773                         dev_err(&client->dev, "unable to register %s\n",
 774                                 init.name);
 775                         goto err_clk;
 776                 }
 777         }
 778
 779         /* Register PFD */
 780         memset(&init, 0, sizeof(init));
 781         init.name = vc5_pfd_names[0];
 782         init.ops = &vc5_pfd_ops;
 783         init.flags = CLK_SET_RATE_PARENT;
 784         if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL)
 785                 init.parent_names = vc5_dbl_names;
 786         else
 787                 init.parent_names = vc5_mux_names;
 788         init.num_parents = 1;
 789         vc5->clk_pfd.init = &init;
 790         ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);
 791         if (ret) {
 792                 dev_err(&client->dev, "unable to register %s\n", init.name);
 793                 goto err_clk;
 794         }
 795
 796         /* Register PLL */
 797         memset(&init, 0, sizeof(init));
 798         init.name = vc5_pll_names[0];
 799         init.ops = &vc5_pll_ops;
 800         init.flags = CLK_SET_RATE_PARENT;
 801         init.parent_names = vc5_pfd_names;
 802         init.num_parents = 1;
 803         vc5->clk_pll.num = 0;
 804         vc5->clk_pll.vc5 = vc5;
 805         vc5->clk_pll.hw.init = &init;
 806         ret = devm_clk_hw_register(&client->dev, &vc5->clk_pll.hw);
 807         if (ret) {
 808                 dev_err(&client->dev, "unable to register %s\n", init.name);
 809                 goto err_clk;
 810         }
 811
 812         /* Register FODs */
 813         for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
 814                 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
 815                 memset(&init, 0, sizeof(init));
 816                 init.name = vc5_fod_names[idx];
 817                 init.ops = &vc5_fod_ops;
 818                 init.flags = CLK_SET_RATE_PARENT;
 819                 init.parent_names = vc5_pll_names;
 820                 init.num_parents = 1;
 821                 vc5->clk_fod[n].num = idx;
 822                 vc5->clk_fod[n].vc5 = vc5;
 823                 vc5->clk_fod[n].hw.init = &init;
 824                 ret = devm_clk_hw_register(&client->dev, &vc5->clk_fod[n].hw);
 825                 if (ret) {
 826                         dev_err(&client->dev, "unable to register %s\n",
 827                                 init.name);
 828                         goto err_clk;
 829                 }
 830         }
 831
 832         /* Register MUX-connected OUT0_I2C_SELB output */
 833         memset(&init, 0, sizeof(init));
 834         init.name = vc5_clk_out_names[0];
 835         init.ops = &vc5_clk_out_ops;
 836         init.flags = CLK_SET_RATE_PARENT;
 837         init.parent_names = vc5_mux_names;
 838         init.num_parents = 1;
 839         vc5->clk_out[0].num = idx;
 840         vc5->clk_out[0].vc5 = vc5;
 841         vc5->clk_out[0].hw.init = &init;
 842         ret = devm_clk_hw_register(&client->dev, &vc5->clk_out[0].hw);
 843         if (ret) {
 844                 dev_err(&client->dev, "unable to register %s\n",
 845                         init.name);
 846                 goto err_clk;
 847         }
 848
 849         /* Register FOD-connected OUTx outputs */
 850         for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
 851                 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
 852                 parent_names[0] = vc5_fod_names[idx];
 853                 if (n == 1)
 854                         parent_names[1] = vc5_mux_names[0];
 855                 else
 856                         parent_names[1] = vc5_clk_out_names[n - 1];
 857
 858                 memset(&init, 0, sizeof(init));
 859                 init.name = vc5_clk_out_names[idx + 1];
 860                 init.ops = &vc5_clk_out_ops;
 861                 init.flags = CLK_SET_RATE_PARENT;
 862                 init.parent_names = parent_names;
 863                 init.num_parents = 2;
 864                 vc5->clk_out[n].num = idx;
 865                 vc5->clk_out[n].vc5 = vc5;
 866                 vc5->clk_out[n].hw.init = &init;
 867                 ret = devm_clk_hw_register(&client->dev,
 868                                            &vc5->clk_out[n].hw);
 869                 if (ret) {
 870                         dev_err(&client->dev, "unable to register %s\n",
 871                                 init.name);
 872                         goto err_clk;
 873                 }
 874         }
 875
 876         ret = of_clk_add_hw_provider(client->dev.of_node, vc5_of_clk_get, vc5);
 877         if (ret) {
 878                 dev_err(&client->dev, "unable to add clk provider\n");
 879                 goto err_clk;
 880         }
 881
 882         return 0;
 883
 884 err_clk:
 885         if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
 886                 clk_unregister_fixed_rate(vc5->pin_xin);
 887         return ret;
 888 }
 889
 890 static int vc5_remove(struct i2c_client *client)
 891 {
 892         struct vc5_driver_data *vc5 = i2c_get_clientdata(client);
 893
 894         of_clk_del_provider(client->dev.of_node);
 895
 896         if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
 897                 clk_unregister_fixed_rate(vc5->pin_xin);
 898
 899         return 0;
 900 }
 901
 902 static int __maybe_unused vc5_suspend(struct device *dev)
 903 {
 904         struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
 905
 906         regcache_cache_only(vc5->regmap, true);
 907         regcache_mark_dirty(vc5->regmap);
 908
 909         return 0;
 910 }
 911
 912 static int __maybe_unused vc5_resume(struct device *dev)
 913 {
 914         struct vc5_driver_data *vc5 = dev_get_drvdata(dev);
 915         int ret;
 916
 917         regcache_cache_only(vc5->regmap, false);
 918         ret = regcache_sync(vc5->regmap);
 919         if (ret)
 920                 dev_err(dev, "Failed to restore register map: %d\n", ret);
 921         return ret;
 922 }
 923
 924 static const struct vc5_chip_info idt_5p49v5923_info = {
 925         .model = IDT_VC5_5P49V5923,
 926         .clk_fod_cnt = 2,
 927         .clk_out_cnt = 3,
 928         .flags = 0,
 929 };
 930
 931 static const struct vc5_chip_info idt_5p49v5925_info = {
 932         .model = IDT_VC5_5P49V5925,
 933         .clk_fod_cnt = 4,
 934         .clk_out_cnt = 5,
 935         .flags = 0,
 936 };
 937
 938 static const struct vc5_chip_info idt_5p49v5933_info = {
 939         .model = IDT_VC5_5P49V5933,
 940         .clk_fod_cnt = 2,
 941         .clk_out_cnt = 3,
 942         .flags = VC5_HAS_INTERNAL_XTAL,
 943 };
 944
 945 static const struct vc5_chip_info idt_5p49v5935_info = {
 946         .model = IDT_VC5_5P49V5935,
 947         .clk_fod_cnt = 4,
 948         .clk_out_cnt = 5,
 949         .flags = VC5_HAS_INTERNAL_XTAL,
 950 };
 951
 952 static const struct vc5_chip_info idt_5p49v6901_info = {
 953         .model = IDT_VC6_5P49V6901,
 954         .clk_fod_cnt = 4,
 955         .clk_out_cnt = 5,
 956         .flags = VC5_HAS_PFD_FREQ_DBL,
 957 };
 958
 959 static const struct i2c_device_id vc5_id[] = {
 960         { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
 961         { "5p49v5925", .driver_data = IDT_VC5_5P49V5925 },
 962         { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
 963         { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
 964         { "5p49v6901", .driver_data = IDT_VC6_5P49V6901 },
 965         { }
 966 };
 967 MODULE_DEVICE_TABLE(i2c, vc5_id);
 968
 969 static const struct of_device_id clk_vc5_of_match[] = {
 970         { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
 971         { .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
 972         { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
 973         { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
 974         { .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
 975         { },
 976 };
 977 MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
 978
 979 static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume);
 980
 981 static struct i2c_driver vc5_driver = {
 982         .driver = {
 983                 .name = "vc5",
 984                 .pm     = &vc5_pm_ops,
 985                 .of_match_table = clk_vc5_of_match,
 986         },
 987         .probe          = vc5_probe,
 988         .remove         = vc5_remove,
 989         .id_table       = vc5_id,
 990 };
 991 module_i2c_driver(vc5_driver);
 992
 993 MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
 994 MODULE_DESCRIPTION("IDT VersaClock 5 driver");
 995 MODULE_LICENSE("GPL");