?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
split dev_queue
[cor.git] / sound / mips / hal2.c
blobc9e0609397083b3681bd413b412495d3c926a6dd
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for A2 audio system used in SGI machines
4 * Copyright (c) 2008 Thomas Bogendoerfer <tsbogend@alpha.fanken.de>
5 *
6 * Based on OSS code from Ladislav Michl <ladis@linux-mips.org>, which
7 * was based on code from Ulf Carlsson
8 */
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/platform_device.h>
14 #include <linux/io.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17
18 #include <asm/sgi/hpc3.h>
19 #include <asm/sgi/ip22.h>
20
21 #include <sound/core.h>
22 #include <sound/control.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm-indirect.h>
25 #include <sound/initval.h>
26
27 #include "hal2.h"
28
29 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
30 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
31
32 module_param(index, int, 0444);
33 MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard.");
34 module_param(id, charp, 0444);
35 MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard.");
36 MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio");
37 MODULE_AUTHOR("Thomas Bogendoerfer");
38 MODULE_LICENSE("GPL");
39
40
41 #define H2_BLOCK_SIZE 1024
42 #define H2_BUF_SIZE 16384
43
44 struct hal2_pbus {
45 struct hpc3_pbus_dmacregs *pbus;
46 int pbusnr;
47 unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */
48 };
49
50 struct hal2_desc {
51 struct hpc_dma_desc desc;
52 u32 pad; /* padding */
53 };
54
55 struct hal2_codec {
56 struct snd_pcm_indirect pcm_indirect;
57 struct snd_pcm_substream *substream;
58
59 unsigned char *buffer;
60 dma_addr_t buffer_dma;
61 struct hal2_desc *desc;
62 dma_addr_t desc_dma;
63 int desc_count;
64 struct hal2_pbus pbus;
65 int voices; /* mono/stereo */
66 unsigned int sample_rate;
67 unsigned int master; /* Master frequency */
68 unsigned short mod; /* MOD value */
69 unsigned short inc; /* INC value */
70 };
71
72 #define H2_MIX_OUTPUT_ATT 0
73 #define H2_MIX_INPUT_GAIN 1
74
75 struct snd_hal2 {
76 struct snd_card *card;
77
78 struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
79 struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
80 struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
81 struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
82
83 struct hal2_codec dac;
84 struct hal2_codec adc;
85 };
86
87 #define H2_INDIRECT_WAIT(regs) while (hal2_read(&regs->isr) & H2_ISR_TSTATUS);
88
89 #define H2_READ_ADDR(addr) (addr | (1<<7))
90 #define H2_WRITE_ADDR(addr) (addr)
91
92 static inline u32 hal2_read(u32 *reg)
93 {
94 return __raw_readl(reg);
95 }
96
97 static inline void hal2_write(u32 val, u32 *reg)
98 {
99 __raw_writel(val, reg);
100 }
101
102
103 static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr)
104 {
105 u32 ret;
106 struct hal2_ctl_regs *regs = hal2->ctl_regs;
107
108 hal2_write(H2_READ_ADDR(addr), &regs->iar);
109 H2_INDIRECT_WAIT(regs);
110 ret = hal2_read(&regs->idr0) & 0xffff;
111 hal2_write(H2_READ_ADDR(addr) | 0x1, &regs->iar);
112 H2_INDIRECT_WAIT(regs);
113 ret |= (hal2_read(&regs->idr0) & 0xffff) << 16;
114 return ret;
115 }
116
117 static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val)
118 {
119 struct hal2_ctl_regs *regs = hal2->ctl_regs;
120
121 hal2_write(val, &regs->idr0);
122 hal2_write(0, &regs->idr1);
123 hal2_write(0, &regs->idr2);
124 hal2_write(0, &regs->idr3);
125 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
126 H2_INDIRECT_WAIT(regs);
127 }
128
129 static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val)
130 {
131 struct hal2_ctl_regs *regs = hal2->ctl_regs;
132
133 hal2_write(val & 0xffff, &regs->idr0);
134 hal2_write(val >> 16, &regs->idr1);
135 hal2_write(0, &regs->idr2);
136 hal2_write(0, &regs->idr3);
137 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
138 H2_INDIRECT_WAIT(regs);
139 }
140
141 static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
142 {
143 struct hal2_ctl_regs *regs = hal2->ctl_regs;
144
145 hal2_write(H2_READ_ADDR(addr), &regs->iar);
146 H2_INDIRECT_WAIT(regs);
147 hal2_write((hal2_read(&regs->idr0) & 0xffff) | bit, &regs->idr0);
148 hal2_write(0, &regs->idr1);
149 hal2_write(0, &regs->idr2);
150 hal2_write(0, &regs->idr3);
151 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
152 H2_INDIRECT_WAIT(regs);
153 }
154
155 static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit)
156 {
157 struct hal2_ctl_regs *regs = hal2->ctl_regs;
158
159 hal2_write(H2_READ_ADDR(addr), &regs->iar);
160 H2_INDIRECT_WAIT(regs);
161 hal2_write((hal2_read(&regs->idr0) & 0xffff) & ~bit, &regs->idr0);
162 hal2_write(0, &regs->idr1);
163 hal2_write(0, &regs->idr2);
164 hal2_write(0, &regs->idr3);
165 hal2_write(H2_WRITE_ADDR(addr), &regs->iar);
166 H2_INDIRECT_WAIT(regs);
167 }
168
169 static int hal2_gain_info(struct snd_kcontrol *kcontrol,
170 struct snd_ctl_elem_info *uinfo)
171 {
172 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
173 uinfo->count = 2;
174 uinfo->value.integer.min = 0;
175 switch ((int)kcontrol->private_value) {
176 case H2_MIX_OUTPUT_ATT:
177 uinfo->value.integer.max = 31;
178 break;
179 case H2_MIX_INPUT_GAIN:
180 uinfo->value.integer.max = 15;
181 break;
182 }
183 return 0;
184 }
185
186 static int hal2_gain_get(struct snd_kcontrol *kcontrol,
187 struct snd_ctl_elem_value *ucontrol)
188 {
189 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
190 u32 tmp;
191 int l, r;
192
193 switch ((int)kcontrol->private_value) {
194 case H2_MIX_OUTPUT_ATT:
195 tmp = hal2_i_read32(hal2, H2I_DAC_C2);
196 if (tmp & H2I_C2_MUTE) {
197 l = 0;
198 r = 0;
199 } else {
200 l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31);
201 r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31);
202 }
203 break;
204 case H2_MIX_INPUT_GAIN:
205 tmp = hal2_i_read32(hal2, H2I_ADC_C2);
206 l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15;
207 r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15;
208 break;
209 default:
210 return -EINVAL;
211 }
212 ucontrol->value.integer.value[0] = l;
213 ucontrol->value.integer.value[1] = r;
214
215 return 0;
216 }
217
218 static int hal2_gain_put(struct snd_kcontrol *kcontrol,
219 struct snd_ctl_elem_value *ucontrol)
220 {
221 struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol);
222 u32 old, new;
223 int l, r;
224
225 l = ucontrol->value.integer.value[0];
226 r = ucontrol->value.integer.value[1];
227
228 switch ((int)kcontrol->private_value) {
229 case H2_MIX_OUTPUT_ATT:
230 old = hal2_i_read32(hal2, H2I_DAC_C2);
231 new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
232 if (l | r) {
233 l = 31 - l;
234 r = 31 - r;
235 new |= (l << H2I_C2_L_ATT_SHIFT);
236 new |= (r << H2I_C2_R_ATT_SHIFT);
237 } else
238 new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE;
239 hal2_i_write32(hal2, H2I_DAC_C2, new);
240 break;
241 case H2_MIX_INPUT_GAIN:
242 old = hal2_i_read32(hal2, H2I_ADC_C2);
243 new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
244 new |= (l << H2I_C2_L_GAIN_SHIFT);
245 new |= (r << H2I_C2_R_GAIN_SHIFT);
246 hal2_i_write32(hal2, H2I_ADC_C2, new);
247 break;
248 default:
249 return -EINVAL;
250 }
251 return old != new;
252 }
253
254 static const struct snd_kcontrol_new hal2_ctrl_headphone = {
255 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
256 .name = "Headphone Playback Volume",
257 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
258 .private_value = H2_MIX_OUTPUT_ATT,
259 .info = hal2_gain_info,
260 .get = hal2_gain_get,
261 .put = hal2_gain_put,
262 };
263
264 static const struct snd_kcontrol_new hal2_ctrl_mic = {
265 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
266 .name = "Mic Capture Volume",
267 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
268 .private_value = H2_MIX_INPUT_GAIN,
269 .info = hal2_gain_info,
270 .get = hal2_gain_get,
271 .put = hal2_gain_put,
272 };
273
274 static int hal2_mixer_create(struct snd_hal2 *hal2)
275 {
276 int err;
277
278 /* mute DAC */
279 hal2_i_write32(hal2, H2I_DAC_C2,
280 H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
281 /* mute ADC */
282 hal2_i_write32(hal2, H2I_ADC_C2, 0);
283
284 err = snd_ctl_add(hal2->card,
285 snd_ctl_new1(&hal2_ctrl_headphone, hal2));
286 if (err < 0)
287 return err;
288
289 err = snd_ctl_add(hal2->card,
290 snd_ctl_new1(&hal2_ctrl_mic, hal2));
291 if (err < 0)
292 return err;
293
294 return 0;
295 }
296
297 static irqreturn_t hal2_interrupt(int irq, void *dev_id)
298 {
299 struct snd_hal2 *hal2 = dev_id;
300 irqreturn_t ret = IRQ_NONE;
301
302 /* decide what caused this interrupt */
303 if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
304 snd_pcm_period_elapsed(hal2->dac.substream);
305 ret = IRQ_HANDLED;
306 }
307 if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
308 snd_pcm_period_elapsed(hal2->adc.substream);
309 ret = IRQ_HANDLED;
310 }
311 return ret;
312 }
313
314 static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
315 {
316 unsigned short mod;
317
318 if (44100 % rate < 48000 % rate) {
319 mod = 4 * 44100 / rate;
320 codec->master = 44100;
321 } else {
322 mod = 4 * 48000 / rate;
323 codec->master = 48000;
324 }
325
326 codec->inc = 4;
327 codec->mod = mod;
328 rate = 4 * codec->master / mod;
329
330 return rate;
331 }
332
333 static void hal2_set_dac_rate(struct snd_hal2 *hal2)
334 {
335 unsigned int master = hal2->dac.master;
336 int inc = hal2->dac.inc;
337 int mod = hal2->dac.mod;
338
339 hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
340 hal2_i_write32(hal2, H2I_BRES1_C2,
341 ((0xffff & (inc - mod - 1)) << 16) | inc);
342 }
343
344 static void hal2_set_adc_rate(struct snd_hal2 *hal2)
345 {
346 unsigned int master = hal2->adc.master;
347 int inc = hal2->adc.inc;
348 int mod = hal2->adc.mod;
349
350 hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
351 hal2_i_write32(hal2, H2I_BRES2_C2,
352 ((0xffff & (inc - mod - 1)) << 16) | inc);
353 }
354
355 static void hal2_setup_dac(struct snd_hal2 *hal2)
356 {
357 unsigned int fifobeg, fifoend, highwater, sample_size;
358 struct hal2_pbus *pbus = &hal2->dac.pbus;
359
360 /* Now we set up some PBUS information. The PBUS needs information about
361 * what portion of the fifo it will use. If it's receiving or
362 * transmitting, and finally whether the stream is little endian or big
363 * endian. The information is written later, on the start call.
364 */
365 sample_size = 2 * hal2->dac.voices;
366 /* Fifo should be set to hold exactly four samples. Highwater mark
367 * should be set to two samples. */
368 highwater = (sample_size * 2) >> 1; /* halfwords */
369 fifobeg = 0; /* playback is first */
370 fifoend = (sample_size * 4) >> 3; /* doublewords */
371 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
372 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
373 /* We disable everything before we do anything at all */
374 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
375 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
376 /* Setup the HAL2 for playback */
377 hal2_set_dac_rate(hal2);
378 /* Set endianess */
379 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
380 /* Set DMA bus */
381 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
382 /* We are using 1st Bresenham clock generator for playback */
383 hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
384 | (1 << H2I_C1_CLKID_SHIFT)
385 | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
386 }
387
388 static void hal2_setup_adc(struct snd_hal2 *hal2)
389 {
390 unsigned int fifobeg, fifoend, highwater, sample_size;
391 struct hal2_pbus *pbus = &hal2->adc.pbus;
392
393 sample_size = 2 * hal2->adc.voices;
394 highwater = (sample_size * 2) >> 1; /* halfwords */
395 fifobeg = (4 * 4) >> 3; /* record is second */
396 fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
397 pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
398 (highwater << 8) | (fifobeg << 16) | (fifoend << 24);
399 pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
400 hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
401 /* Setup the HAL2 for record */
402 hal2_set_adc_rate(hal2);
403 /* Set endianess */
404 hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
405 /* Set DMA bus */
406 hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
407 /* We are using 2nd Bresenham clock generator for record */
408 hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
409 | (2 << H2I_C1_CLKID_SHIFT)
410 | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
411 }
412
413 static void hal2_start_dac(struct snd_hal2 *hal2)
414 {
415 struct hal2_pbus *pbus = &hal2->dac.pbus;
416
417 pbus->pbus->pbdma_dptr = hal2->dac.desc_dma;
418 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
419 /* enable DAC */
420 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
421 }
422
423 static void hal2_start_adc(struct snd_hal2 *hal2)
424 {
425 struct hal2_pbus *pbus = &hal2->adc.pbus;
426
427 pbus->pbus->pbdma_dptr = hal2->adc.desc_dma;
428 pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
429 /* enable ADC */
430 hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
431 }
432
433 static inline void hal2_stop_dac(struct snd_hal2 *hal2)
434 {
435 hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
436 /* The HAL2 itself may remain enabled safely */
437 }
438
439 static inline void hal2_stop_adc(struct snd_hal2 *hal2)
440 {
441 hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
442 }
443
444 static int hal2_alloc_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec)
445 {
446 struct device *dev = hal2->card->dev;
447 struct hal2_desc *desc;
448 dma_addr_t desc_dma, buffer_dma;
449 int count = H2_BUF_SIZE / H2_BLOCK_SIZE;
450 int i;
451
452 codec->buffer = dma_alloc_attrs(dev, H2_BUF_SIZE, &buffer_dma,
453 GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
454 if (!codec->buffer)
455 return -ENOMEM;
456 desc = dma_alloc_attrs(dev, count * sizeof(struct hal2_desc),
457 &desc_dma, GFP_KERNEL, DMA_ATTR_NON_CONSISTENT);
458 if (!desc) {
459 dma_free_attrs(dev, H2_BUF_SIZE, codec->buffer, buffer_dma,
460 DMA_ATTR_NON_CONSISTENT);
461 return -ENOMEM;
462 }
463 codec->buffer_dma = buffer_dma;
464 codec->desc_dma = desc_dma;
465 codec->desc = desc;
466 for (i = 0; i < count; i++) {
467 desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE;
468 desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
469 desc->desc.pnext = (i == count - 1) ?
470 desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc);
471 desc++;
472 }
473 dma_cache_sync(dev, codec->desc, count * sizeof(struct hal2_desc),
474 DMA_TO_DEVICE);
475 codec->desc_count = count;
476 return 0;
477 }
478
479 static void hal2_free_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec)
480 {
481 struct device *dev = hal2->card->dev;
482
483 dma_free_attrs(dev, codec->desc_count * sizeof(struct hal2_desc),
484 codec->desc, codec->desc_dma, DMA_ATTR_NON_CONSISTENT);
485 dma_free_attrs(dev, H2_BUF_SIZE, codec->buffer, codec->buffer_dma,
486 DMA_ATTR_NON_CONSISTENT);
487 }
488
489 static const struct snd_pcm_hardware hal2_pcm_hw = {
490 .info = (SNDRV_PCM_INFO_MMAP |
491 SNDRV_PCM_INFO_MMAP_VALID |
492 SNDRV_PCM_INFO_INTERLEAVED |
493 SNDRV_PCM_INFO_BLOCK_TRANSFER |
494 SNDRV_PCM_INFO_SYNC_APPLPTR),
495 .formats = SNDRV_PCM_FMTBIT_S16_BE,
496 .rates = SNDRV_PCM_RATE_8000_48000,
497 .rate_min = 8000,
498 .rate_max = 48000,
499 .channels_min = 2,
500 .channels_max = 2,
501 .buffer_bytes_max = 65536,
502 .period_bytes_min = 1024,
503 .period_bytes_max = 65536,
504 .periods_min = 2,
505 .periods_max = 1024,
506 };
507
508 static int hal2_pcm_hw_params(struct snd_pcm_substream *substream,
509 struct snd_pcm_hw_params *params)
510 {
511 int err;
512
513 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
514 if (err < 0)
515 return err;
516
517 return 0;
518 }
519
520 static int hal2_pcm_hw_free(struct snd_pcm_substream *substream)
521 {
522 return snd_pcm_lib_free_pages(substream);
523 }
524
525 static int hal2_playback_open(struct snd_pcm_substream *substream)
526 {
527 struct snd_pcm_runtime *runtime = substream->runtime;
528 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
529 int err;
530
531 runtime->hw = hal2_pcm_hw;
532
533 err = hal2_alloc_dmabuf(hal2, &hal2->dac);
534 if (err)
535 return err;
536 return 0;
537 }
538
539 static int hal2_playback_close(struct snd_pcm_substream *substream)
540 {
541 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
542
543 hal2_free_dmabuf(hal2, &hal2->dac);
544 return 0;
545 }
546
547 static int hal2_playback_prepare(struct snd_pcm_substream *substream)
548 {
549 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
550 struct snd_pcm_runtime *runtime = substream->runtime;
551 struct hal2_codec *dac = &hal2->dac;
552
553 dac->voices = runtime->channels;
554 dac->sample_rate = hal2_compute_rate(dac, runtime->rate);
555 memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect));
556 dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
557 dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
558 dac->pcm_indirect.hw_io = dac->buffer_dma;
559 dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
560 dac->substream = substream;
561 hal2_setup_dac(hal2);
562 return 0;
563 }
564
565 static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd)
566 {
567 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
568
569 switch (cmd) {
570 case SNDRV_PCM_TRIGGER_START:
571 hal2_start_dac(hal2);
572 break;
573 case SNDRV_PCM_TRIGGER_STOP:
574 hal2_stop_dac(hal2);
575 break;
576 default:
577 return -EINVAL;
578 }
579 return 0;
580 }
581
582 static snd_pcm_uframes_t
583 hal2_playback_pointer(struct snd_pcm_substream *substream)
584 {
585 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
586 struct hal2_codec *dac = &hal2->dac;
587
588 return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect,
589 dac->pbus.pbus->pbdma_bptr);
590 }
591
592 static void hal2_playback_transfer(struct snd_pcm_substream *substream,
593 struct snd_pcm_indirect *rec, size_t bytes)
594 {
595 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
596 unsigned char *buf = hal2->dac.buffer + rec->hw_data;
597
598 memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes);
599 dma_cache_sync(hal2->card->dev, buf, bytes, DMA_TO_DEVICE);
600
601 }
602
603 static int hal2_playback_ack(struct snd_pcm_substream *substream)
604 {
605 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
606 struct hal2_codec *dac = &hal2->dac;
607
608 return snd_pcm_indirect_playback_transfer(substream,
609 &dac->pcm_indirect,
610 hal2_playback_transfer);
611 }
612
613 static int hal2_capture_open(struct snd_pcm_substream *substream)
614 {
615 struct snd_pcm_runtime *runtime = substream->runtime;
616 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
617 struct hal2_codec *adc = &hal2->adc;
618 int err;
619
620 runtime->hw = hal2_pcm_hw;
621
622 err = hal2_alloc_dmabuf(hal2, adc);
623 if (err)
624 return err;
625 return 0;
626 }
627
628 static int hal2_capture_close(struct snd_pcm_substream *substream)
629 {
630 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
631
632 hal2_free_dmabuf(hal2, &hal2->adc);
633 return 0;
634 }
635
636 static int hal2_capture_prepare(struct snd_pcm_substream *substream)
637 {
638 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
639 struct snd_pcm_runtime *runtime = substream->runtime;
640 struct hal2_codec *adc = &hal2->adc;
641
642 adc->voices = runtime->channels;
643 adc->sample_rate = hal2_compute_rate(adc, runtime->rate);
644 memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect));
645 adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE;
646 adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2;
647 adc->pcm_indirect.hw_io = adc->buffer_dma;
648 adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
649 adc->substream = substream;
650 hal2_setup_adc(hal2);
651 return 0;
652 }
653
654 static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd)
655 {
656 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
657
658 switch (cmd) {
659 case SNDRV_PCM_TRIGGER_START:
660 hal2_start_adc(hal2);
661 break;
662 case SNDRV_PCM_TRIGGER_STOP:
663 hal2_stop_adc(hal2);
664 break;
665 default:
666 return -EINVAL;
667 }
668 return 0;
669 }
670
671 static snd_pcm_uframes_t
672 hal2_capture_pointer(struct snd_pcm_substream *substream)
673 {
674 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
675 struct hal2_codec *adc = &hal2->adc;
676
677 return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect,
678 adc->pbus.pbus->pbdma_bptr);
679 }
680
681 static void hal2_capture_transfer(struct snd_pcm_substream *substream,
682 struct snd_pcm_indirect *rec, size_t bytes)
683 {
684 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
685 unsigned char *buf = hal2->adc.buffer + rec->hw_data;
686
687 dma_cache_sync(hal2->card->dev, buf, bytes, DMA_FROM_DEVICE);
688 memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes);
689 }
690
691 static int hal2_capture_ack(struct snd_pcm_substream *substream)
692 {
693 struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream);
694 struct hal2_codec *adc = &hal2->adc;
695
696 return snd_pcm_indirect_capture_transfer(substream,
697 &adc->pcm_indirect,
698 hal2_capture_transfer);
699 }
700
701 static const struct snd_pcm_ops hal2_playback_ops = {
702 .open = hal2_playback_open,
703 .close = hal2_playback_close,
704 .ioctl = snd_pcm_lib_ioctl,
705 .hw_params = hal2_pcm_hw_params,
706 .hw_free = hal2_pcm_hw_free,
707 .prepare = hal2_playback_prepare,
708 .trigger = hal2_playback_trigger,
709 .pointer = hal2_playback_pointer,
710 .ack = hal2_playback_ack,
711 };
712
713 static const struct snd_pcm_ops hal2_capture_ops = {
714 .open = hal2_capture_open,
715 .close = hal2_capture_close,
716 .ioctl = snd_pcm_lib_ioctl,
717 .hw_params = hal2_pcm_hw_params,
718 .hw_free = hal2_pcm_hw_free,
719 .prepare = hal2_capture_prepare,
720 .trigger = hal2_capture_trigger,
721 .pointer = hal2_capture_pointer,
722 .ack = hal2_capture_ack,
723 };
724
725 static int hal2_pcm_create(struct snd_hal2 *hal2)
726 {
727 struct snd_pcm *pcm;
728 int err;
729
730 /* create first pcm device with one outputs and one input */
731 err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm);
732 if (err < 0)
733 return err;
734
735 pcm->private_data = hal2;
736 strcpy(pcm->name, "SGI HAL2");
737
738 /* set operators */
739 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
740 &hal2_playback_ops);
741 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
742 &hal2_capture_ops);
743 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
744 NULL, 0, 1024 * 1024);
745
746 return 0;
747 }
748
749 static int hal2_dev_free(struct snd_device *device)
750 {
751 struct snd_hal2 *hal2 = device->device_data;
752
753 free_irq(SGI_HPCDMA_IRQ, hal2);
754 kfree(hal2);
755 return 0;
756 }
757
758 static struct snd_device_ops hal2_ops = {
759 .dev_free = hal2_dev_free,
760 };
761
762 static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
763 int index)
764 {
765 codec->pbus.pbusnr = index;
766 codec->pbus.pbus = &hpc3->pbdma[index];
767 }
768
769 static int hal2_detect(struct snd_hal2 *hal2)
770 {
771 unsigned short board, major, minor;
772 unsigned short rev;
773
774 /* reset HAL2 */
775 hal2_write(0, &hal2->ctl_regs->isr);
776
777 /* release reset */
778 hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N,
779 &hal2->ctl_regs->isr);
780
781
782 hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
783 rev = hal2_read(&hal2->ctl_regs->rev);
784 if (rev & H2_REV_AUDIO_PRESENT)
785 return -ENODEV;
786
787 board = (rev & H2_REV_BOARD_M) >> 12;
788 major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
789 minor = (rev & H2_REV_MINOR_CHIP_M);
790
791 printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
792 board, major, minor);
793
794 return 0;
795 }
796
797 static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip)
798 {
799 struct snd_hal2 *hal2;
800 struct hpc3_regs *hpc3 = hpc3c0;
801 int err;
802
803 hal2 = kzalloc(sizeof(*hal2), GFP_KERNEL);
804 if (!hal2)
805 return -ENOMEM;
806
807 hal2->card = card;
808
809 if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
810 "SGI HAL2", hal2)) {
811 printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
812 kfree(hal2);
813 return -EAGAIN;
814 }
815
816 hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
817 hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
818 hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
819 hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
820
821 if (hal2_detect(hal2) < 0) {
822 kfree(hal2);
823 return -ENODEV;
824 }
825
826 hal2_init_codec(&hal2->dac, hpc3, 0);
827 hal2_init_codec(&hal2->adc, hpc3, 1);
828
829 /*
830 * All DMA channel interfaces in HAL2 are designed to operate with
831 * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
832 * in D5. HAL2 is a 16-bit device which can accept both big and little
833 * endian format. It assumes that even address bytes are on high
834 * portion of PBUS (15:8) and assumes that HPC3 is programmed to
835 * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
836 */
837 #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
838 (2 << HPC3_DMACFG_D4R_SHIFT) | \
839 (2 << HPC3_DMACFG_D5R_SHIFT) | \
840 (0 << HPC3_DMACFG_D3W_SHIFT) | \
841 (2 << HPC3_DMACFG_D4W_SHIFT) | \
842 (2 << HPC3_DMACFG_D5W_SHIFT) | \
843 HPC3_DMACFG_DS16 | \
844 HPC3_DMACFG_EVENHI | \
845 HPC3_DMACFG_RTIME | \
846 (8 << HPC3_DMACFG_BURST_SHIFT) | \
847 HPC3_DMACFG_DRQLIVE)
848 /*
849 * Ignore what's mentioned in the specification and write value which
850 * works in The Real World (TM)
851 */
852 hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
853 hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
854
855 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops);
856 if (err < 0) {
857 free_irq(SGI_HPCDMA_IRQ, hal2);
858 kfree(hal2);
859 return err;
860 }
861 *rchip = hal2;
862 return 0;
863 }
864
865 static int hal2_probe(struct platform_device *pdev)
866 {
867 struct snd_card *card;
868 struct snd_hal2 *chip;
869 int err;
870
871 err = snd_card_new(&pdev->dev, index, id, THIS_MODULE, 0, &card);
872 if (err < 0)
873 return err;
874
875 err = hal2_create(card, &chip);
876 if (err < 0) {
877 snd_card_free(card);
878 return err;
879 }
880
881 err = hal2_pcm_create(chip);
882 if (err < 0) {
883 snd_card_free(card);
884 return err;
885 }
886 err = hal2_mixer_create(chip);
887 if (err < 0) {
888 snd_card_free(card);
889 return err;
890 }
891
892 strcpy(card->driver, "SGI HAL2 Audio");
893 strcpy(card->shortname, "SGI HAL2 Audio");
894 sprintf(card->longname, "%s irq %i",
895 card->shortname,
896 SGI_HPCDMA_IRQ);
897
898 err = snd_card_register(card);
899 if (err < 0) {
900 snd_card_free(card);
901 return err;
902 }
903 platform_set_drvdata(pdev, card);
904 return 0;
905 }
906
907 static int hal2_remove(struct platform_device *pdev)
908 {
909 struct snd_card *card = platform_get_drvdata(pdev);
910
911 snd_card_free(card);
912 return 0;
913 }
914
915 static struct platform_driver hal2_driver = {
916 .probe = hal2_probe,
917 .remove = hal2_remove,
918 .driver = {
919 .name = "sgihal2",
920 }
921 };
922
923 module_platform_driver(hal2_driver);
connection oriented routing