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split dev_queue
[cor.git] / drivers / ata / sata_fsl.c
blob9239615d8a0472967fa534f0dcd8523da944ea1a
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/ata/sata_fsl.c
4 *
5 * Freescale 3.0Gbps SATA device driver
6 *
7 * Author: Ashish Kalra <ashish.kalra@freescale.com>
8 * Li Yang <leoli@freescale.com>
9 *
10 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17
18 #include <scsi/scsi_host.h>
19 #include <scsi/scsi_cmnd.h>
20 #include <linux/libata.h>
21 #include <asm/io.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25
26 static unsigned int intr_coalescing_count;
27 module_param(intr_coalescing_count, int, S_IRUGO);
28 MODULE_PARM_DESC(intr_coalescing_count,
29 "INT coalescing count threshold (1..31)");
30
31 static unsigned int intr_coalescing_ticks;
32 module_param(intr_coalescing_ticks, int, S_IRUGO);
33 MODULE_PARM_DESC(intr_coalescing_ticks,
34 "INT coalescing timer threshold in AHB ticks");
35 /* Controller information */
36 enum {
37 SATA_FSL_QUEUE_DEPTH = 16,
38 SATA_FSL_MAX_PRD = 63,
39 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
40 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
41
42 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
43 ATA_FLAG_PMP | ATA_FLAG_NCQ |
44 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
45
46 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
47 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
48 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
49
50 /*
51 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
52 * chained indirect PRDEs up to a max count of 63.
53 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
54 * be setup as an indirect descriptor, pointing to it's next
55 * (contiguous) PRDE. Though chained indirect PRDE arrays are
56 * supported,it will be more efficient to use a direct PRDT and
57 * a single chain/link to indirect PRDE array/PRDT.
58 */
59
60 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
61 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
62 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
63 SATA_FSL_CMD_DESC_RSRVD = 16,
64
65 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD +
69 SATA_FSL_MAX_PRD * 16),
70
71 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
72 (SATA_FSL_CMD_DESC_CFIS_SZ +
73 SATA_FSL_CMD_DESC_SFIS_SZ +
74 SATA_FSL_CMD_DESC_ACMD_SZ +
75 SATA_FSL_CMD_DESC_RSRVD),
76
77 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
78 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
79 SATA_FSL_CMD_DESC_AR_SZ),
80
81 /*
82 * MPC8315 has two SATA controllers, SATA1 & SATA2
83 * (one port per controller)
84 * MPC837x has 2/4 controllers, one port per controller
85 */
86
87 SATA_FSL_MAX_PORTS = 1,
88
89 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
90 };
91
92 /*
93 * Interrupt Coalescing Control Register bitdefs */
94 enum {
95 ICC_MIN_INT_COUNT_THRESHOLD = 1,
96 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
97 ICC_MIN_INT_TICKS_THRESHOLD = 0,
98 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
99 ICC_SAFE_INT_TICKS = 1,
100 };
101
102 /*
103 * Host Controller command register set - per port
104 */
105 enum {
106 CQ = 0,
107 CA = 8,
108 CC = 0x10,
109 CE = 0x18,
110 DE = 0x20,
111 CHBA = 0x24,
112 HSTATUS = 0x28,
113 HCONTROL = 0x2C,
114 CQPMP = 0x30,
115 SIGNATURE = 0x34,
116 ICC = 0x38,
117
118 /*
119 * Host Status Register (HStatus) bitdefs
120 */
121 ONLINE = (1 << 31),
122 GOING_OFFLINE = (1 << 30),
123 BIST_ERR = (1 << 29),
124 CLEAR_ERROR = (1 << 27),
125
126 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
127 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
128 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
129 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
130 FATAL_ERR_DATA_OVERRUN = (1 << 12),
131 FATAL_ERR_CRC_ERR_TX = (1 << 11),
132 FATAL_ERR_CRC_ERR_RX = (1 << 10),
133 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
134 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
135
136 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
137 FATAL_ERR_PARITY_ERR_TX |
138 FATAL_ERR_PARITY_ERR_RX |
139 FATAL_ERR_DATA_UNDERRUN |
140 FATAL_ERR_DATA_OVERRUN |
141 FATAL_ERR_CRC_ERR_TX |
142 FATAL_ERR_CRC_ERR_RX |
143 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
144
145 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
146 INT_ON_FATAL_ERR = (1 << 5),
147 INT_ON_PHYRDY_CHG = (1 << 4),
148
149 INT_ON_SIGNATURE_UPDATE = (1 << 3),
150 INT_ON_SNOTIFY_UPDATE = (1 << 2),
151 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
152 INT_ON_CMD_COMPLETE = 1,
153
154 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
155 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
156
157 /*
158 * Host Control Register (HControl) bitdefs
159 */
160 HCONTROL_ONLINE_PHY_RST = (1 << 31),
161 HCONTROL_FORCE_OFFLINE = (1 << 30),
162 HCONTROL_LEGACY = (1 << 28),
163 HCONTROL_PARITY_PROT_MOD = (1 << 14),
164 HCONTROL_DPATH_PARITY = (1 << 12),
165 HCONTROL_SNOOP_ENABLE = (1 << 10),
166 HCONTROL_PMP_ATTACHED = (1 << 9),
167 HCONTROL_COPYOUT_STATFIS = (1 << 8),
168 IE_ON_FATAL_ERR = (1 << 5),
169 IE_ON_PHYRDY_CHG = (1 << 4),
170 IE_ON_SIGNATURE_UPDATE = (1 << 3),
171 IE_ON_SNOTIFY_UPDATE = (1 << 2),
172 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
173 IE_ON_CMD_COMPLETE = 1,
174
175 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
176 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
177 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
178
179 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
180 DATA_SNOOP_ENABLE_V1 = (1 << 22),
181 DATA_SNOOP_ENABLE_V2 = (1 << 28),
182 };
183
184 /*
185 * SATA Superset Registers
186 */
187 enum {
188 SSTATUS = 0,
189 SERROR = 4,
190 SCONTROL = 8,
191 SNOTIFY = 0xC,
192 };
193
194 /*
195 * Control Status Register Set
196 */
197 enum {
198 TRANSCFG = 0,
199 TRANSSTATUS = 4,
200 LINKCFG = 8,
201 LINKCFG1 = 0xC,
202 LINKCFG2 = 0x10,
203 LINKSTATUS = 0x14,
204 LINKSTATUS1 = 0x18,
205 PHYCTRLCFG = 0x1C,
206 COMMANDSTAT = 0x20,
207 };
208
209 /* TRANSCFG (transport-layer) configuration control */
210 enum {
211 TRANSCFG_RX_WATER_MARK = (1 << 4),
212 };
213
214 /* PHY (link-layer) configuration control */
215 enum {
216 PHY_BIST_ENABLE = 0x01,
217 };
218
219 /*
220 * Command Header Table entry, i.e, command slot
221 * 4 Dwords per command slot, command header size == 64 Dwords.
222 */
223 struct cmdhdr_tbl_entry {
224 u32 cda;
225 u32 prde_fis_len;
226 u32 ttl;
227 u32 desc_info;
228 };
229
230 /*
231 * Description information bitdefs
232 */
233 enum {
234 CMD_DESC_RES = (1 << 11),
235 VENDOR_SPECIFIC_BIST = (1 << 10),
236 CMD_DESC_SNOOP_ENABLE = (1 << 9),
237 FPDMA_QUEUED_CMD = (1 << 8),
238 SRST_CMD = (1 << 7),
239 BIST = (1 << 6),
240 ATAPI_CMD = (1 << 5),
241 };
242
243 /*
244 * Command Descriptor
245 */
246 struct command_desc {
247 u8 cfis[8 * 4];
248 u8 sfis[8 * 4];
249 u8 acmd[4 * 4];
250 u8 fill[4 * 4];
251 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
252 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
253 };
254
255 /*
256 * Physical region table descriptor(PRD)
257 */
258
259 struct prde {
260 u32 dba;
261 u8 fill[2 * 4];
262 u32 ddc_and_ext;
263 };
264
265 /*
266 * ata_port private data
267 * This is our per-port instance data.
268 */
269 struct sata_fsl_port_priv {
270 struct cmdhdr_tbl_entry *cmdslot;
271 dma_addr_t cmdslot_paddr;
272 struct command_desc *cmdentry;
273 dma_addr_t cmdentry_paddr;
274 };
275
276 /*
277 * ata_port->host_set private data
278 */
279 struct sata_fsl_host_priv {
280 void __iomem *hcr_base;
281 void __iomem *ssr_base;
282 void __iomem *csr_base;
283 int irq;
284 int data_snoop;
285 struct device_attribute intr_coalescing;
286 struct device_attribute rx_watermark;
287 };
288
289 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
290 unsigned int count, unsigned int ticks)
291 {
292 struct sata_fsl_host_priv *host_priv = host->private_data;
293 void __iomem *hcr_base = host_priv->hcr_base;
294 unsigned long flags;
295
296 if (count > ICC_MAX_INT_COUNT_THRESHOLD)
297 count = ICC_MAX_INT_COUNT_THRESHOLD;
298 else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
299 count = ICC_MIN_INT_COUNT_THRESHOLD;
300
301 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
302 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
303 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
304 (count > ICC_MIN_INT_COUNT_THRESHOLD))
305 ticks = ICC_SAFE_INT_TICKS;
306
307 spin_lock_irqsave(&host->lock, flags);
308 iowrite32((count << 24 | ticks), hcr_base + ICC);
309
310 intr_coalescing_count = count;
311 intr_coalescing_ticks = ticks;
312 spin_unlock_irqrestore(&host->lock, flags);
313
314 DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
315 intr_coalescing_count, intr_coalescing_ticks);
316 DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
317 hcr_base, ioread32(hcr_base + ICC));
318 }
319
320 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
321 struct device_attribute *attr, char *buf)
322 {
323 return sprintf(buf, "%d %d\n",
324 intr_coalescing_count, intr_coalescing_ticks);
325 }
326
327 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
328 struct device_attribute *attr,
329 const char *buf, size_t count)
330 {
331 unsigned int coalescing_count, coalescing_ticks;
332
333 if (sscanf(buf, "%d%d",
334 &coalescing_count,
335 &coalescing_ticks) != 2) {
336 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
337 return -EINVAL;
338 }
339
340 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
341 coalescing_count, coalescing_ticks);
342
343 return strlen(buf);
344 }
345
346 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
347 struct device_attribute *attr, char *buf)
348 {
349 unsigned int rx_watermark;
350 unsigned long flags;
351 struct ata_host *host = dev_get_drvdata(dev);
352 struct sata_fsl_host_priv *host_priv = host->private_data;
353 void __iomem *csr_base = host_priv->csr_base;
354
355 spin_lock_irqsave(&host->lock, flags);
356 rx_watermark = ioread32(csr_base + TRANSCFG);
357 rx_watermark &= 0x1f;
358
359 spin_unlock_irqrestore(&host->lock, flags);
360 return sprintf(buf, "%d\n", rx_watermark);
361 }
362
363 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
364 struct device_attribute *attr,
365 const char *buf, size_t count)
366 {
367 unsigned int rx_watermark;
368 unsigned long flags;
369 struct ata_host *host = dev_get_drvdata(dev);
370 struct sata_fsl_host_priv *host_priv = host->private_data;
371 void __iomem *csr_base = host_priv->csr_base;
372 u32 temp;
373
374 if (sscanf(buf, "%d", &rx_watermark) != 1) {
375 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
376 return -EINVAL;
377 }
378
379 spin_lock_irqsave(&host->lock, flags);
380 temp = ioread32(csr_base + TRANSCFG);
381 temp &= 0xffffffe0;
382 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
383
384 spin_unlock_irqrestore(&host->lock, flags);
385 return strlen(buf);
386 }
387
388 static inline unsigned int sata_fsl_tag(unsigned int tag,
389 void __iomem *hcr_base)
390 {
391 /* We let libATA core do actual (queue) tag allocation */
392
393 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
394 DPRINTK("tag %d invalid : out of range\n", tag);
395 return 0;
396 }
397
398 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
399 DPRINTK("tag %d invalid : in use!!\n", tag);
400 return 0;
401 }
402
403 return tag;
404 }
405
406 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
407 unsigned int tag, u32 desc_info,
408 u32 data_xfer_len, u8 num_prde,
409 u8 fis_len)
410 {
411 dma_addr_t cmd_descriptor_address;
412
413 cmd_descriptor_address = pp->cmdentry_paddr +
414 tag * SATA_FSL_CMD_DESC_SIZE;
415
416 /* NOTE: both data_xfer_len & fis_len are Dword counts */
417
418 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
419 pp->cmdslot[tag].prde_fis_len =
420 cpu_to_le32((num_prde << 16) | (fis_len << 2));
421 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
422 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
423
424 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
425 pp->cmdslot[tag].cda,
426 pp->cmdslot[tag].prde_fis_len,
427 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
428
429 }
430
431 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
432 u32 *ttl, dma_addr_t cmd_desc_paddr,
433 int data_snoop)
434 {
435 struct scatterlist *sg;
436 unsigned int num_prde = 0;
437 u32 ttl_dwords = 0;
438
439 /*
440 * NOTE : direct & indirect prdt's are contiguously allocated
441 */
442 struct prde *prd = (struct prde *)&((struct command_desc *)
443 cmd_desc)->prdt;
444
445 struct prde *prd_ptr_to_indirect_ext = NULL;
446 unsigned indirect_ext_segment_sz = 0;
447 dma_addr_t indirect_ext_segment_paddr;
448 unsigned int si;
449
450 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
451
452 indirect_ext_segment_paddr = cmd_desc_paddr +
453 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
454
455 for_each_sg(qc->sg, sg, qc->n_elem, si) {
456 dma_addr_t sg_addr = sg_dma_address(sg);
457 u32 sg_len = sg_dma_len(sg);
458
459 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
460 (unsigned long long)sg_addr, sg_len);
461
462 /* warn if each s/g element is not dword aligned */
463 if (unlikely(sg_addr & 0x03))
464 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
465 (unsigned long long)sg_addr);
466 if (unlikely(sg_len & 0x03))
467 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
468 sg_len);
469
470 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
471 sg_next(sg) != NULL) {
472 VPRINTK("setting indirect prde\n");
473 prd_ptr_to_indirect_ext = prd;
474 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
475 indirect_ext_segment_sz = 0;
476 ++prd;
477 ++num_prde;
478 }
479
480 ttl_dwords += sg_len;
481 prd->dba = cpu_to_le32(sg_addr);
482 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
483
484 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
485 ttl_dwords, prd->dba, prd->ddc_and_ext);
486
487 ++num_prde;
488 ++prd;
489 if (prd_ptr_to_indirect_ext)
490 indirect_ext_segment_sz += sg_len;
491 }
492
493 if (prd_ptr_to_indirect_ext) {
494 /* set indirect extension flag along with indirect ext. size */
495 prd_ptr_to_indirect_ext->ddc_and_ext =
496 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
497 data_snoop |
498 (indirect_ext_segment_sz & ~0x03)));
499 }
500
501 *ttl = ttl_dwords;
502 return num_prde;
503 }
504
505 static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
506 {
507 struct ata_port *ap = qc->ap;
508 struct sata_fsl_port_priv *pp = ap->private_data;
509 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
510 void __iomem *hcr_base = host_priv->hcr_base;
511 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
512 struct command_desc *cd;
513 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
514 u32 num_prde = 0;
515 u32 ttl_dwords = 0;
516 dma_addr_t cd_paddr;
517
518 cd = (struct command_desc *)pp->cmdentry + tag;
519 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
520
521 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
522
523 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
524 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
525
526 if (qc->tf.protocol == ATA_PROT_NCQ) {
527 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
528 cd->cfis[3], cd->cfis[11]);
529 }
530
531 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
532 if (ata_is_atapi(qc->tf.protocol)) {
533 desc_info |= ATAPI_CMD;
534 memset((void *)&cd->acmd, 0, 32);
535 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
536 }
537
538 if (qc->flags & ATA_QCFLAG_DMAMAP)
539 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
540 &ttl_dwords, cd_paddr,
541 host_priv->data_snoop);
542
543 if (qc->tf.protocol == ATA_PROT_NCQ)
544 desc_info |= FPDMA_QUEUED_CMD;
545
546 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
547 num_prde, 5);
548
549 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
550 desc_info, ttl_dwords, num_prde);
551
552 return AC_ERR_OK;
553 }
554
555 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
556 {
557 struct ata_port *ap = qc->ap;
558 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
559 void __iomem *hcr_base = host_priv->hcr_base;
560 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
561
562 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
563 ioread32(CQ + hcr_base),
564 ioread32(CA + hcr_base),
565 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
566
567 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
568
569 /* Simply queue command to the controller/device */
570 iowrite32(1 << tag, CQ + hcr_base);
571
572 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
573 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
574
575 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
576 ioread32(CE + hcr_base),
577 ioread32(DE + hcr_base),
578 ioread32(CC + hcr_base),
579 ioread32(COMMANDSTAT + host_priv->csr_base));
580
581 return 0;
582 }
583
584 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
585 {
586 struct sata_fsl_port_priv *pp = qc->ap->private_data;
587 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
588 void __iomem *hcr_base = host_priv->hcr_base;
589 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
590 struct command_desc *cd;
591
592 cd = pp->cmdentry + tag;
593
594 ata_tf_from_fis(cd->sfis, &qc->result_tf);
595 return true;
596 }
597
598 static int sata_fsl_scr_write(struct ata_link *link,
599 unsigned int sc_reg_in, u32 val)
600 {
601 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
602 void __iomem *ssr_base = host_priv->ssr_base;
603 unsigned int sc_reg;
604
605 switch (sc_reg_in) {
606 case SCR_STATUS:
607 case SCR_ERROR:
608 case SCR_CONTROL:
609 case SCR_ACTIVE:
610 sc_reg = sc_reg_in;
611 break;
612 default:
613 return -EINVAL;
614 }
615
616 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
617
618 iowrite32(val, ssr_base + (sc_reg * 4));
619 return 0;
620 }
621
622 static int sata_fsl_scr_read(struct ata_link *link,
623 unsigned int sc_reg_in, u32 *val)
624 {
625 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
626 void __iomem *ssr_base = host_priv->ssr_base;
627 unsigned int sc_reg;
628
629 switch (sc_reg_in) {
630 case SCR_STATUS:
631 case SCR_ERROR:
632 case SCR_CONTROL:
633 case SCR_ACTIVE:
634 sc_reg = sc_reg_in;
635 break;
636 default:
637 return -EINVAL;
638 }
639
640 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
641
642 *val = ioread32(ssr_base + (sc_reg * 4));
643 return 0;
644 }
645
646 static void sata_fsl_freeze(struct ata_port *ap)
647 {
648 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
649 void __iomem *hcr_base = host_priv->hcr_base;
650 u32 temp;
651
652 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
653 ioread32(CQ + hcr_base),
654 ioread32(CA + hcr_base),
655 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
656 VPRINTK("CmdStat = 0x%x\n",
657 ioread32(host_priv->csr_base + COMMANDSTAT));
658
659 /* disable interrupts on the controller/port */
660 temp = ioread32(hcr_base + HCONTROL);
661 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
662
663 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
664 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
665 }
666
667 static void sata_fsl_thaw(struct ata_port *ap)
668 {
669 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
670 void __iomem *hcr_base = host_priv->hcr_base;
671 u32 temp;
672
673 /* ack. any pending IRQs for this controller/port */
674 temp = ioread32(hcr_base + HSTATUS);
675
676 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
677
678 if (temp & 0x3F)
679 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
680
681 /* enable interrupts on the controller/port */
682 temp = ioread32(hcr_base + HCONTROL);
683 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
684
685 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
686 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
687 }
688
689 static void sata_fsl_pmp_attach(struct ata_port *ap)
690 {
691 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
692 void __iomem *hcr_base = host_priv->hcr_base;
693 u32 temp;
694
695 temp = ioread32(hcr_base + HCONTROL);
696 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
697 }
698
699 static void sata_fsl_pmp_detach(struct ata_port *ap)
700 {
701 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
702 void __iomem *hcr_base = host_priv->hcr_base;
703 u32 temp;
704
705 temp = ioread32(hcr_base + HCONTROL);
706 temp &= ~HCONTROL_PMP_ATTACHED;
707 iowrite32(temp, hcr_base + HCONTROL);
708
709 /* enable interrupts on the controller/port */
710 temp = ioread32(hcr_base + HCONTROL);
711 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
712
713 }
714
715 static int sata_fsl_port_start(struct ata_port *ap)
716 {
717 struct device *dev = ap->host->dev;
718 struct sata_fsl_port_priv *pp;
719 void *mem;
720 dma_addr_t mem_dma;
721 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
722 void __iomem *hcr_base = host_priv->hcr_base;
723 u32 temp;
724
725 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
726 if (!pp)
727 return -ENOMEM;
728
729 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
730 GFP_KERNEL);
731 if (!mem) {
732 kfree(pp);
733 return -ENOMEM;
734 }
735
736 pp->cmdslot = mem;
737 pp->cmdslot_paddr = mem_dma;
738
739 mem += SATA_FSL_CMD_SLOT_SIZE;
740 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
741
742 pp->cmdentry = mem;
743 pp->cmdentry_paddr = mem_dma;
744
745 ap->private_data = pp;
746
747 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
748 pp->cmdslot_paddr, pp->cmdentry_paddr);
749
750 /* Now, update the CHBA register in host controller cmd register set */
751 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
752
753 /*
754 * Now, we can bring the controller on-line & also initiate
755 * the COMINIT sequence, we simply return here and the boot-probing
756 * & device discovery process is re-initiated by libATA using a
757 * Softreset EH (dummy) session. Hence, boot probing and device
758 * discovey will be part of sata_fsl_softreset() callback.
759 */
760
761 temp = ioread32(hcr_base + HCONTROL);
762 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
763
764 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
765 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
766 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
767
768 return 0;
769 }
770
771 static void sata_fsl_port_stop(struct ata_port *ap)
772 {
773 struct device *dev = ap->host->dev;
774 struct sata_fsl_port_priv *pp = ap->private_data;
775 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
776 void __iomem *hcr_base = host_priv->hcr_base;
777 u32 temp;
778
779 /*
780 * Force host controller to go off-line, aborting current operations
781 */
782 temp = ioread32(hcr_base + HCONTROL);
783 temp &= ~HCONTROL_ONLINE_PHY_RST;
784 temp |= HCONTROL_FORCE_OFFLINE;
785 iowrite32(temp, hcr_base + HCONTROL);
786
787 /* Poll for controller to go offline - should happen immediately */
788 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
789
790 ap->private_data = NULL;
791 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
792 pp->cmdslot, pp->cmdslot_paddr);
793
794 kfree(pp);
795 }
796
797 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
798 {
799 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
800 void __iomem *hcr_base = host_priv->hcr_base;
801 struct ata_taskfile tf;
802 u32 temp;
803
804 temp = ioread32(hcr_base + SIGNATURE);
805
806 VPRINTK("raw sig = 0x%x\n", temp);
807 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
808 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
809
810 tf.lbah = (temp >> 24) & 0xff;
811 tf.lbam = (temp >> 16) & 0xff;
812 tf.lbal = (temp >> 8) & 0xff;
813 tf.nsect = temp & 0xff;
814
815 return ata_dev_classify(&tf);
816 }
817
818 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
819 unsigned long deadline)
820 {
821 struct ata_port *ap = link->ap;
822 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
823 void __iomem *hcr_base = host_priv->hcr_base;
824 u32 temp;
825 int i = 0;
826 unsigned long start_jiffies;
827
828 DPRINTK("in xx_hardreset\n");
829
830 try_offline_again:
831 /*
832 * Force host controller to go off-line, aborting current operations
833 */
834 temp = ioread32(hcr_base + HCONTROL);
835 temp &= ~HCONTROL_ONLINE_PHY_RST;
836 iowrite32(temp, hcr_base + HCONTROL);
837
838 /* Poll for controller to go offline */
839 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
840 1, 500);
841
842 if (temp & ONLINE) {
843 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
844
845 /*
846 * Try to offline controller atleast twice
847 */
848 i++;
849 if (i == 2)
850 goto err;
851 else
852 goto try_offline_again;
853 }
854
855 DPRINTK("hardreset, controller off-lined\n");
856 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
857 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
858
859 /*
860 * PHY reset should remain asserted for atleast 1ms
861 */
862 ata_msleep(ap, 1);
863
864 sata_set_spd(link);
865
866 /*
867 * Now, bring the host controller online again, this can take time
868 * as PHY reset and communication establishment, 1st D2H FIS and
869 * device signature update is done, on safe side assume 500ms
870 * NOTE : Host online status may be indicated immediately!!
871 */
872
873 temp = ioread32(hcr_base + HCONTROL);
874 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
875 temp |= HCONTROL_PMP_ATTACHED;
876 iowrite32(temp, hcr_base + HCONTROL);
877
878 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
879
880 if (!(temp & ONLINE)) {
881 ata_port_err(ap, "Hardreset failed, not on-lined\n");
882 goto err;
883 }
884
885 DPRINTK("hardreset, controller off-lined & on-lined\n");
886 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
887 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
888
889 /*
890 * First, wait for the PHYRDY change to occur before waiting for
891 * the signature, and also verify if SStatus indicates device
892 * presence
893 */
894
895 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
896 if ((!(temp & 0x10)) || ata_link_offline(link)) {
897 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
898 ioread32(hcr_base + HSTATUS));
899 *class = ATA_DEV_NONE;
900 return 0;
901 }
902
903 /*
904 * Wait for the first D2H from device,i.e,signature update notification
905 */
906 start_jiffies = jiffies;
907 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
908 500, jiffies_to_msecs(deadline - start_jiffies));
909
910 if ((temp & 0xFF) != 0x18) {
911 ata_port_warn(ap, "No Signature Update\n");
912 *class = ATA_DEV_NONE;
913 goto do_followup_srst;
914 } else {
915 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
916 jiffies_to_msecs(jiffies - start_jiffies));
917 *class = sata_fsl_dev_classify(ap);
918 return 0;
919 }
920
921 do_followup_srst:
922 /*
923 * request libATA to perform follow-up softreset
924 */
925 return -EAGAIN;
926
927 err:
928 return -EIO;
929 }
930
931 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
932 unsigned long deadline)
933 {
934 struct ata_port *ap = link->ap;
935 struct sata_fsl_port_priv *pp = ap->private_data;
936 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
937 void __iomem *hcr_base = host_priv->hcr_base;
938 int pmp = sata_srst_pmp(link);
939 u32 temp;
940 struct ata_taskfile tf;
941 u8 *cfis;
942 u32 Serror;
943
944 DPRINTK("in xx_softreset\n");
945
946 if (ata_link_offline(link)) {
947 DPRINTK("PHY reports no device\n");
948 *class = ATA_DEV_NONE;
949 return 0;
950 }
951
952 /*
953 * Send a device reset (SRST) explicitly on command slot #0
954 * Check : will the command queue (reg) be cleared during offlining ??
955 * Also we will be online only if Phy commn. has been established
956 * and device presence has been detected, therefore if we have
957 * reached here, we can send a command to the target device
958 */
959
960 DPRINTK("Sending SRST/device reset\n");
961
962 ata_tf_init(link->device, &tf);
963 cfis = (u8 *) &pp->cmdentry->cfis;
964
965 /* device reset/SRST is a control register update FIS, uses tag0 */
966 sata_fsl_setup_cmd_hdr_entry(pp, 0,
967 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
968
969 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
970 ata_tf_to_fis(&tf, pmp, 0, cfis);
971
972 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
973 cfis[0], cfis[1], cfis[2], cfis[3]);
974
975 /*
976 * Queue SRST command to the controller/device, ensure that no
977 * other commands are active on the controller/device
978 */
979
980 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
981 ioread32(CQ + hcr_base),
982 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
983
984 iowrite32(0xFFFF, CC + hcr_base);
985 if (pmp != SATA_PMP_CTRL_PORT)
986 iowrite32(pmp, CQPMP + hcr_base);
987 iowrite32(1, CQ + hcr_base);
988
989 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
990 if (temp & 0x1) {
991 ata_port_warn(ap, "ATA_SRST issue failed\n");
992
993 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
994 ioread32(CQ + hcr_base),
995 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
996
997 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
998
999 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1000 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1001 DPRINTK("Serror = 0x%x\n", Serror);
1002 goto err;
1003 }
1004
1005 ata_msleep(ap, 1);
1006
1007 /*
1008 * SATA device enters reset state after receiving a Control register
1009 * FIS with SRST bit asserted and it awaits another H2D Control reg.
1010 * FIS with SRST bit cleared, then the device does internal diags &
1011 * initialization, followed by indicating it's initialization status
1012 * using ATA signature D2H register FIS to the host controller.
1013 */
1014
1015 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1016 0, 0, 5);
1017
1018 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
1019 ata_tf_to_fis(&tf, pmp, 0, cfis);
1020
1021 if (pmp != SATA_PMP_CTRL_PORT)
1022 iowrite32(pmp, CQPMP + hcr_base);
1023 iowrite32(1, CQ + hcr_base);
1024 ata_msleep(ap, 150); /* ?? */
1025
1026 /*
1027 * The above command would have signalled an interrupt on command
1028 * complete, which needs special handling, by clearing the Nth
1029 * command bit of the CCreg
1030 */
1031 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1032
1033 DPRINTK("SATA FSL : Now checking device signature\n");
1034
1035 *class = ATA_DEV_NONE;
1036
1037 /* Verify if SStatus indicates device presence */
1038 if (ata_link_online(link)) {
1039 /*
1040 * if we are here, device presence has been detected,
1041 * 1st D2H FIS would have been received, but sfis in
1042 * command desc. is not updated, but signature register
1043 * would have been updated
1044 */
1045
1046 *class = sata_fsl_dev_classify(ap);
1047
1048 DPRINTK("class = %d\n", *class);
1049 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1050 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1051 }
1052
1053 return 0;
1054
1055 err:
1056 return -EIO;
1057 }
1058
1059 static void sata_fsl_error_handler(struct ata_port *ap)
1060 {
1061
1062 DPRINTK("in xx_error_handler\n");
1063 sata_pmp_error_handler(ap);
1064
1065 }
1066
1067 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1068 {
1069 if (qc->flags & ATA_QCFLAG_FAILED)
1070 qc->err_mask |= AC_ERR_OTHER;
1071
1072 if (qc->err_mask) {
1073 /* make DMA engine forget about the failed command */
1074
1075 }
1076 }
1077
1078 static void sata_fsl_error_intr(struct ata_port *ap)
1079 {
1080 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1081 void __iomem *hcr_base = host_priv->hcr_base;
1082 u32 hstatus, dereg=0, cereg = 0, SError = 0;
1083 unsigned int err_mask = 0, action = 0;
1084 int freeze = 0, abort=0;
1085 struct ata_link *link = NULL;
1086 struct ata_queued_cmd *qc = NULL;
1087 struct ata_eh_info *ehi;
1088
1089 hstatus = ioread32(hcr_base + HSTATUS);
1090 cereg = ioread32(hcr_base + CE);
1091
1092 /* first, analyze and record host port events */
1093 link = &ap->link;
1094 ehi = &link->eh_info;
1095 ata_ehi_clear_desc(ehi);
1096
1097 /*
1098 * Handle & Clear SError
1099 */
1100
1101 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1102 if (unlikely(SError & 0xFFFF0000))
1103 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1104
1105 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1106 hstatus, cereg, ioread32(hcr_base + DE), SError);
1107
1108 /* handle fatal errors */
1109 if (hstatus & FATAL_ERROR_DECODE) {
1110 ehi->err_mask |= AC_ERR_ATA_BUS;
1111 ehi->action |= ATA_EH_SOFTRESET;
1112
1113 freeze = 1;
1114 }
1115
1116 /* Handle SDB FIS receive & notify update */
1117 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1118 sata_async_notification(ap);
1119
1120 /* Handle PHYRDY change notification */
1121 if (hstatus & INT_ON_PHYRDY_CHG) {
1122 DPRINTK("SATA FSL: PHYRDY change indication\n");
1123
1124 /* Setup a soft-reset EH action */
1125 ata_ehi_hotplugged(ehi);
1126 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1127 freeze = 1;
1128 }
1129
1130 /* handle single device errors */
1131 if (cereg) {
1132 /*
1133 * clear the command error, also clears queue to the device
1134 * in error, and we can (re)issue commands to this device.
1135 * When a device is in error all commands queued into the
1136 * host controller and at the device are considered aborted
1137 * and the queue for that device is stopped. Now, after
1138 * clearing the device error, we can issue commands to the
1139 * device to interrogate it to find the source of the error.
1140 */
1141 abort = 1;
1142
1143 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1144 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1145
1146 /* find out the offending link and qc */
1147 if (ap->nr_pmp_links) {
1148 unsigned int dev_num;
1149
1150 dereg = ioread32(hcr_base + DE);
1151 iowrite32(dereg, hcr_base + DE);
1152 iowrite32(cereg, hcr_base + CE);
1153
1154 dev_num = ffs(dereg) - 1;
1155 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1156 link = &ap->pmp_link[dev_num];
1157 ehi = &link->eh_info;
1158 qc = ata_qc_from_tag(ap, link->active_tag);
1159 /*
1160 * We should consider this as non fatal error,
1161 * and TF must be updated as done below.
1162 */
1163
1164 err_mask |= AC_ERR_DEV;
1165
1166 } else {
1167 err_mask |= AC_ERR_HSM;
1168 action |= ATA_EH_HARDRESET;
1169 freeze = 1;
1170 }
1171 } else {
1172 dereg = ioread32(hcr_base + DE);
1173 iowrite32(dereg, hcr_base + DE);
1174 iowrite32(cereg, hcr_base + CE);
1175
1176 qc = ata_qc_from_tag(ap, link->active_tag);
1177 /*
1178 * We should consider this as non fatal error,
1179 * and TF must be updated as done below.
1180 */
1181 err_mask |= AC_ERR_DEV;
1182 }
1183 }
1184
1185 /* record error info */
1186 if (qc)
1187 qc->err_mask |= err_mask;
1188 else
1189 ehi->err_mask |= err_mask;
1190
1191 ehi->action |= action;
1192
1193 /* freeze or abort */
1194 if (freeze)
1195 ata_port_freeze(ap);
1196 else if (abort) {
1197 if (qc)
1198 ata_link_abort(qc->dev->link);
1199 else
1200 ata_port_abort(ap);
1201 }
1202 }
1203
1204 static void sata_fsl_host_intr(struct ata_port *ap)
1205 {
1206 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1207 void __iomem *hcr_base = host_priv->hcr_base;
1208 u32 hstatus, done_mask = 0;
1209 struct ata_queued_cmd *qc;
1210 u32 SError;
1211 u32 tag;
1212 u32 status_mask = INT_ON_ERROR;
1213
1214 hstatus = ioread32(hcr_base + HSTATUS);
1215
1216 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1217
1218 /* Read command completed register */
1219 done_mask = ioread32(hcr_base + CC);
1220
1221 /* Workaround for data length mismatch errata */
1222 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1223 ata_qc_for_each_with_internal(ap, qc, tag) {
1224 if (qc && ata_is_atapi(qc->tf.protocol)) {
1225 u32 hcontrol;
1226 /* Set HControl[27] to clear error registers */
1227 hcontrol = ioread32(hcr_base + HCONTROL);
1228 iowrite32(hcontrol | CLEAR_ERROR,
1229 hcr_base + HCONTROL);
1230
1231 /* Clear HControl[27] */
1232 iowrite32(hcontrol & ~CLEAR_ERROR,
1233 hcr_base + HCONTROL);
1234
1235 /* Clear SError[E] bit */
1236 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1237 SError);
1238
1239 /* Ignore fatal error and device error */
1240 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1241 | INT_ON_FATAL_ERR);
1242 break;
1243 }
1244 }
1245 }
1246
1247 if (unlikely(SError & 0xFFFF0000)) {
1248 DPRINTK("serror @host_intr : 0x%x\n", SError);
1249 sata_fsl_error_intr(ap);
1250 }
1251
1252 if (unlikely(hstatus & status_mask)) {
1253 DPRINTK("error interrupt!!\n");
1254 sata_fsl_error_intr(ap);
1255 return;
1256 }
1257
1258 VPRINTK("Status of all queues :\n");
1259 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
1260 done_mask,
1261 ioread32(hcr_base + CA),
1262 ioread32(hcr_base + CE),
1263 ioread32(hcr_base + CQ),
1264 ap->qc_active);
1265
1266 if (done_mask & ap->qc_active) {
1267 int i;
1268 /* clear CC bit, this will also complete the interrupt */
1269 iowrite32(done_mask, hcr_base + CC);
1270
1271 DPRINTK("Status of all queues :\n");
1272 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1273 done_mask, ioread32(hcr_base + CA),
1274 ioread32(hcr_base + CE));
1275
1276 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1277 if (done_mask & (1 << i))
1278 DPRINTK
1279 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1280 i, ioread32(hcr_base + CC),
1281 ioread32(hcr_base + CA));
1282 }
1283 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1284 return;
1285
1286 } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
1287 iowrite32(1, hcr_base + CC);
1288 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1289
1290 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1291 ioread32(hcr_base + CC));
1292
1293 if (qc) {
1294 ata_qc_complete(qc);
1295 }
1296 } else {
1297 /* Spurious Interrupt!! */
1298 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1299 ioread32(hcr_base + CC));
1300 iowrite32(done_mask, hcr_base + CC);
1301 return;
1302 }
1303 }
1304
1305 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1306 {
1307 struct ata_host *host = dev_instance;
1308 struct sata_fsl_host_priv *host_priv = host->private_data;
1309 void __iomem *hcr_base = host_priv->hcr_base;
1310 u32 interrupt_enables;
1311 unsigned handled = 0;
1312 struct ata_port *ap;
1313
1314 /* ack. any pending IRQs for this controller/port */
1315 interrupt_enables = ioread32(hcr_base + HSTATUS);
1316 interrupt_enables &= 0x3F;
1317
1318 DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1319
1320 if (!interrupt_enables)
1321 return IRQ_NONE;
1322
1323 spin_lock(&host->lock);
1324
1325 /* Assuming one port per host controller */
1326
1327 ap = host->ports[0];
1328 if (ap) {
1329 sata_fsl_host_intr(ap);
1330 } else {
1331 dev_warn(host->dev, "interrupt on disabled port 0\n");
1332 }
1333
1334 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1335 handled = 1;
1336
1337 spin_unlock(&host->lock);
1338
1339 return IRQ_RETVAL(handled);
1340 }
1341
1342 /*
1343 * Multiple ports are represented by multiple SATA controllers with
1344 * one port per controller
1345 */
1346 static int sata_fsl_init_controller(struct ata_host *host)
1347 {
1348 struct sata_fsl_host_priv *host_priv = host->private_data;
1349 void __iomem *hcr_base = host_priv->hcr_base;
1350 u32 temp;
1351
1352 /*
1353 * NOTE : We cannot bring the controller online before setting
1354 * the CHBA, hence main controller initialization is done as
1355 * part of the port_start() callback
1356 */
1357
1358 /* sata controller to operate in enterprise mode */
1359 temp = ioread32(hcr_base + HCONTROL);
1360 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1361
1362 /* ack. any pending IRQs for this controller/port */
1363 temp = ioread32(hcr_base + HSTATUS);
1364 if (temp & 0x3F)
1365 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1366
1367 /* Keep interrupts disabled on the controller */
1368 temp = ioread32(hcr_base + HCONTROL);
1369 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1370
1371 /* Disable interrupt coalescing control(icc), for the moment */
1372 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1373 iowrite32(0x01000000, hcr_base + ICC);
1374
1375 /* clear error registers, SError is cleared by libATA */
1376 iowrite32(0x00000FFFF, hcr_base + CE);
1377 iowrite32(0x00000FFFF, hcr_base + DE);
1378
1379 /*
1380 * reset the number of command complete bits which will cause the
1381 * interrupt to be signaled
1382 */
1383 fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1384 intr_coalescing_ticks);
1385
1386 /*
1387 * host controller will be brought on-line, during xx_port_start()
1388 * callback, that should also initiate the OOB, COMINIT sequence
1389 */
1390
1391 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1392 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1393
1394 return 0;
1395 }
1396
1397 /*
1398 * scsi mid-layer and libata interface structures
1399 */
1400 static struct scsi_host_template sata_fsl_sht = {
1401 ATA_NCQ_SHT("sata_fsl"),
1402 .can_queue = SATA_FSL_QUEUE_DEPTH,
1403 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1404 .dma_boundary = ATA_DMA_BOUNDARY,
1405 };
1406
1407 static struct ata_port_operations sata_fsl_ops = {
1408 .inherits = &sata_pmp_port_ops,
1409
1410 .qc_defer = ata_std_qc_defer,
1411 .qc_prep = sata_fsl_qc_prep,
1412 .qc_issue = sata_fsl_qc_issue,
1413 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1414
1415 .scr_read = sata_fsl_scr_read,
1416 .scr_write = sata_fsl_scr_write,
1417
1418 .freeze = sata_fsl_freeze,
1419 .thaw = sata_fsl_thaw,
1420 .softreset = sata_fsl_softreset,
1421 .hardreset = sata_fsl_hardreset,
1422 .pmp_softreset = sata_fsl_softreset,
1423 .error_handler = sata_fsl_error_handler,
1424 .post_internal_cmd = sata_fsl_post_internal_cmd,
1425
1426 .port_start = sata_fsl_port_start,
1427 .port_stop = sata_fsl_port_stop,
1428
1429 .pmp_attach = sata_fsl_pmp_attach,
1430 .pmp_detach = sata_fsl_pmp_detach,
1431 };
1432
1433 static const struct ata_port_info sata_fsl_port_info[] = {
1434 {
1435 .flags = SATA_FSL_HOST_FLAGS,
1436 .pio_mask = ATA_PIO4,
1437 .udma_mask = ATA_UDMA6,
1438 .port_ops = &sata_fsl_ops,
1439 },
1440 };
1441
1442 static int sata_fsl_probe(struct platform_device *ofdev)
1443 {
1444 int retval = -ENXIO;
1445 void __iomem *hcr_base = NULL;
1446 void __iomem *ssr_base = NULL;
1447 void __iomem *csr_base = NULL;
1448 struct sata_fsl_host_priv *host_priv = NULL;
1449 int irq;
1450 struct ata_host *host = NULL;
1451 u32 temp;
1452
1453 struct ata_port_info pi = sata_fsl_port_info[0];
1454 const struct ata_port_info *ppi[] = { &pi, NULL };
1455
1456 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1457
1458 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1459 if (!hcr_base)
1460 goto error_exit_with_cleanup;
1461
1462 ssr_base = hcr_base + 0x100;
1463 csr_base = hcr_base + 0x140;
1464
1465 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1466 temp = ioread32(csr_base + TRANSCFG);
1467 temp = temp & 0xffffffe0;
1468 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1469 }
1470
1471 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1472 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1473 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1474
1475 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1476 if (!host_priv)
1477 goto error_exit_with_cleanup;
1478
1479 host_priv->hcr_base = hcr_base;
1480 host_priv->ssr_base = ssr_base;
1481 host_priv->csr_base = csr_base;
1482
1483 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1484 if (!irq) {
1485 dev_err(&ofdev->dev, "invalid irq from platform\n");
1486 goto error_exit_with_cleanup;
1487 }
1488 host_priv->irq = irq;
1489
1490 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1491 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1492 else
1493 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1494
1495 /* allocate host structure */
1496 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1497 if (!host) {
1498 retval = -ENOMEM;
1499 goto error_exit_with_cleanup;
1500 }
1501
1502 /* host->iomap is not used currently */
1503 host->private_data = host_priv;
1504
1505 /* initialize host controller */
1506 sata_fsl_init_controller(host);
1507
1508 /*
1509 * Now, register with libATA core, this will also initiate the
1510 * device discovery process, invoking our port_start() handler &
1511 * error_handler() to execute a dummy Softreset EH session
1512 */
1513 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1514 &sata_fsl_sht);
1515
1516 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1517 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1518 sysfs_attr_init(&host_priv->intr_coalescing.attr);
1519 host_priv->intr_coalescing.attr.name = "intr_coalescing";
1520 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1521 retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1522 if (retval)
1523 goto error_exit_with_cleanup;
1524
1525 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1526 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1527 sysfs_attr_init(&host_priv->rx_watermark.attr);
1528 host_priv->rx_watermark.attr.name = "rx_watermark";
1529 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1530 retval = device_create_file(host->dev, &host_priv->rx_watermark);
1531 if (retval) {
1532 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1533 goto error_exit_with_cleanup;
1534 }
1535
1536 return 0;
1537
1538 error_exit_with_cleanup:
1539
1540 if (host)
1541 ata_host_detach(host);
1542
1543 if (hcr_base)
1544 iounmap(hcr_base);
1545 kfree(host_priv);
1546
1547 return retval;
1548 }
1549
1550 static int sata_fsl_remove(struct platform_device *ofdev)
1551 {
1552 struct ata_host *host = platform_get_drvdata(ofdev);
1553 struct sata_fsl_host_priv *host_priv = host->private_data;
1554
1555 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1556 device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1557
1558 ata_host_detach(host);
1559
1560 irq_dispose_mapping(host_priv->irq);
1561 iounmap(host_priv->hcr_base);
1562 kfree(host_priv);
1563
1564 return 0;
1565 }
1566
1567 #ifdef CONFIG_PM_SLEEP
1568 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1569 {
1570 struct ata_host *host = platform_get_drvdata(op);
1571 return ata_host_suspend(host, state);
1572 }
1573
1574 static int sata_fsl_resume(struct platform_device *op)
1575 {
1576 struct ata_host *host = platform_get_drvdata(op);
1577 struct sata_fsl_host_priv *host_priv = host->private_data;
1578 int ret;
1579 void __iomem *hcr_base = host_priv->hcr_base;
1580 struct ata_port *ap = host->ports[0];
1581 struct sata_fsl_port_priv *pp = ap->private_data;
1582
1583 ret = sata_fsl_init_controller(host);
1584 if (ret) {
1585 dev_err(&op->dev, "Error initializing hardware\n");
1586 return ret;
1587 }
1588
1589 /* Recovery the CHBA register in host controller cmd register set */
1590 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1591
1592 iowrite32((ioread32(hcr_base + HCONTROL)
1593 | HCONTROL_ONLINE_PHY_RST
1594 | HCONTROL_SNOOP_ENABLE
1595 | HCONTROL_PMP_ATTACHED),
1596 hcr_base + HCONTROL);
1597
1598 ata_host_resume(host);
1599 return 0;
1600 }
1601 #endif
1602
1603 static const struct of_device_id fsl_sata_match[] = {
1604 {
1605 .compatible = "fsl,pq-sata",
1606 },
1607 {
1608 .compatible = "fsl,pq-sata-v2",
1609 },
1610 {},
1611 };
1612
1613 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1614
1615 static struct platform_driver fsl_sata_driver = {
1616 .driver = {
1617 .name = "fsl-sata",
1618 .of_match_table = fsl_sata_match,
1619 },
1620 .probe = sata_fsl_probe,
1621 .remove = sata_fsl_remove,
1622 #ifdef CONFIG_PM_SLEEP
1623 .suspend = sata_fsl_suspend,
1624 .resume = sata_fsl_resume,
1625 #endif
1626 };
1627
1628 module_platform_driver(fsl_sata_driver);
1629
1630 MODULE_LICENSE("GPL");
1631 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1632 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1633 MODULE_VERSION("1.10");
connection oriented routing