drivers/clk/davinci/pll-dm355.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * PLL clock descriptions for TI DM355
   4  *
   5  * Copyright (C) 2018 David Lechner <david@lechnology.com>
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/clk/davinci.h>
  10 #include <linux/clkdev.h>
  11 #include <linux/init.h>
  12 #include <linux/types.h>
  13
  14 #include "pll.h"
  15
  16 static const struct davinci_pll_clk_info dm355_pll1_info = {
  17         .name = "pll1",
  18         .pllm_mask = GENMASK(7, 0),
  19         .pllm_min = 92,
  20         .pllm_max = 184,
  21         .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED |
  22                  PLL_PREDIV_FIXED8 | PLL_HAS_POSTDIV |
  23                  PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  24 };
  25
  26 SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  27 SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  28 SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  29 SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
  30
  31 int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  32 {
  33         struct clk *clk;
  34
  35         davinci_pll_clk_register(dev, &dm355_pll1_info, "ref_clk", base, cfgchip);
  36
  37         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
  38         clk_register_clkdev(clk, "pll1_sysclk1", "dm355-psc");
  39
  40         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
  41         clk_register_clkdev(clk, "pll1_sysclk2", "dm355-psc");
  42
  43         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
  44         clk_register_clkdev(clk, "pll1_sysclk3", "dm355-psc");
  45
  46         clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
  47         clk_register_clkdev(clk, "pll1_sysclk4", "dm355-psc");
  48
  49         clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
  50         clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
  51
  52         davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
  53
  54         return 0;
  55 }
  56
  57 static const struct davinci_pll_clk_info dm355_pll2_info = {
  58         .name = "pll2",
  59         .pllm_mask = GENMASK(7, 0),
  60         .pllm_min = 92,
  61         .pllm_max = 184,
  62         .flags = PLL_HAS_PREDIV | PLL_PREDIV_ALWAYS_ENABLED | PLL_HAS_POSTDIV |
  63                  PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
  64 };
  65
  66 SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
  67
  68 int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
  69 {
  70         davinci_pll_clk_register(dev, &dm355_pll2_info, "oscin", base, cfgchip);
  71
  72         davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
  73
  74         davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
  75
  76         return 0;
  77 }