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[cor.git] / drivers / clk / clk-si5341.c
blob6e780c2a9e6ba4290cf8bce60936c5a943d4e1e4
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Silicon Labs Si5341/Si5340 Clock generator
4 * Copyright (C) 2019 Topic Embedded Products
5 * Author: Mike Looijmans <mike.looijmans@topic.nl>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/gcd.h>
12 #include <linux/math64.h>
13 #include <linux/i2c.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <asm/unaligned.h>
18
19 #define SI5341_MAX_NUM_OUTPUTS 10
20 #define SI5340_MAX_NUM_OUTPUTS 4
21
22 #define SI5341_NUM_SYNTH 5
23 #define SI5340_NUM_SYNTH 4
24
25 /* Range of the synthesizer fractional divider */
26 #define SI5341_SYNTH_N_MIN 10
27 #define SI5341_SYNTH_N_MAX 4095
28
29 /* The chip can get its input clock from 3 input pins or an XTAL */
30
31 /* There is one PLL running at 13500–14256 MHz */
32 #define SI5341_PLL_VCO_MIN 13500000000ull
33 #define SI5341_PLL_VCO_MAX 14256000000ull
34
35 /* The 5 frequency synthesizers obtain their input from the PLL */
36 struct clk_si5341_synth {
37 struct clk_hw hw;
38 struct clk_si5341 *data;
39 u8 index;
40 };
41 #define to_clk_si5341_synth(_hw) \
42 container_of(_hw, struct clk_si5341_synth, hw)
43
44 /* The output stages can be connected to any synth (full mux) */
45 struct clk_si5341_output {
46 struct clk_hw hw;
47 struct clk_si5341 *data;
48 u8 index;
49 };
50 #define to_clk_si5341_output(_hw) \
51 container_of(_hw, struct clk_si5341_output, hw)
52
53 struct clk_si5341 {
54 struct clk_hw hw;
55 struct regmap *regmap;
56 struct i2c_client *i2c_client;
57 struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
58 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
59 struct clk *pxtal;
60 const char *pxtal_name;
61 const u16 *reg_output_offset;
62 const u16 *reg_rdiv_offset;
63 u64 freq_vco; /* 13500–14256 MHz */
64 u8 num_outputs;
65 u8 num_synth;
66 };
67 #define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
68
69 struct clk_si5341_output_config {
70 u8 out_format_drv_bits;
71 u8 out_cm_ampl_bits;
72 bool synth_master;
73 bool always_on;
74 };
75
76 #define SI5341_PAGE 0x0001
77 #define SI5341_PN_BASE 0x0002
78 #define SI5341_DEVICE_REV 0x0005
79 #define SI5341_STATUS 0x000C
80 #define SI5341_SOFT_RST 0x001C
81
82 /* Input dividers (48-bit) */
83 #define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
84 #define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
85
86 /* PLL configuration */
87 #define SI5341_PLL_M_NUM 0x0235
88 #define SI5341_PLL_M_DEN 0x023B
89
90 /* Output configuration */
91 #define SI5341_OUT_CONFIG(output) \
92 ((output)->data->reg_output_offset[(output)->index])
93 #define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
94 #define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
95 #define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
96 #define SI5341_OUT_R_REG(output) \
97 ((output)->data->reg_rdiv_offset[(output)->index])
98
99 /* Synthesize N divider */
100 #define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
101 #define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
102 #define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
103
104 /* Synthesizer output enable, phase bypass, power mode */
105 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
106 #define SI5341_SYNTH_N_PIBYP 0x0A04
107 #define SI5341_SYNTH_N_PDNB 0x0A05
108 #define SI5341_SYNTH_N_CLK_DIS 0x0B4A
109
110 #define SI5341_REGISTER_MAX 0xBFF
111
112 /* SI5341_OUT_CONFIG bits */
113 #define SI5341_OUT_CFG_PDN BIT(0)
114 #define SI5341_OUT_CFG_OE BIT(1)
115 #define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
116
117 /* Static configuration (to be moved to firmware) */
118 struct si5341_reg_default {
119 u16 address;
120 u8 value;
121 };
122
123 /* Output configuration registers 0..9 are not quite logically organized */
124 static const u16 si5341_reg_output_offset[] = {
125 0x0108,
126 0x010D,
127 0x0112,
128 0x0117,
129 0x011C,
130 0x0121,
131 0x0126,
132 0x012B,
133 0x0130,
134 0x013A,
135 };
136
137 static const u16 si5340_reg_output_offset[] = {
138 0x0112,
139 0x0117,
140 0x0126,
141 0x012B,
142 };
143
144 /* The location of the R divider registers */
145 static const u16 si5341_reg_rdiv_offset[] = {
146 0x024A,
147 0x024D,
148 0x0250,
149 0x0253,
150 0x0256,
151 0x0259,
152 0x025C,
153 0x025F,
154 0x0262,
155 0x0268,
156 };
157 static const u16 si5340_reg_rdiv_offset[] = {
158 0x0250,
159 0x0253,
160 0x025C,
161 0x025F,
162 };
163
164 /*
165 * Programming sequence from ClockBuilder, settings to initialize the system
166 * using only the XTAL input, without pre-divider.
167 * This also contains settings that aren't mentioned anywhere in the datasheet.
168 * The "known" settings like synth and output configuration are done later.
169 */
170 static const struct si5341_reg_default si5341_reg_defaults[] = {
171 { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
172 { 0x0018, 0xFF }, /* INT mask */
173 { 0x0021, 0x0F }, /* Select XTAL as input */
174 { 0x0022, 0x00 }, /* Not in datasheet */
175 { 0x002B, 0x02 }, /* SPI config */
176 { 0x002C, 0x20 }, /* LOS enable for XTAL */
177 { 0x002D, 0x00 }, /* LOS timing */
178 { 0x002E, 0x00 },
179 { 0x002F, 0x00 },
180 { 0x0030, 0x00 },
181 { 0x0031, 0x00 },
182 { 0x0032, 0x00 },
183 { 0x0033, 0x00 },
184 { 0x0034, 0x00 },
185 { 0x0035, 0x00 },
186 { 0x0036, 0x00 },
187 { 0x0037, 0x00 },
188 { 0x0038, 0x00 }, /* LOS setting (thresholds) */
189 { 0x0039, 0x00 },
190 { 0x003A, 0x00 },
191 { 0x003B, 0x00 },
192 { 0x003C, 0x00 },
193 { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
194 { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
195 { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
196 { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
197 { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
198 { 0x009E, 0x00 }, /* Not in datasheet */
199 { 0x0102, 0x01 }, /* Enable outputs */
200 { 0x013F, 0x00 }, /* Not in datasheet */
201 { 0x0140, 0x00 }, /* Not in datasheet */
202 { 0x0141, 0x40 }, /* OUT LOS */
203 { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
204 { 0x0203, 0x00 },
205 { 0x0204, 0x00 },
206 { 0x0205, 0x00 },
207 { 0x0206, 0x00 }, /* PXAXB (2^x) */
208 { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
209 { 0x0209, 0x00 },
210 { 0x020A, 0x00 },
211 { 0x020B, 0x00 },
212 { 0x020C, 0x00 },
213 { 0x020D, 0x00 },
214 { 0x020E, 0x00 },
215 { 0x020F, 0x00 },
216 { 0x0210, 0x00 },
217 { 0x0211, 0x00 },
218 { 0x0212, 0x00 },
219 { 0x0213, 0x00 },
220 { 0x0214, 0x00 },
221 { 0x0215, 0x00 },
222 { 0x0216, 0x00 },
223 { 0x0217, 0x00 },
224 { 0x0218, 0x00 },
225 { 0x0219, 0x00 },
226 { 0x021A, 0x00 },
227 { 0x021B, 0x00 },
228 { 0x021C, 0x00 },
229 { 0x021D, 0x00 },
230 { 0x021E, 0x00 },
231 { 0x021F, 0x00 },
232 { 0x0220, 0x00 },
233 { 0x0221, 0x00 },
234 { 0x0222, 0x00 },
235 { 0x0223, 0x00 },
236 { 0x0224, 0x00 },
237 { 0x0225, 0x00 },
238 { 0x0226, 0x00 },
239 { 0x0227, 0x00 },
240 { 0x0228, 0x00 },
241 { 0x0229, 0x00 },
242 { 0x022A, 0x00 },
243 { 0x022B, 0x00 },
244 { 0x022C, 0x00 },
245 { 0x022D, 0x00 },
246 { 0x022E, 0x00 },
247 { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
248 { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
249 { 0x026C, 0x00 },
250 { 0x026D, 0x00 },
251 { 0x026E, 0x00 },
252 { 0x026F, 0x00 },
253 { 0x0270, 0x00 },
254 { 0x0271, 0x00 },
255 { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
256 { 0x0339, 0x1F }, /* N_FSTEP_MSK */
257 { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
258 { 0x033C, 0x00 },
259 { 0x033D, 0x00 },
260 { 0x033E, 0x00 },
261 { 0x033F, 0x00 },
262 { 0x0340, 0x00 },
263 { 0x0341, 0x00 },
264 { 0x0342, 0x00 },
265 { 0x0343, 0x00 },
266 { 0x0344, 0x00 },
267 { 0x0345, 0x00 },
268 { 0x0346, 0x00 },
269 { 0x0347, 0x00 },
270 { 0x0348, 0x00 },
271 { 0x0349, 0x00 },
272 { 0x034A, 0x00 },
273 { 0x034B, 0x00 },
274 { 0x034C, 0x00 },
275 { 0x034D, 0x00 },
276 { 0x034E, 0x00 },
277 { 0x034F, 0x00 },
278 { 0x0350, 0x00 },
279 { 0x0351, 0x00 },
280 { 0x0352, 0x00 },
281 { 0x0353, 0x00 },
282 { 0x0354, 0x00 },
283 { 0x0355, 0x00 },
284 { 0x0356, 0x00 },
285 { 0x0357, 0x00 },
286 { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
287 { 0x0359, 0x00 }, /* Nx_DELAY */
288 { 0x035A, 0x00 },
289 { 0x035B, 0x00 },
290 { 0x035C, 0x00 },
291 { 0x035D, 0x00 },
292 { 0x035E, 0x00 },
293 { 0x035F, 0x00 },
294 { 0x0360, 0x00 },
295 { 0x0361, 0x00 },
296 { 0x0362, 0x00 }, /* Nx_DELAY end */
297 { 0x0802, 0x00 }, /* Not in datasheet */
298 { 0x0803, 0x00 }, /* Not in datasheet */
299 { 0x0804, 0x00 }, /* Not in datasheet */
300 { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
301 { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
302 { 0x0943, 0x00 }, /* IO_VDD_SEL=0 (0=1v8, use 1=3v3) */
303 { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
304 { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
305 { 0x0A02, 0x00 }, /* Not in datasheet */
306 { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
307 };
308
309 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
310 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
311 u64 *val1, u32 *val2)
312 {
313 int err;
314 u8 r[10];
315
316 err = regmap_bulk_read(regmap, reg, r, 10);
317 if (err < 0)
318 return err;
319
320 *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
321 (get_unaligned_le32(r));
322 *val2 = get_unaligned_le32(&r[6]);
323
324 return 0;
325 }
326
327 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
328 u64 n_num, u32 n_den)
329 {
330 u8 r[10];
331
332 /* Shift left as far as possible without overflowing */
333 while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
334 n_num <<= 1;
335 n_den <<= 1;
336 }
337
338 /* 44 bits (6 bytes) numerator */
339 put_unaligned_le32(n_num, r);
340 r[4] = (n_num >> 32) & 0xff;
341 r[5] = (n_num >> 40) & 0x0f;
342 /* 32 bits denominator */
343 put_unaligned_le32(n_den, &r[6]);
344
345 /* Program the fraction */
346 return regmap_bulk_write(regmap, reg, r, sizeof(r));
347 }
348
349 /* VCO, we assume it runs at a constant frequency */
350 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
351 unsigned long parent_rate)
352 {
353 struct clk_si5341 *data = to_clk_si5341(hw);
354 int err;
355 u64 res;
356 u64 m_num;
357 u32 m_den;
358 unsigned int shift;
359
360 /* Assume that PDIV is not being used, just read the PLL setting */
361 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
362 &m_num, &m_den);
363 if (err < 0)
364 return 0;
365
366 if (!m_num || !m_den)
367 return 0;
368
369 /*
370 * Though m_num is 64-bit, only the upper bits are actually used. While
371 * calculating m_num and m_den, they are shifted as far as possible to
372 * the left. To avoid 96-bit division here, we just shift them back so
373 * we can do with just 64 bits.
374 */
375 shift = 0;
376 res = m_num;
377 while (res & 0xffff00000000ULL) {
378 ++shift;
379 res >>= 1;
380 }
381 res *= parent_rate;
382 do_div(res, (m_den >> shift));
383
384 /* We cannot return the actual frequency in 32 bit, store it locally */
385 data->freq_vco = res;
386
387 /* Report kHz since the value is out of range */
388 do_div(res, 1000);
389
390 return (unsigned long)res;
391 }
392
393 static const struct clk_ops si5341_clk_ops = {
394 .recalc_rate = si5341_clk_recalc_rate,
395 };
396
397 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
398
399 /* The synthesizer is on if all power and enable bits are set */
400 static int si5341_synth_clk_is_on(struct clk_hw *hw)
401 {
402 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
403 int err;
404 u32 val;
405 u8 index = synth->index;
406
407 err = regmap_read(synth->data->regmap,
408 SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
409 if (err < 0)
410 return 0;
411
412 if (!(val & BIT(index)))
413 return 0;
414
415 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
416 if (err < 0)
417 return 0;
418
419 if (!(val & BIT(index)))
420 return 0;
421
422 /* This bit must be 0 for the synthesizer to receive clock input */
423 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
424 if (err < 0)
425 return 0;
426
427 return !(val & BIT(index));
428 }
429
430 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
431 {
432 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
433 u8 index = synth->index; /* In range 0..5 */
434 u8 mask = BIT(index);
435
436 /* Disable output */
437 regmap_update_bits(synth->data->regmap,
438 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
439 /* Power down */
440 regmap_update_bits(synth->data->regmap,
441 SI5341_SYNTH_N_PDNB, mask, 0);
442 /* Disable clock input to synth (set to 1 to disable) */
443 regmap_update_bits(synth->data->regmap,
444 SI5341_SYNTH_N_CLK_DIS, mask, mask);
445 }
446
447 static int si5341_synth_clk_prepare(struct clk_hw *hw)
448 {
449 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
450 int err;
451 u8 index = synth->index;
452 u8 mask = BIT(index);
453
454 /* Power up */
455 err = regmap_update_bits(synth->data->regmap,
456 SI5341_SYNTH_N_PDNB, mask, mask);
457 if (err < 0)
458 return err;
459
460 /* Enable clock input to synth (set bit to 0 to enable) */
461 err = regmap_update_bits(synth->data->regmap,
462 SI5341_SYNTH_N_CLK_DIS, mask, 0);
463 if (err < 0)
464 return err;
465
466 /* Enable output */
467 return regmap_update_bits(synth->data->regmap,
468 SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
469 }
470
471 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
472 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
473 unsigned long parent_rate)
474 {
475 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
476 u64 f;
477 u64 n_num;
478 u32 n_den;
479 int err;
480
481 err = si5341_decode_44_32(synth->data->regmap,
482 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
483 if (err < 0)
484 return err;
485
486 /*
487 * n_num and n_den are shifted left as much as possible, so to prevent
488 * overflow in 64-bit math, we shift n_den 4 bits to the right
489 */
490 f = synth->data->freq_vco;
491 f *= n_den >> 4;
492
493 /* Now we need to to 64-bit division: f/n_num */
494 /* And compensate for the 4 bits we dropped */
495 f = div64_u64(f, (n_num >> 4));
496
497 return f;
498 }
499
500 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
501 unsigned long *parent_rate)
502 {
503 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
504 u64 f;
505
506 /* The synthesizer accuracy is such that anything in range will work */
507 f = synth->data->freq_vco;
508 do_div(f, SI5341_SYNTH_N_MAX);
509 if (rate < f)
510 return f;
511
512 f = synth->data->freq_vco;
513 do_div(f, SI5341_SYNTH_N_MIN);
514 if (rate > f)
515 return f;
516
517 return rate;
518 }
519
520 static int si5341_synth_program(struct clk_si5341_synth *synth,
521 u64 n_num, u32 n_den, bool is_integer)
522 {
523 int err;
524 u8 index = synth->index;
525
526 err = si5341_encode_44_32(synth->data->regmap,
527 SI5341_SYNTH_N_NUM(index), n_num, n_den);
528
529 err = regmap_update_bits(synth->data->regmap,
530 SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
531 if (err < 0)
532 return err;
533
534 return regmap_write(synth->data->regmap,
535 SI5341_SYNTH_N_UPD(index), 0x01);
536 }
537
538
539 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
540 unsigned long parent_rate)
541 {
542 struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
543 u64 n_num;
544 u32 n_den;
545 u32 r;
546 u32 g;
547 bool is_integer;
548
549 n_num = synth->data->freq_vco;
550
551 /* see if there's an integer solution */
552 r = do_div(n_num, rate);
553 is_integer = (r == 0);
554 if (is_integer) {
555 /* Integer divider equal to n_num */
556 n_den = 1;
557 } else {
558 /* Calculate a fractional solution */
559 g = gcd(r, rate);
560 n_den = rate / g;
561 n_num *= n_den;
562 n_num += r / g;
563 }
564
565 dev_dbg(&synth->data->i2c_client->dev,
566 "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
567 synth->index, n_num, n_den,
568 is_integer ? "int" : "frac");
569
570 return si5341_synth_program(synth, n_num, n_den, is_integer);
571 }
572
573 static const struct clk_ops si5341_synth_clk_ops = {
574 .is_prepared = si5341_synth_clk_is_on,
575 .prepare = si5341_synth_clk_prepare,
576 .unprepare = si5341_synth_clk_unprepare,
577 .recalc_rate = si5341_synth_clk_recalc_rate,
578 .round_rate = si5341_synth_clk_round_rate,
579 .set_rate = si5341_synth_clk_set_rate,
580 };
581
582 static int si5341_output_clk_is_on(struct clk_hw *hw)
583 {
584 struct clk_si5341_output *output = to_clk_si5341_output(hw);
585 int err;
586 u32 val;
587
588 err = regmap_read(output->data->regmap,
589 SI5341_OUT_CONFIG(output), &val);
590 if (err < 0)
591 return err;
592
593 /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
594 return (val & 0x03) == SI5341_OUT_CFG_OE;
595 }
596
597 /* Disables and then powers down the output */
598 static void si5341_output_clk_unprepare(struct clk_hw *hw)
599 {
600 struct clk_si5341_output *output = to_clk_si5341_output(hw);
601
602 regmap_update_bits(output->data->regmap,
603 SI5341_OUT_CONFIG(output),
604 SI5341_OUT_CFG_OE, 0);
605 regmap_update_bits(output->data->regmap,
606 SI5341_OUT_CONFIG(output),
607 SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
608 }
609
610 /* Powers up and then enables the output */
611 static int si5341_output_clk_prepare(struct clk_hw *hw)
612 {
613 struct clk_si5341_output *output = to_clk_si5341_output(hw);
614 int err;
615
616 err = regmap_update_bits(output->data->regmap,
617 SI5341_OUT_CONFIG(output),
618 SI5341_OUT_CFG_PDN, 0);
619 if (err < 0)
620 return err;
621
622 return regmap_update_bits(output->data->regmap,
623 SI5341_OUT_CONFIG(output),
624 SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
625 }
626
627 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
628 unsigned long parent_rate)
629 {
630 struct clk_si5341_output *output = to_clk_si5341_output(hw);
631 int err;
632 u32 val;
633 u32 r_divider;
634 u8 r[3];
635
636 err = regmap_bulk_read(output->data->regmap,
637 SI5341_OUT_R_REG(output), r, 3);
638 if (err < 0)
639 return err;
640
641 /* Calculate value as 24-bit integer*/
642 r_divider = r[2] << 16 | r[1] << 8 | r[0];
643
644 /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
645 if (!r_divider)
646 return 0;
647
648 /* Divider is 2*(Rx_REG+1) */
649 r_divider += 1;
650 r_divider <<= 1;
651
652 err = regmap_read(output->data->regmap,
653 SI5341_OUT_CONFIG(output), &val);
654 if (err < 0)
655 return err;
656
657 if (val & SI5341_OUT_CFG_RDIV_FORCE2)
658 r_divider = 2;
659
660 return parent_rate / r_divider;
661 }
662
663 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
664 unsigned long *parent_rate)
665 {
666 unsigned long r;
667
668 r = *parent_rate >> 1;
669
670 /* If rate is an even divisor, no changes to parent required */
671 if (r && !(r % rate))
672 return (long)rate;
673
674 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
675 if (rate > 200000000) {
676 /* minimum r-divider is 2 */
677 r = 2;
678 } else {
679 /* Take a parent frequency near 400 MHz */
680 r = (400000000u / rate) & ~1;
681 }
682 *parent_rate = r * rate;
683 } else {
684 /* We cannot change our parent's rate, report what we can do */
685 r /= rate;
686 rate = *parent_rate / (r << 1);
687 }
688
689 return rate;
690 }
691
692 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
693 unsigned long parent_rate)
694 {
695 struct clk_si5341_output *output = to_clk_si5341_output(hw);
696 /* Frequency divider is (r_div + 1) * 2 */
697 u32 r_div = (parent_rate / rate) >> 1;
698 int err;
699 u8 r[3];
700
701 if (r_div <= 1)
702 r_div = 0;
703 else if (r_div >= BIT(24))
704 r_div = BIT(24) - 1;
705 else
706 --r_div;
707
708 /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
709 err = regmap_update_bits(output->data->regmap,
710 SI5341_OUT_CONFIG(output),
711 SI5341_OUT_CFG_RDIV_FORCE2,
712 (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
713 if (err < 0)
714 return err;
715
716 /* Always write Rx_REG, because a zero value disables the divider */
717 r[0] = r_div ? (r_div & 0xff) : 1;
718 r[1] = (r_div >> 8) & 0xff;
719 r[2] = (r_div >> 16) & 0xff;
720 err = regmap_bulk_write(output->data->regmap,
721 SI5341_OUT_R_REG(output), r, 3);
722
723 return 0;
724 }
725
726 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
727 {
728 return regmap_update_bits(output->data->regmap,
729 SI5341_OUT_MUX_SEL(output), 0x07, index);
730 }
731
732 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
733 {
734 struct clk_si5341_output *output = to_clk_si5341_output(hw);
735
736 if (index >= output->data->num_synth)
737 return -EINVAL;
738
739 return si5341_output_reparent(output, index);
740 }
741
742 static u8 si5341_output_get_parent(struct clk_hw *hw)
743 {
744 struct clk_si5341_output *output = to_clk_si5341_output(hw);
745 int err;
746 u32 val;
747
748 err = regmap_read(output->data->regmap,
749 SI5341_OUT_MUX_SEL(output), &val);
750
751 return val & 0x7;
752 }
753
754 static const struct clk_ops si5341_output_clk_ops = {
755 .is_prepared = si5341_output_clk_is_on,
756 .prepare = si5341_output_clk_prepare,
757 .unprepare = si5341_output_clk_unprepare,
758 .recalc_rate = si5341_output_clk_recalc_rate,
759 .round_rate = si5341_output_clk_round_rate,
760 .set_rate = si5341_output_clk_set_rate,
761 .set_parent = si5341_output_set_parent,
762 .get_parent = si5341_output_get_parent,
763 };
764
765 /*
766 * The chip can be bought in a pre-programmed version, or one can program the
767 * NVM in the chip to boot up in a preset mode. This routine tries to determine
768 * if that's the case, or if we need to reset and program everything from
769 * scratch. Returns negative error, or true/false.
770 */
771 static int si5341_is_programmed_already(struct clk_si5341 *data)
772 {
773 int err;
774 u8 r[4];
775
776 /* Read the PLL divider value, it must have a non-zero value */
777 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
778 r, ARRAY_SIZE(r));
779 if (err < 0)
780 return err;
781
782 return !!get_unaligned_le32(r);
783 }
784
785 static struct clk_hw *
786 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
787 {
788 struct clk_si5341 *data = _data;
789 unsigned int idx = clkspec->args[1];
790 unsigned int group = clkspec->args[0];
791
792 switch (group) {
793 case 0:
794 if (idx >= data->num_outputs) {
795 dev_err(&data->i2c_client->dev,
796 "invalid output index %u\n", idx);
797 return ERR_PTR(-EINVAL);
798 }
799 return &data->clk[idx].hw;
800 case 1:
801 if (idx >= data->num_synth) {
802 dev_err(&data->i2c_client->dev,
803 "invalid synthesizer index %u\n", idx);
804 return ERR_PTR(-EINVAL);
805 }
806 return &data->synth[idx].hw;
807 case 2:
808 if (idx > 0) {
809 dev_err(&data->i2c_client->dev,
810 "invalid PLL index %u\n", idx);
811 return ERR_PTR(-EINVAL);
812 }
813 return &data->hw;
814 default:
815 dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
816 return ERR_PTR(-EINVAL);
817 }
818 }
819
820 static int si5341_probe_chip_id(struct clk_si5341 *data)
821 {
822 int err;
823 u8 reg[4];
824 u16 model;
825
826 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
827 ARRAY_SIZE(reg));
828 if (err < 0) {
829 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
830 return err;
831 }
832
833 model = get_unaligned_le16(reg);
834
835 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
836 model, reg[2], reg[3]);
837
838 switch (model) {
839 case 0x5340:
840 data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
841 data->num_synth = SI5340_NUM_SYNTH;
842 data->reg_output_offset = si5340_reg_output_offset;
843 data->reg_rdiv_offset = si5340_reg_rdiv_offset;
844 break;
845 case 0x5341:
846 data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
847 data->num_synth = SI5341_NUM_SYNTH;
848 data->reg_output_offset = si5341_reg_output_offset;
849 data->reg_rdiv_offset = si5341_reg_rdiv_offset;
850 break;
851 default:
852 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
853 model);
854 return -EINVAL;
855 }
856
857 return 0;
858 }
859
860 /* Read active settings into the regmap cache for later reference */
861 static int si5341_read_settings(struct clk_si5341 *data)
862 {
863 int err;
864 u8 i;
865 u8 r[10];
866
867 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
868 if (err < 0)
869 return err;
870
871 err = regmap_bulk_read(data->regmap,
872 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
873 if (err < 0)
874 return err;
875
876 err = regmap_bulk_read(data->regmap,
877 SI5341_SYNTH_N_CLK_DIS, r, 1);
878 if (err < 0)
879 return err;
880
881 for (i = 0; i < data->num_synth; ++i) {
882 err = regmap_bulk_read(data->regmap,
883 SI5341_SYNTH_N_NUM(i), r, 10);
884 if (err < 0)
885 return err;
886 }
887
888 for (i = 0; i < data->num_outputs; ++i) {
889 err = regmap_bulk_read(data->regmap,
890 data->reg_output_offset[i], r, 4);
891 if (err < 0)
892 return err;
893
894 err = regmap_bulk_read(data->regmap,
895 data->reg_rdiv_offset[i], r, 3);
896 if (err < 0)
897 return err;
898 }
899
900 return 0;
901 }
902
903 static int si5341_write_multiple(struct clk_si5341 *data,
904 const struct si5341_reg_default *values, unsigned int num_values)
905 {
906 unsigned int i;
907 int res;
908
909 for (i = 0; i < num_values; ++i) {
910 res = regmap_write(data->regmap,
911 values[i].address, values[i].value);
912 if (res < 0) {
913 dev_err(&data->i2c_client->dev,
914 "Failed to write %#x:%#x\n",
915 values[i].address, values[i].value);
916 return res;
917 }
918 }
919
920 return 0;
921 }
922
923 static const struct si5341_reg_default si5341_preamble[] = {
924 { 0x0B25, 0x00 },
925 { 0x0502, 0x01 },
926 { 0x0505, 0x03 },
927 { 0x0957, 0x1F },
928 { 0x0B4E, 0x1A },
929 };
930
931 static int si5341_send_preamble(struct clk_si5341 *data)
932 {
933 int res;
934 u32 revision;
935
936 /* For revision 2 and up, the values are slightly different */
937 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
938 if (res < 0)
939 return res;
940
941 /* Write "preamble" as specified by datasheet */
942 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
943 if (res < 0)
944 return res;
945 res = si5341_write_multiple(data,
946 si5341_preamble, ARRAY_SIZE(si5341_preamble));
947 if (res < 0)
948 return res;
949
950 /* Datasheet specifies a 300ms wait after sending the preamble */
951 msleep(300);
952
953 return 0;
954 }
955
956 /* Perform a soft reset and write post-amble */
957 static int si5341_finalize_defaults(struct clk_si5341 *data)
958 {
959 int res;
960 u32 revision;
961
962 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
963 if (res < 0)
964 return res;
965
966 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
967
968 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
969 if (res < 0)
970 return res;
971
972 /* Datasheet does not explain these nameless registers */
973 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
974 if (res < 0)
975 return res;
976 res = regmap_write(data->regmap, 0x0B25, 0x02);
977 if (res < 0)
978 return res;
979
980 return 0;
981 }
982
983
984 static const struct regmap_range si5341_regmap_volatile_range[] = {
985 regmap_reg_range(0x000C, 0x0012), /* Status */
986 regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
987 regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
988 /* Update bits for synth config */
989 regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
990 regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
991 regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
992 regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
993 regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
994 };
995
996 static const struct regmap_access_table si5341_regmap_volatile = {
997 .yes_ranges = si5341_regmap_volatile_range,
998 .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
999 };
1000
1001 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1002 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1003 {
1004 .range_min = 0,
1005 .range_max = SI5341_REGISTER_MAX,
1006 .selector_reg = SI5341_PAGE,
1007 .selector_mask = 0xff,
1008 .selector_shift = 0,
1009 .window_start = 0,
1010 .window_len = 256,
1011 },
1012 };
1013
1014 static const struct regmap_config si5341_regmap_config = {
1015 .reg_bits = 8,
1016 .val_bits = 8,
1017 .cache_type = REGCACHE_RBTREE,
1018 .ranges = si5341_regmap_ranges,
1019 .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1020 .max_register = SI5341_REGISTER_MAX,
1021 .volatile_table = &si5341_regmap_volatile,
1022 };
1023
1024 static int si5341_dt_parse_dt(struct i2c_client *client,
1025 struct clk_si5341_output_config *config)
1026 {
1027 struct device_node *child;
1028 struct device_node *np = client->dev.of_node;
1029 u32 num;
1030 u32 val;
1031
1032 memset(config, 0, sizeof(struct clk_si5341_output_config) *
1033 SI5341_MAX_NUM_OUTPUTS);
1034
1035 for_each_child_of_node(np, child) {
1036 if (of_property_read_u32(child, "reg", &num)) {
1037 dev_err(&client->dev, "missing reg property of %s\n",
1038 child->name);
1039 goto put_child;
1040 }
1041
1042 if (num >= SI5341_MAX_NUM_OUTPUTS) {
1043 dev_err(&client->dev, "invalid clkout %d\n", num);
1044 goto put_child;
1045 }
1046
1047 if (!of_property_read_u32(child, "silabs,format", &val)) {
1048 /* Set cm and ampl conservatively to 3v3 settings */
1049 switch (val) {
1050 case 1: /* normal differential */
1051 config[num].out_cm_ampl_bits = 0x33;
1052 break;
1053 case 2: /* low-power differential */
1054 config[num].out_cm_ampl_bits = 0x13;
1055 break;
1056 case 4: /* LVCMOS */
1057 config[num].out_cm_ampl_bits = 0x33;
1058 /* Set SI recommended impedance for LVCMOS */
1059 config[num].out_format_drv_bits |= 0xc0;
1060 break;
1061 default:
1062 dev_err(&client->dev,
1063 "invalid silabs,format %u for %u\n",
1064 val, num);
1065 goto put_child;
1066 }
1067 config[num].out_format_drv_bits &= ~0x07;
1068 config[num].out_format_drv_bits |= val & 0x07;
1069 /* Always enable the SYNC feature */
1070 config[num].out_format_drv_bits |= 0x08;
1071 }
1072
1073 if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1074 if (val > 0xf) {
1075 dev_err(&client->dev,
1076 "invalid silabs,common-mode %u\n",
1077 val);
1078 goto put_child;
1079 }
1080 config[num].out_cm_ampl_bits &= 0xf0;
1081 config[num].out_cm_ampl_bits |= val & 0x0f;
1082 }
1083
1084 if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1085 if (val > 0xf) {
1086 dev_err(&client->dev,
1087 "invalid silabs,amplitude %u\n",
1088 val);
1089 goto put_child;
1090 }
1091 config[num].out_cm_ampl_bits &= 0x0f;
1092 config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1093 }
1094
1095 if (of_property_read_bool(child, "silabs,disable-high"))
1096 config[num].out_format_drv_bits |= 0x10;
1097
1098 config[num].synth_master =
1099 of_property_read_bool(child, "silabs,synth-master");
1100
1101 config[num].always_on =
1102 of_property_read_bool(child, "always-on");
1103 }
1104
1105 return 0;
1106
1107 put_child:
1108 of_node_put(child);
1109 return -EINVAL;
1110 }
1111
1112 /*
1113 * If not pre-configured, calculate and set the PLL configuration manually.
1114 * For low-jitter performance, the PLL should be set such that the synthesizers
1115 * only need integer division.
1116 * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1117 * the chip to generate any frequency on its outputs, but jitter performance
1118 * may be sub-optimal.
1119 */
1120 static int si5341_initialize_pll(struct clk_si5341 *data)
1121 {
1122 struct device_node *np = data->i2c_client->dev.of_node;
1123 u32 m_num = 0;
1124 u32 m_den = 0;
1125
1126 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1127 dev_err(&data->i2c_client->dev,
1128 "PLL configuration requires silabs,pll-m-num\n");
1129 }
1130 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1131 dev_err(&data->i2c_client->dev,
1132 "PLL configuration requires silabs,pll-m-den\n");
1133 }
1134
1135 if (!m_num || !m_den) {
1136 dev_err(&data->i2c_client->dev,
1137 "PLL configuration invalid, assume 14GHz\n");
1138 m_den = clk_get_rate(data->pxtal) / 10;
1139 m_num = 1400000000;
1140 }
1141
1142 return si5341_encode_44_32(data->regmap,
1143 SI5341_PLL_M_NUM, m_num, m_den);
1144 }
1145
1146 static int si5341_probe(struct i2c_client *client,
1147 const struct i2c_device_id *id)
1148 {
1149 struct clk_si5341 *data;
1150 struct clk_init_data init;
1151 const char *root_clock_name;
1152 const char *synth_clock_names[SI5341_NUM_SYNTH];
1153 int err;
1154 unsigned int i;
1155 struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1156 bool initialization_required;
1157
1158 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1159 if (!data)
1160 return -ENOMEM;
1161
1162 data->i2c_client = client;
1163
1164 data->pxtal = devm_clk_get(&client->dev, "xtal");
1165 if (IS_ERR(data->pxtal)) {
1166 if (PTR_ERR(data->pxtal) == -EPROBE_DEFER)
1167 return -EPROBE_DEFER;
1168
1169 dev_err(&client->dev, "Missing xtal clock input\n");
1170 }
1171
1172 err = si5341_dt_parse_dt(client, config);
1173 if (err)
1174 return err;
1175
1176 if (of_property_read_string(client->dev.of_node, "clock-output-names",
1177 &init.name))
1178 init.name = client->dev.of_node->name;
1179 root_clock_name = init.name;
1180
1181 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1182 if (IS_ERR(data->regmap))
1183 return PTR_ERR(data->regmap);
1184
1185 i2c_set_clientdata(client, data);
1186
1187 err = si5341_probe_chip_id(data);
1188 if (err < 0)
1189 return err;
1190
1191 /* "Activate" the xtal (usually a fixed clock) */
1192 clk_prepare_enable(data->pxtal);
1193
1194 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1195 initialization_required = true;
1196 } else {
1197 err = si5341_is_programmed_already(data);
1198 if (err < 0)
1199 return err;
1200
1201 initialization_required = !err;
1202 }
1203
1204 if (initialization_required) {
1205 /* Populate the regmap cache in preparation for "cache only" */
1206 err = si5341_read_settings(data);
1207 if (err < 0)
1208 return err;
1209
1210 err = si5341_send_preamble(data);
1211 if (err < 0)
1212 return err;
1213
1214 /*
1215 * We intend to send all 'final' register values in a single
1216 * transaction. So cache all register writes until we're done
1217 * configuring.
1218 */
1219 regcache_cache_only(data->regmap, true);
1220
1221 /* Write the configuration pairs from the firmware blob */
1222 err = si5341_write_multiple(data, si5341_reg_defaults,
1223 ARRAY_SIZE(si5341_reg_defaults));
1224 if (err < 0)
1225 return err;
1226
1227 /* PLL configuration is required */
1228 err = si5341_initialize_pll(data);
1229 if (err < 0)
1230 return err;
1231 }
1232
1233 /* Register the PLL */
1234 data->pxtal_name = __clk_get_name(data->pxtal);
1235 init.parent_names = &data->pxtal_name;
1236 init.num_parents = 1; /* For now, only XTAL input supported */
1237 init.ops = &si5341_clk_ops;
1238 init.flags = 0;
1239 data->hw.init = &init;
1240
1241 err = devm_clk_hw_register(&client->dev, &data->hw);
1242 if (err) {
1243 dev_err(&client->dev, "clock registration failed\n");
1244 return err;
1245 }
1246
1247 init.num_parents = 1;
1248 init.parent_names = &root_clock_name;
1249 init.ops = &si5341_synth_clk_ops;
1250 for (i = 0; i < data->num_synth; ++i) {
1251 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1252 "%s.N%u", client->dev.of_node->name, i);
1253 init.name = synth_clock_names[i];
1254 data->synth[i].index = i;
1255 data->synth[i].data = data;
1256 data->synth[i].hw.init = &init;
1257 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1258 if (err) {
1259 dev_err(&client->dev,
1260 "synth N%u registration failed\n", i);
1261 }
1262 }
1263
1264 init.num_parents = data->num_synth;
1265 init.parent_names = synth_clock_names;
1266 init.ops = &si5341_output_clk_ops;
1267 for (i = 0; i < data->num_outputs; ++i) {
1268 init.name = kasprintf(GFP_KERNEL, "%s.%d",
1269 client->dev.of_node->name, i);
1270 init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1271 data->clk[i].index = i;
1272 data->clk[i].data = data;
1273 data->clk[i].hw.init = &init;
1274 if (config[i].out_format_drv_bits & 0x07) {
1275 regmap_write(data->regmap,
1276 SI5341_OUT_FORMAT(&data->clk[i]),
1277 config[i].out_format_drv_bits);
1278 regmap_write(data->regmap,
1279 SI5341_OUT_CM(&data->clk[i]),
1280 config[i].out_cm_ampl_bits);
1281 }
1282 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1283 kfree(init.name); /* clock framework made a copy of the name */
1284 if (err) {
1285 dev_err(&client->dev,
1286 "output %u registration failed\n", i);
1287 return err;
1288 }
1289 if (config[i].always_on)
1290 clk_prepare(data->clk[i].hw.clk);
1291 }
1292
1293 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_si5341_get,
1294 data);
1295 if (err) {
1296 dev_err(&client->dev, "unable to add clk provider\n");
1297 return err;
1298 }
1299
1300 if (initialization_required) {
1301 /* Synchronize */
1302 regcache_cache_only(data->regmap, false);
1303 err = regcache_sync(data->regmap);
1304 if (err < 0)
1305 return err;
1306
1307 err = si5341_finalize_defaults(data);
1308 if (err < 0)
1309 return err;
1310 }
1311
1312 /* Free the names, clk framework makes copies */
1313 for (i = 0; i < data->num_synth; ++i)
1314 devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1315
1316 return 0;
1317 }
1318
1319 static const struct i2c_device_id si5341_id[] = {
1320 { "si5340", 0 },
1321 { "si5341", 1 },
1322 { }
1323 };
1324 MODULE_DEVICE_TABLE(i2c, si5341_id);
1325
1326 static const struct of_device_id clk_si5341_of_match[] = {
1327 { .compatible = "silabs,si5340" },
1328 { .compatible = "silabs,si5341" },
1329 { }
1330 };
1331 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1332
1333 static struct i2c_driver si5341_driver = {
1334 .driver = {
1335 .name = "si5341",
1336 .of_match_table = clk_si5341_of_match,
1337 },
1338 .probe = si5341_probe,
1339 .id_table = si5341_id,
1340 };
1341 module_i2c_driver(si5341_driver);
1342
1343 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1344 MODULE_DESCRIPTION("Si5341 driver");
1345 MODULE_LICENSE("GPL");
connection oriented routing