1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Leilk Liu <leilk.liu@mediatek.com>
8 #include <linux/device.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
15 #include <linux/of_gpio.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
22 #define SPI_CFG0_REG 0x0000
23 #define SPI_CFG1_REG 0x0004
24 #define SPI_TX_SRC_REG 0x0008
25 #define SPI_RX_DST_REG 0x000c
26 #define SPI_TX_DATA_REG 0x0010
27 #define SPI_RX_DATA_REG 0x0014
28 #define SPI_CMD_REG 0x0018
29 #define SPI_STATUS0_REG 0x001c
30 #define SPI_PAD_SEL_REG 0x0024
31 #define SPI_CFG2_REG 0x0028
32 #define SPI_TX_SRC_REG_64 0x002c
33 #define SPI_RX_DST_REG_64 0x0030
35 #define SPI_CFG0_SCK_HIGH_OFFSET 0
36 #define SPI_CFG0_SCK_LOW_OFFSET 8
37 #define SPI_CFG0_CS_HOLD_OFFSET 16
38 #define SPI_CFG0_CS_SETUP_OFFSET 24
39 #define SPI_ADJUST_CFG0_SCK_LOW_OFFSET 16
40 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0
41 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16
43 #define SPI_CFG1_CS_IDLE_OFFSET 0
44 #define SPI_CFG1_PACKET_LOOP_OFFSET 8
45 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16
46 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30
48 #define SPI_CFG1_CS_IDLE_MASK 0xff
49 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00
50 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
52 #define SPI_CMD_ACT BIT(0)
53 #define SPI_CMD_RESUME BIT(1)
54 #define SPI_CMD_RST BIT(2)
55 #define SPI_CMD_PAUSE_EN BIT(4)
56 #define SPI_CMD_DEASSERT BIT(5)
57 #define SPI_CMD_SAMPLE_SEL BIT(6)
58 #define SPI_CMD_CS_POL BIT(7)
59 #define SPI_CMD_CPHA BIT(8)
60 #define SPI_CMD_CPOL BIT(9)
61 #define SPI_CMD_RX_DMA BIT(10)
62 #define SPI_CMD_TX_DMA BIT(11)
63 #define SPI_CMD_TXMSBF BIT(12)
64 #define SPI_CMD_RXMSBF BIT(13)
65 #define SPI_CMD_RX_ENDIAN BIT(14)
66 #define SPI_CMD_TX_ENDIAN BIT(15)
67 #define SPI_CMD_FINISH_IE BIT(16)
68 #define SPI_CMD_PAUSE_IE BIT(17)
70 #define MT8173_SPI_MAX_PAD_SEL 3
72 #define MTK_SPI_PAUSE_INT_STATUS 0x2
74 #define MTK_SPI_IDLE 0
75 #define MTK_SPI_PAUSED 1
77 #define MTK_SPI_MAX_FIFO_SIZE 32U
78 #define MTK_SPI_PACKET_SIZE 1024
79 #define MTK_SPI_32BITS_MASK (0xffffffff)
81 #define DMA_ADDR_EXT_BITS (36)
82 #define DMA_ADDR_DEF_BITS (32)
84 struct mtk_spi_compatible
{
86 /* Must explicitly send dummy Tx bytes to do Rx only transfer */
88 /* some IC design adjust cfg register to enhance time accuracy */
90 /* some IC support DMA addr extension */
99 struct clk
*parent_clk
, *sel_clk
, *spi_clk
;
100 struct spi_transfer
*cur_transfer
;
103 struct scatterlist
*tx_sgl
, *rx_sgl
;
104 u32 tx_sgl_len
, rx_sgl_len
;
105 const struct mtk_spi_compatible
*dev_comp
;
108 static const struct mtk_spi_compatible mtk_common_compat
;
110 static const struct mtk_spi_compatible mt2712_compat
= {
114 static const struct mtk_spi_compatible mt6765_compat
= {
115 .need_pad_sel
= true,
117 .enhance_timing
= true,
121 static const struct mtk_spi_compatible mt7622_compat
= {
123 .enhance_timing
= true,
126 static const struct mtk_spi_compatible mt8173_compat
= {
127 .need_pad_sel
= true,
131 static const struct mtk_spi_compatible mt8183_compat
= {
132 .need_pad_sel
= true,
134 .enhance_timing
= true,
138 * A piece of default chip info unless the platform
141 static const struct mtk_chip_config mtk_default_chip_info
= {
145 static const struct of_device_id mtk_spi_of_match
[] = {
146 { .compatible
= "mediatek,mt2701-spi",
147 .data
= (void *)&mtk_common_compat
,
149 { .compatible
= "mediatek,mt2712-spi",
150 .data
= (void *)&mt2712_compat
,
152 { .compatible
= "mediatek,mt6589-spi",
153 .data
= (void *)&mtk_common_compat
,
155 { .compatible
= "mediatek,mt6765-spi",
156 .data
= (void *)&mt6765_compat
,
158 { .compatible
= "mediatek,mt7622-spi",
159 .data
= (void *)&mt7622_compat
,
161 { .compatible
= "mediatek,mt7629-spi",
162 .data
= (void *)&mt7622_compat
,
164 { .compatible
= "mediatek,mt8135-spi",
165 .data
= (void *)&mtk_common_compat
,
167 { .compatible
= "mediatek,mt8173-spi",
168 .data
= (void *)&mt8173_compat
,
170 { .compatible
= "mediatek,mt8183-spi",
171 .data
= (void *)&mt8183_compat
,
175 MODULE_DEVICE_TABLE(of
, mtk_spi_of_match
);
177 static void mtk_spi_reset(struct mtk_spi
*mdata
)
181 /* set the software reset bit in SPI_CMD_REG. */
182 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
183 reg_val
|= SPI_CMD_RST
;
184 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
186 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
187 reg_val
&= ~SPI_CMD_RST
;
188 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
191 static int mtk_spi_prepare_message(struct spi_master
*master
,
192 struct spi_message
*msg
)
196 struct spi_device
*spi
= msg
->spi
;
197 struct mtk_chip_config
*chip_config
= spi
->controller_data
;
198 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
200 cpha
= spi
->mode
& SPI_CPHA
? 1 : 0;
201 cpol
= spi
->mode
& SPI_CPOL
? 1 : 0;
203 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
205 reg_val
|= SPI_CMD_CPHA
;
207 reg_val
&= ~SPI_CMD_CPHA
;
209 reg_val
|= SPI_CMD_CPOL
;
211 reg_val
&= ~SPI_CMD_CPOL
;
213 /* set the mlsbx and mlsbtx */
214 if (spi
->mode
& SPI_LSB_FIRST
) {
215 reg_val
&= ~SPI_CMD_TXMSBF
;
216 reg_val
&= ~SPI_CMD_RXMSBF
;
218 reg_val
|= SPI_CMD_TXMSBF
;
219 reg_val
|= SPI_CMD_RXMSBF
;
222 /* set the tx/rx endian */
223 #ifdef __LITTLE_ENDIAN
224 reg_val
&= ~SPI_CMD_TX_ENDIAN
;
225 reg_val
&= ~SPI_CMD_RX_ENDIAN
;
227 reg_val
|= SPI_CMD_TX_ENDIAN
;
228 reg_val
|= SPI_CMD_RX_ENDIAN
;
231 if (mdata
->dev_comp
->enhance_timing
) {
232 /* set CS polarity */
233 if (spi
->mode
& SPI_CS_HIGH
)
234 reg_val
|= SPI_CMD_CS_POL
;
236 reg_val
&= ~SPI_CMD_CS_POL
;
238 if (chip_config
->sample_sel
)
239 reg_val
|= SPI_CMD_SAMPLE_SEL
;
241 reg_val
&= ~SPI_CMD_SAMPLE_SEL
;
244 /* set finish and pause interrupt always enable */
245 reg_val
|= SPI_CMD_FINISH_IE
| SPI_CMD_PAUSE_IE
;
247 /* disable dma mode */
248 reg_val
&= ~(SPI_CMD_TX_DMA
| SPI_CMD_RX_DMA
);
250 /* disable deassert mode */
251 reg_val
&= ~SPI_CMD_DEASSERT
;
253 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
256 if (mdata
->dev_comp
->need_pad_sel
)
257 writel(mdata
->pad_sel
[spi
->chip_select
],
258 mdata
->base
+ SPI_PAD_SEL_REG
);
263 static void mtk_spi_set_cs(struct spi_device
*spi
, bool enable
)
266 struct mtk_spi
*mdata
= spi_master_get_devdata(spi
->master
);
268 if (spi
->mode
& SPI_CS_HIGH
)
271 reg_val
= readl(mdata
->base
+ SPI_CMD_REG
);
273 reg_val
|= SPI_CMD_PAUSE_EN
;
274 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
276 reg_val
&= ~SPI_CMD_PAUSE_EN
;
277 writel(reg_val
, mdata
->base
+ SPI_CMD_REG
);
278 mdata
->state
= MTK_SPI_IDLE
;
279 mtk_spi_reset(mdata
);
283 static void mtk_spi_prepare_transfer(struct spi_master
*master
,
284 struct spi_transfer
*xfer
)
286 u32 spi_clk_hz
, div
, sck_time
, cs_time
, reg_val
= 0;
287 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
289 spi_clk_hz
= clk_get_rate(mdata
->spi_clk
);
290 if (xfer
->speed_hz
< spi_clk_hz
/ 2)
291 div
= DIV_ROUND_UP(spi_clk_hz
, xfer
->speed_hz
);
295 sck_time
= (div
+ 1) / 2;
296 cs_time
= sck_time
* 2;
298 if (mdata
->dev_comp
->enhance_timing
) {
299 reg_val
|= (((sck_time
- 1) & 0xffff)
300 << SPI_CFG0_SCK_HIGH_OFFSET
);
301 reg_val
|= (((sck_time
- 1) & 0xffff)
302 << SPI_ADJUST_CFG0_SCK_LOW_OFFSET
);
303 writel(reg_val
, mdata
->base
+ SPI_CFG2_REG
);
304 reg_val
|= (((cs_time
- 1) & 0xffff)
305 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET
);
306 reg_val
|= (((cs_time
- 1) & 0xffff)
307 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET
);
308 writel(reg_val
, mdata
->base
+ SPI_CFG0_REG
);
310 reg_val
|= (((sck_time
- 1) & 0xff)
311 << SPI_CFG0_SCK_HIGH_OFFSET
);
312 reg_val
|= (((sck_time
- 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET
);
313 reg_val
|= (((cs_time
- 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET
);
314 reg_val
|= (((cs_time
- 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET
);
315 writel(reg_val
, mdata
->base
+ SPI_CFG0_REG
);
318 reg_val
= readl(mdata
->base
+ SPI_CFG1_REG
);
319 reg_val
&= ~SPI_CFG1_CS_IDLE_MASK
;
320 reg_val
|= (((cs_time
- 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET
);
321 writel(reg_val
, mdata
->base
+ SPI_CFG1_REG
);
324 static void mtk_spi_setup_packet(struct spi_master
*master
)
326 u32 packet_size
, packet_loop
, reg_val
;
327 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
329 packet_size
= min_t(u32
, mdata
->xfer_len
, MTK_SPI_PACKET_SIZE
);
330 packet_loop
= mdata
->xfer_len
/ packet_size
;
332 reg_val
= readl(mdata
->base
+ SPI_CFG1_REG
);
333 reg_val
&= ~(SPI_CFG1_PACKET_LENGTH_MASK
| SPI_CFG1_PACKET_LOOP_MASK
);
334 reg_val
|= (packet_size
- 1) << SPI_CFG1_PACKET_LENGTH_OFFSET
;
335 reg_val
|= (packet_loop
- 1) << SPI_CFG1_PACKET_LOOP_OFFSET
;
336 writel(reg_val
, mdata
->base
+ SPI_CFG1_REG
);
339 static void mtk_spi_enable_transfer(struct spi_master
*master
)
342 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
344 cmd
= readl(mdata
->base
+ SPI_CMD_REG
);
345 if (mdata
->state
== MTK_SPI_IDLE
)
348 cmd
|= SPI_CMD_RESUME
;
349 writel(cmd
, mdata
->base
+ SPI_CMD_REG
);
352 static int mtk_spi_get_mult_delta(u32 xfer_len
)
356 if (xfer_len
> MTK_SPI_PACKET_SIZE
)
357 mult_delta
= xfer_len
% MTK_SPI_PACKET_SIZE
;
364 static void mtk_spi_update_mdata_len(struct spi_master
*master
)
367 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
369 if (mdata
->tx_sgl_len
&& mdata
->rx_sgl_len
) {
370 if (mdata
->tx_sgl_len
> mdata
->rx_sgl_len
) {
371 mult_delta
= mtk_spi_get_mult_delta(mdata
->rx_sgl_len
);
372 mdata
->xfer_len
= mdata
->rx_sgl_len
- mult_delta
;
373 mdata
->rx_sgl_len
= mult_delta
;
374 mdata
->tx_sgl_len
-= mdata
->xfer_len
;
376 mult_delta
= mtk_spi_get_mult_delta(mdata
->tx_sgl_len
);
377 mdata
->xfer_len
= mdata
->tx_sgl_len
- mult_delta
;
378 mdata
->tx_sgl_len
= mult_delta
;
379 mdata
->rx_sgl_len
-= mdata
->xfer_len
;
381 } else if (mdata
->tx_sgl_len
) {
382 mult_delta
= mtk_spi_get_mult_delta(mdata
->tx_sgl_len
);
383 mdata
->xfer_len
= mdata
->tx_sgl_len
- mult_delta
;
384 mdata
->tx_sgl_len
= mult_delta
;
385 } else if (mdata
->rx_sgl_len
) {
386 mult_delta
= mtk_spi_get_mult_delta(mdata
->rx_sgl_len
);
387 mdata
->xfer_len
= mdata
->rx_sgl_len
- mult_delta
;
388 mdata
->rx_sgl_len
= mult_delta
;
392 static void mtk_spi_setup_dma_addr(struct spi_master
*master
,
393 struct spi_transfer
*xfer
)
395 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
398 writel((u32
)(xfer
->tx_dma
& MTK_SPI_32BITS_MASK
),
399 mdata
->base
+ SPI_TX_SRC_REG
);
400 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
401 if (mdata
->dev_comp
->dma_ext
)
402 writel((u32
)(xfer
->tx_dma
>> 32),
403 mdata
->base
+ SPI_TX_SRC_REG_64
);
408 writel((u32
)(xfer
->rx_dma
& MTK_SPI_32BITS_MASK
),
409 mdata
->base
+ SPI_RX_DST_REG
);
410 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
411 if (mdata
->dev_comp
->dma_ext
)
412 writel((u32
)(xfer
->rx_dma
>> 32),
413 mdata
->base
+ SPI_RX_DST_REG_64
);
418 static int mtk_spi_fifo_transfer(struct spi_master
*master
,
419 struct spi_device
*spi
,
420 struct spi_transfer
*xfer
)
424 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
426 mdata
->cur_transfer
= xfer
;
427 mdata
->xfer_len
= min(MTK_SPI_MAX_FIFO_SIZE
, xfer
->len
);
428 mdata
->num_xfered
= 0;
429 mtk_spi_prepare_transfer(master
, xfer
);
430 mtk_spi_setup_packet(master
);
433 iowrite32_rep(mdata
->base
+ SPI_TX_DATA_REG
, xfer
->tx_buf
, cnt
);
435 remainder
= xfer
->len
% 4;
438 memcpy(®_val
, xfer
->tx_buf
+ (cnt
* 4), remainder
);
439 writel(reg_val
, mdata
->base
+ SPI_TX_DATA_REG
);
442 mtk_spi_enable_transfer(master
);
447 static int mtk_spi_dma_transfer(struct spi_master
*master
,
448 struct spi_device
*spi
,
449 struct spi_transfer
*xfer
)
452 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
454 mdata
->tx_sgl
= NULL
;
455 mdata
->rx_sgl
= NULL
;
456 mdata
->tx_sgl_len
= 0;
457 mdata
->rx_sgl_len
= 0;
458 mdata
->cur_transfer
= xfer
;
459 mdata
->num_xfered
= 0;
461 mtk_spi_prepare_transfer(master
, xfer
);
463 cmd
= readl(mdata
->base
+ SPI_CMD_REG
);
465 cmd
|= SPI_CMD_TX_DMA
;
467 cmd
|= SPI_CMD_RX_DMA
;
468 writel(cmd
, mdata
->base
+ SPI_CMD_REG
);
471 mdata
->tx_sgl
= xfer
->tx_sg
.sgl
;
473 mdata
->rx_sgl
= xfer
->rx_sg
.sgl
;
476 xfer
->tx_dma
= sg_dma_address(mdata
->tx_sgl
);
477 mdata
->tx_sgl_len
= sg_dma_len(mdata
->tx_sgl
);
480 xfer
->rx_dma
= sg_dma_address(mdata
->rx_sgl
);
481 mdata
->rx_sgl_len
= sg_dma_len(mdata
->rx_sgl
);
484 mtk_spi_update_mdata_len(master
);
485 mtk_spi_setup_packet(master
);
486 mtk_spi_setup_dma_addr(master
, xfer
);
487 mtk_spi_enable_transfer(master
);
492 static int mtk_spi_transfer_one(struct spi_master
*master
,
493 struct spi_device
*spi
,
494 struct spi_transfer
*xfer
)
496 if (master
->can_dma(master
, spi
, xfer
))
497 return mtk_spi_dma_transfer(master
, spi
, xfer
);
499 return mtk_spi_fifo_transfer(master
, spi
, xfer
);
502 static bool mtk_spi_can_dma(struct spi_master
*master
,
503 struct spi_device
*spi
,
504 struct spi_transfer
*xfer
)
506 /* Buffers for DMA transactions must be 4-byte aligned */
507 return (xfer
->len
> MTK_SPI_MAX_FIFO_SIZE
&&
508 (unsigned long)xfer
->tx_buf
% 4 == 0 &&
509 (unsigned long)xfer
->rx_buf
% 4 == 0);
512 static int mtk_spi_setup(struct spi_device
*spi
)
514 struct mtk_spi
*mdata
= spi_master_get_devdata(spi
->master
);
516 if (!spi
->controller_data
)
517 spi
->controller_data
= (void *)&mtk_default_chip_info
;
519 if (mdata
->dev_comp
->need_pad_sel
&& gpio_is_valid(spi
->cs_gpio
))
520 gpio_direction_output(spi
->cs_gpio
, !(spi
->mode
& SPI_CS_HIGH
));
525 static irqreturn_t
mtk_spi_interrupt(int irq
, void *dev_id
)
527 u32 cmd
, reg_val
, cnt
, remainder
, len
;
528 struct spi_master
*master
= dev_id
;
529 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
530 struct spi_transfer
*trans
= mdata
->cur_transfer
;
532 reg_val
= readl(mdata
->base
+ SPI_STATUS0_REG
);
533 if (reg_val
& MTK_SPI_PAUSE_INT_STATUS
)
534 mdata
->state
= MTK_SPI_PAUSED
;
536 mdata
->state
= MTK_SPI_IDLE
;
538 if (!master
->can_dma(master
, master
->cur_msg
->spi
, trans
)) {
540 cnt
= mdata
->xfer_len
/ 4;
541 ioread32_rep(mdata
->base
+ SPI_RX_DATA_REG
,
542 trans
->rx_buf
+ mdata
->num_xfered
, cnt
);
543 remainder
= mdata
->xfer_len
% 4;
545 reg_val
= readl(mdata
->base
+ SPI_RX_DATA_REG
);
546 memcpy(trans
->rx_buf
+
554 mdata
->num_xfered
+= mdata
->xfer_len
;
555 if (mdata
->num_xfered
== trans
->len
) {
556 spi_finalize_current_transfer(master
);
560 len
= trans
->len
- mdata
->num_xfered
;
561 mdata
->xfer_len
= min(MTK_SPI_MAX_FIFO_SIZE
, len
);
562 mtk_spi_setup_packet(master
);
564 cnt
= mdata
->xfer_len
/ 4;
565 iowrite32_rep(mdata
->base
+ SPI_TX_DATA_REG
,
566 trans
->tx_buf
+ mdata
->num_xfered
, cnt
);
568 remainder
= mdata
->xfer_len
% 4;
572 trans
->tx_buf
+ (cnt
* 4) + mdata
->num_xfered
,
574 writel(reg_val
, mdata
->base
+ SPI_TX_DATA_REG
);
577 mtk_spi_enable_transfer(master
);
583 trans
->tx_dma
+= mdata
->xfer_len
;
585 trans
->rx_dma
+= mdata
->xfer_len
;
587 if (mdata
->tx_sgl
&& (mdata
->tx_sgl_len
== 0)) {
588 mdata
->tx_sgl
= sg_next(mdata
->tx_sgl
);
590 trans
->tx_dma
= sg_dma_address(mdata
->tx_sgl
);
591 mdata
->tx_sgl_len
= sg_dma_len(mdata
->tx_sgl
);
594 if (mdata
->rx_sgl
&& (mdata
->rx_sgl_len
== 0)) {
595 mdata
->rx_sgl
= sg_next(mdata
->rx_sgl
);
597 trans
->rx_dma
= sg_dma_address(mdata
->rx_sgl
);
598 mdata
->rx_sgl_len
= sg_dma_len(mdata
->rx_sgl
);
602 if (!mdata
->tx_sgl
&& !mdata
->rx_sgl
) {
603 /* spi disable dma */
604 cmd
= readl(mdata
->base
+ SPI_CMD_REG
);
605 cmd
&= ~SPI_CMD_TX_DMA
;
606 cmd
&= ~SPI_CMD_RX_DMA
;
607 writel(cmd
, mdata
->base
+ SPI_CMD_REG
);
609 spi_finalize_current_transfer(master
);
613 mtk_spi_update_mdata_len(master
);
614 mtk_spi_setup_packet(master
);
615 mtk_spi_setup_dma_addr(master
, trans
);
616 mtk_spi_enable_transfer(master
);
621 static int mtk_spi_probe(struct platform_device
*pdev
)
623 struct spi_master
*master
;
624 struct mtk_spi
*mdata
;
625 const struct of_device_id
*of_id
;
626 int i
, irq
, ret
, addr_bits
;
628 master
= spi_alloc_master(&pdev
->dev
, sizeof(*mdata
));
630 dev_err(&pdev
->dev
, "failed to alloc spi master\n");
634 master
->auto_runtime_pm
= true;
635 master
->dev
.of_node
= pdev
->dev
.of_node
;
636 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
;
638 master
->set_cs
= mtk_spi_set_cs
;
639 master
->prepare_message
= mtk_spi_prepare_message
;
640 master
->transfer_one
= mtk_spi_transfer_one
;
641 master
->can_dma
= mtk_spi_can_dma
;
642 master
->setup
= mtk_spi_setup
;
644 of_id
= of_match_node(mtk_spi_of_match
, pdev
->dev
.of_node
);
646 dev_err(&pdev
->dev
, "failed to probe of_node\n");
651 mdata
= spi_master_get_devdata(master
);
652 mdata
->dev_comp
= of_id
->data
;
654 if (mdata
->dev_comp
->enhance_timing
)
655 master
->mode_bits
|= SPI_CS_HIGH
;
657 if (mdata
->dev_comp
->must_tx
)
658 master
->flags
= SPI_MASTER_MUST_TX
;
660 if (mdata
->dev_comp
->need_pad_sel
) {
661 mdata
->pad_num
= of_property_count_u32_elems(
663 "mediatek,pad-select");
664 if (mdata
->pad_num
< 0) {
666 "No 'mediatek,pad-select' property\n");
671 mdata
->pad_sel
= devm_kmalloc_array(&pdev
->dev
, mdata
->pad_num
,
672 sizeof(u32
), GFP_KERNEL
);
673 if (!mdata
->pad_sel
) {
678 for (i
= 0; i
< mdata
->pad_num
; i
++) {
679 of_property_read_u32_index(pdev
->dev
.of_node
,
680 "mediatek,pad-select",
681 i
, &mdata
->pad_sel
[i
]);
682 if (mdata
->pad_sel
[i
] > MT8173_SPI_MAX_PAD_SEL
) {
683 dev_err(&pdev
->dev
, "wrong pad-sel[%d]: %u\n",
684 i
, mdata
->pad_sel
[i
]);
691 platform_set_drvdata(pdev
, master
);
692 mdata
->base
= devm_platform_ioremap_resource(pdev
, 0);
693 if (IS_ERR(mdata
->base
)) {
694 ret
= PTR_ERR(mdata
->base
);
698 irq
= platform_get_irq(pdev
, 0);
704 if (!pdev
->dev
.dma_mask
)
705 pdev
->dev
.dma_mask
= &pdev
->dev
.coherent_dma_mask
;
707 ret
= devm_request_irq(&pdev
->dev
, irq
, mtk_spi_interrupt
,
708 IRQF_TRIGGER_NONE
, dev_name(&pdev
->dev
), master
);
710 dev_err(&pdev
->dev
, "failed to register irq (%d)\n", ret
);
714 mdata
->parent_clk
= devm_clk_get(&pdev
->dev
, "parent-clk");
715 if (IS_ERR(mdata
->parent_clk
)) {
716 ret
= PTR_ERR(mdata
->parent_clk
);
717 dev_err(&pdev
->dev
, "failed to get parent-clk: %d\n", ret
);
721 mdata
->sel_clk
= devm_clk_get(&pdev
->dev
, "sel-clk");
722 if (IS_ERR(mdata
->sel_clk
)) {
723 ret
= PTR_ERR(mdata
->sel_clk
);
724 dev_err(&pdev
->dev
, "failed to get sel-clk: %d\n", ret
);
728 mdata
->spi_clk
= devm_clk_get(&pdev
->dev
, "spi-clk");
729 if (IS_ERR(mdata
->spi_clk
)) {
730 ret
= PTR_ERR(mdata
->spi_clk
);
731 dev_err(&pdev
->dev
, "failed to get spi-clk: %d\n", ret
);
735 ret
= clk_prepare_enable(mdata
->spi_clk
);
737 dev_err(&pdev
->dev
, "failed to enable spi_clk (%d)\n", ret
);
741 ret
= clk_set_parent(mdata
->sel_clk
, mdata
->parent_clk
);
743 dev_err(&pdev
->dev
, "failed to clk_set_parent (%d)\n", ret
);
744 clk_disable_unprepare(mdata
->spi_clk
);
748 clk_disable_unprepare(mdata
->spi_clk
);
750 pm_runtime_enable(&pdev
->dev
);
752 ret
= devm_spi_register_master(&pdev
->dev
, master
);
754 dev_err(&pdev
->dev
, "failed to register master (%d)\n", ret
);
755 goto err_disable_runtime_pm
;
758 if (mdata
->dev_comp
->need_pad_sel
) {
759 if (mdata
->pad_num
!= master
->num_chipselect
) {
761 "pad_num does not match num_chipselect(%d != %d)\n",
762 mdata
->pad_num
, master
->num_chipselect
);
764 goto err_disable_runtime_pm
;
767 if (!master
->cs_gpios
&& master
->num_chipselect
> 1) {
769 "cs_gpios not specified and num_chipselect > 1\n");
771 goto err_disable_runtime_pm
;
774 if (master
->cs_gpios
) {
775 for (i
= 0; i
< master
->num_chipselect
; i
++) {
776 ret
= devm_gpio_request(&pdev
->dev
,
778 dev_name(&pdev
->dev
));
781 "can't get CS GPIO %i\n", i
);
782 goto err_disable_runtime_pm
;
788 if (mdata
->dev_comp
->dma_ext
)
789 addr_bits
= DMA_ADDR_EXT_BITS
;
791 addr_bits
= DMA_ADDR_DEF_BITS
;
792 ret
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(addr_bits
));
794 dev_notice(&pdev
->dev
, "SPI dma_set_mask(%d) failed, ret:%d\n",
799 err_disable_runtime_pm
:
800 pm_runtime_disable(&pdev
->dev
);
802 spi_master_put(master
);
807 static int mtk_spi_remove(struct platform_device
*pdev
)
809 struct spi_master
*master
= platform_get_drvdata(pdev
);
810 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
812 pm_runtime_disable(&pdev
->dev
);
814 mtk_spi_reset(mdata
);
819 #ifdef CONFIG_PM_SLEEP
820 static int mtk_spi_suspend(struct device
*dev
)
823 struct spi_master
*master
= dev_get_drvdata(dev
);
824 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
826 ret
= spi_master_suspend(master
);
830 if (!pm_runtime_suspended(dev
))
831 clk_disable_unprepare(mdata
->spi_clk
);
836 static int mtk_spi_resume(struct device
*dev
)
839 struct spi_master
*master
= dev_get_drvdata(dev
);
840 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
842 if (!pm_runtime_suspended(dev
)) {
843 ret
= clk_prepare_enable(mdata
->spi_clk
);
845 dev_err(dev
, "failed to enable spi_clk (%d)\n", ret
);
850 ret
= spi_master_resume(master
);
852 clk_disable_unprepare(mdata
->spi_clk
);
856 #endif /* CONFIG_PM_SLEEP */
859 static int mtk_spi_runtime_suspend(struct device
*dev
)
861 struct spi_master
*master
= dev_get_drvdata(dev
);
862 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
864 clk_disable_unprepare(mdata
->spi_clk
);
869 static int mtk_spi_runtime_resume(struct device
*dev
)
871 struct spi_master
*master
= dev_get_drvdata(dev
);
872 struct mtk_spi
*mdata
= spi_master_get_devdata(master
);
875 ret
= clk_prepare_enable(mdata
->spi_clk
);
877 dev_err(dev
, "failed to enable spi_clk (%d)\n", ret
);
883 #endif /* CONFIG_PM */
885 static const struct dev_pm_ops mtk_spi_pm
= {
886 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend
, mtk_spi_resume
)
887 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend
,
888 mtk_spi_runtime_resume
, NULL
)
891 static struct platform_driver mtk_spi_driver
= {
895 .of_match_table
= mtk_spi_of_match
,
897 .probe
= mtk_spi_probe
,
898 .remove
= mtk_spi_remove
,
901 module_platform_driver(mtk_spi_driver
);
903 MODULE_DESCRIPTION("MTK SPI Controller driver");
904 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
905 MODULE_LICENSE("GPL v2");
906 MODULE_ALIAS("platform:mtk-spi");