platform/micaz/platform-conf.h

   1 /*
   2  * Copyright (c) 2010, Swedish Institute of Computer Science.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of the Institute nor the names of its contributors
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * $Id: platform-conf.h,v 1.1 2010/06/23 10:25:54 joxe Exp $
  30  */
  31
  32 /**
  33  * \file
  34  *         A brief description of what this file is
  35  * \author
  36  *         Niclas Finne <nfi@sics.se>
  37  *         Joakim Eriksson <joakime@sics.se>
  38  */
  39
  40 #ifndef __PLATFORM_CONF_H__
  41 #define __PLATFORM_CONF_H__
  42
  43 /*
  44  * Definitions below are dictated by the hardware and not really
  45  * changeable!
  46  */
  47 #define PLATFORM PLATFORM_AVR
  48
  49 /*
  50  * MCU and clock rate.
  51  * MICAZ runs on 7.3728 MHz clock.
  52  */
  53 #define MCU_MHZ 7
  54
  55 /* Clock ticks per second */
  56 #define CLOCK_CONF_SECOND 128
  57
  58
  59 /* LED ports */
  60 #define LEDS_PxDIR DDRA // port direction register
  61 #define LEDS_PxOUT PORTA // port register
  62 #define LEDS_CONF_RED    0x04 //red led
  63 #define LEDS_CONF_GREEN  0x02 // green led
  64 #define LEDS_CONF_YELLOW 0x01 // yellow led
  65
  66 /* COM port to be used for SLIP connection */
  67 #define SLIP_PORT RS232_PORT_0
  68
  69 /* Pre-allocated memory for loadable modules heap space (in bytes)*/
  70 #define MMEM_CONF_SIZE 256
  71
  72 /* Use the following address for code received via the codeprop
  73  * facility
  74  */
  75 #define EEPROMFS_ADDR_CODEPROP 0x8000
  76
  77 #define EEPROM_NODE_ID_START 0x00
  78
  79
  80 #define NETSTACK_CONF_RADIO   cc2420_driver
  81
  82
  83 /*
  84  * SPI bus configuration for the TMote Sky.
  85  */
  86
  87 /* SPI input/output registers. */
  88 #define SPI_TXBUF SPDR
  89 #define SPI_RXBUF SPDR
  90
  91 #define BV(bitno) _BV(bitno)
  92
  93 #define SPI_WAITFOREOTx() do { while (!(SPSR & BV(SPIF))); } while (0)
  94 #define SPI_WAITFOREORx() do { while (!(SPSR & BV(SPIF))); } while (0)
  95
  96 #define SCK            1  /* - Output: SPI Serial Clock (SCLK) - ATMEGA128 PORTB, PIN1 */
  97 #define MOSI           2  /* - Output: SPI Master out - slave in (MOSI) - ATMEGA128 PORTB, PIN2 */
  98 #define MISO           3  /* - Input:  SPI Master in - slave out (MISO) - ATMEGA128 PORTB, PIN3 */
  99
 100 /*
 101  * SPI bus - M25P80 external flash configuration.
 102  */
 103
 104 #define FLASH_PWR       3       /* P4.3 Output */
 105 #define FLASH_CS        4       /* P4.4 Output */
 106 #define FLASH_HOLD      7       /* P4.7 Output */
 107
 108 /* Enable/disable flash access to the SPI bus (active low). */
 109
 110 #define SPI_FLASH_ENABLE()  ( P4OUT &= ~BV(FLASH_CS) )
 111 #define SPI_FLASH_DISABLE() ( P4OUT |=  BV(FLASH_CS) )
 112
 113 #define SPI_FLASH_HOLD()                ( P4OUT &= ~BV(FLASH_HOLD) )
 114 #define SPI_FLASH_UNHOLD()              ( P4OUT |=  BV(FLASH_HOLD) )
 115
 116 /*
 117  * SPI bus - CC2420 pin configuration.
 118  */
 119
 120 #define CC2420_CONF_SYMBOL_LOOP_COUNT 500
 121
 122 /*
 123  * SPI bus - CC2420 pin configuration.
 124  */
 125
 126 #define FIFO_P         6
 127 #define FIFO           7
 128 #define CCA            6
 129
 130 #define SFD            4
 131 #define CSN            0
 132 #define VREG_EN        5
 133 #define RESET_N        6
 134
 135
 136 /* - Input: FIFOP from CC2420 - ATMEGA128 PORTE, PIN6 */
 137 #define CC2420_FIFOP_PORT(type)   P##type##E
 138 #define CC2420_FIFOP_PIN          6
 139 /* - Input: FIFO from CC2420 - ATMEGA128 PORTB, PIN7 */
 140 #define CC2420_FIFO_PORT(type)     P##type##B
 141 #define CC2420_FIFO_PIN            7
 142 /* - Input: CCA from CC2420 - ATMEGA128 PORTD, PIN6 */
 143 #define CC2420_CCA_PORT(type)      P##type##D
 144 #define CC2420_CCA_PIN             6
 145 /* - Input:  SFD from CC2420 - ATMEGA128 PORTD, PIN4 */
 146 #define CC2420_SFD_PORT(type)      P##type##D
 147 #define CC2420_SFD_PIN             4
 148 /* - Output: SPI Chip Select (CS_N) - ATMEGA128 PORTB, PIN0 */
 149 #define CC2420_CSN_PORT(type)      P##type##B
 150 #define CC2420_CSN_PIN             0
 151 /* - Output: VREG_EN to CC2420 - ATMEGA128 PORTA, PIN5 */
 152 #define CC2420_VREG_PORT(type)     P##type##A
 153 #define CC2420_VREG_PIN            5
 154 /* - Output: RESET_N to CC2420 - ATMEGA128 PORTA, PIN6 */
 155 #define CC2420_RESET_PORT(type)    P##type##A
 156 #define CC2420_RESET_PIN           6
 157
 158 #define CC2420_IRQ_VECTOR INT6_vect
 159
 160 /* Pin status. */
 161 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
 162 #define CC2420_FIFO_IS_1  (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
 163 #define CC2420_CCA_IS_1   (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
 164 #define CC2420_SFD_IS_1   (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
 165
 166 /* The CC2420 reset pin. */
 167 #define SET_RESET_INACTIVE()   (CC2420_RESET_PORT(ORT) |=  BV(CC2420_RESET_PIN))
 168 #define SET_RESET_ACTIVE()     (CC2420_RESET_PORT(ORT) &= ~BV(CC2420_RESET_PIN))
 169
 170 /* CC2420 voltage regulator enable pin. */
 171 #define SET_VREG_ACTIVE()       (CC2420_VREG_PORT(ORT) |=  BV(CC2420_VREG_PIN))
 172 #define SET_VREG_INACTIVE()     (CC2420_VREG_PORT(ORT) &= ~BV(CC2420_VREG_PIN))
 173
 174 /* CC2420 rising edge trigger for external interrupt 6 (FIFOP).
 175  * Enable the external interrupt request for INT6.
 176  * See Atmega128 datasheet about EICRB Register
 177  */
 178 #define CC2420_FIFOP_INT_INIT() do {\
 179   EICRB |= 0x30; \
 180   CC2420_CLEAR_FIFOP_INT(); \
 181 } while (0)
 182
 183 /* FIFOP on external interrupt 6. */
 184 #define CC2420_ENABLE_FIFOP_INT()          do { EIMSK |= 0x40; } while (0)
 185 #define CC2420_DISABLE_FIFOP_INT()         do { EIMSK &= ~0x40; } while (0)
 186 #define CC2420_CLEAR_FIFOP_INT()           do { EIFR = 0x40; } while (0)
 187
 188 /*
 189  * Enables/disables CC2420 access to the SPI bus (not the bus).
 190  * (Chip Select)
 191  */
 192 #define CC2420_SPI_ENABLE() (PORTB &= ~BV(CSN)) /* ENABLE CSn (active low) */
 193 #define CC2420_SPI_DISABLE() (PORTB |=  BV(CSN)) /* DISABLE CSn (active low) */
 194
 195 #endif /* __PLATFORM_CONF_H__ */