platform/sky/contiki-conf.h

   1 /* -*- C -*- */
   2 /* @(#)$Id: contiki-conf.h,v 1.57 2009/06/29 09:54:39 nifi Exp $ */
   3
   4 #ifndef CONTIKI_CONF_H
   5 #define CONTIKI_CONF_H
   6
   7 /* Specifies the default MAC driver */
   8 #define MAC_CONF_DRIVER xmac_driver
   9
  10 #define XMAC_CONF_COMPOWER 1
  11 #define XMAC_CONF_ANNOUNCEMENTS 1
  12
  13 #define PACKETBUF_CONF_ATTRS_INLINE 1
  14
  15 #define QUEUEBUF_CONF_NUM          16
  16
  17 #define IEEE802154_CONF_PANID       0xABCD
  18
  19 #define SHELL_VARS_CONF_RAM_BEGIN 0x1100
  20 #define SHELL_VARS_CONF_RAM_END 0x2000
  21
  22 /* DCO speed resynchronization for more robust UART, etc. */
  23 #define DCOSYNCH_CONF_ENABLED 1
  24 #define DCOSYNCH_CONF_PERIOD 30
  25
  26 #ifndef WITH_UIP6
  27 #define TIMESYNCH_CONF_ENABLED 1
  28 #define CC2420_CONF_TIMESTAMPS 1
  29 #define CC2420_CONF_CHECKSUM   0
  30 #define RIME_CONF_NO_POLITE_ANNOUCEMENTS 0
  31 #else
  32 #define RIME_CONF_NO_POLITE_ANNOUCEMENTS 1
  33 #endif /* !WITH_UIP6 */
  34
  35 #define CFS_CONF_OFFSET_TYPE    long
  36
  37 #define PROFILE_CONF_ON 0
  38 #define ENERGEST_CONF_ON 1
  39
  40 #define HAVE_STDINT_H
  41 #define MSP430_MEMCPY_WORKAROUND 1
  42 #include "msp430def.h"
  43
  44 #ifndef RF_CHANNEL
  45 #define RF_CHANNEL              26
  46 #endif /* RF_CHANNEL */
  47
  48 #define ELFLOADER_CONF_TEXT_IN_ROM 0
  49 #define ELFLOADER_CONF_DATAMEMORY_SIZE 0x400
  50 #define ELFLOADER_CONF_TEXTMEMORY_SIZE 0x800
  51
  52 #define IRQ_PORT1 0x01
  53 #define IRQ_PORT2 0x02
  54 #define IRQ_ADC   0x03
  55
  56 #define CCIF
  57 #define CLIF
  58
  59 #define CC_CONF_INLINE inline
  60
  61 #define AODV_COMPLIANCE
  62 #define AODV_NUM_RT_ENTRIES 32
  63
  64 #define TMOTE_SKY 1
  65 #define WITH_ASCII 1
  66
  67 #define PROCESS_CONF_NUMEVENTS 8
  68 #define PROCESS_CONF_STATS 1
  69 /*#define PROCESS_CONF_FASTPOLL    4*/
  70
  71 /* CPU target speed in Hz */
  72 #define F_CPU 3900000uL /*2457600uL*/
  73
  74 /* Our clock resolution, this is the same as Unix HZ. */
  75 #define CLOCK_CONF_SECOND 128
  76
  77 #define BAUD2UBR(baud) ((F_CPU/baud))
  78
  79 #ifdef WITH_UIP6
  80
  81 #define RIMEADDR_CONF_SIZE              8
  82
  83 #define UIP_CONF_LL_802154              1
  84 #define UIP_CONF_LLH_LEN                0
  85
  86 #ifndef UIP_CONF_ROUTER
  87 #define UIP_CONF_ROUTER                 0
  88 #endif
  89
  90 #define UIP_CONF_IPV6                   1
  91 #define UIP_CONF_IPV6_QUEUE_PKT         1
  92 #define UIP_CONF_IPV6_CHECKS            1
  93 #define UIP_CONF_IPV6_REASSEMBLY        0
  94 #define UIP_CONF_NETIF_MAX_ADDRESSES    3
  95 #define UIP_CONF_ND6_MAX_PREFIXES       3
  96 #define UIP_CONF_ND6_MAX_NEIGHBORS      4
  97 #define UIP_CONF_ND6_MAX_DEFROUTERS     2
  98 #define UIP_CONF_IP_FORWARD             0
  99 #define UIP_CONF_BUFFER_SIZE            256
 100
 101 #define SICSLOWPAN_CONF_COMPRESSION_IPV6        0
 102 #define SICSLOWPAN_CONF_COMPRESSION_HC1         1
 103 #define SICSLOWPAN_CONF_COMPRESSION_HC01        2
 104 #define SICSLOWPAN_CONF_COMPRESSION             SICSLOWPAN_CONF_COMPRESSION_HC01
 105 #define SICSLOWPAN_CONF_FRAG                    0
 106 #define SICSLOWPAN_CONF_CONVENTIONAL_MAC        1
 107 #define SICSLOWPAN_CONF_MAX_ADDR_CONTEXTS       2
 108 #else
 109 #define UIP_CONF_IP_FORWARD      1
 110 #define UIP_CONF_BUFFER_SIZE     108
 111 #endif /* WITH_UIP6 */
 112
 113 #define UIP_CONF_ICMP_DEST_UNREACH 1
 114
 115 #define UIP_CONF_DHCP_LIGHT
 116 #define UIP_CONF_LLH_LEN         0
 117 #define UIP_CONF_RECEIVE_WINDOW  60
 118 #define UIP_CONF_TCP_MSS         60
 119 #define UIP_CONF_MAX_CONNECTIONS 4
 120 #define UIP_CONF_MAX_LISTENPORTS 8
 121 #define UIP_CONF_UDP_CONNS       12
 122 #define UIP_CONF_FWCACHE_SIZE    30
 123 #define UIP_CONF_BROADCAST       1
 124 #define UIP_ARCH_IPCHKSUM        1
 125 #define UIP_CONF_UDP             1
 126 #define UIP_CONF_UDP_CHECKSUMS   1
 127 #define UIP_CONF_PINGADDRCONF    0
 128 #define UIP_CONF_LOGGING         0
 129
 130 #define UIP_CONF_TCP_SPLIT       0
 131
 132 /*
 133  * Definitions below are dictated by the hardware and not really
 134  * changeable!
 135  */
 136
 137 /* LED ports */
 138 #define LEDS_PxDIR P5DIR
 139 #define LEDS_PxOUT P5OUT
 140 #define LEDS_CONF_RED    0x10
 141 #define LEDS_CONF_GREEN  0x20
 142 #define LEDS_CONF_YELLOW 0x40
 143
 144 /* Button sensors. */
 145 #define IRQ_PORT2 0x02
 146
 147 typedef unsigned short uip_stats_t;
 148 typedef unsigned short clock_time_t;
 149
 150 typedef unsigned long off_t;
 151 #define ROM_ERASE_UNIT_SIZE  512
 152 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
 153
 154 /* Use the first 64k of external flash for node configuration */
 155 #define NODE_ID_XMEM_OFFSET     (0 * XMEM_ERASE_UNIT_SIZE)
 156
 157 /* Use the second 64k of external flash for codeprop. */
 158 #define EEPROMFS_ADDR_CODEPROP  (1 * XMEM_ERASE_UNIT_SIZE)
 159
 160 #define CFS_XMEM_CONF_OFFSET    (2 * XMEM_ERASE_UNIT_SIZE)
 161 #define CFS_XMEM_CONF_SIZE      (1 * XMEM_ERASE_UNIT_SIZE)
 162
 163 #define CFS_RAM_CONF_SIZE 4096
 164
 165 /*
 166  * SPI bus configuration for the TMote Sky.
 167  */
 168
 169 /* SPI input/output registers. */
 170 #define SPI_TXBUF U0TXBUF
 171 #define SPI_RXBUF U0RXBUF
 172
 173                                 /* USART0 Tx buffer ready? */
 174 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
 175                                 /* USART0 Rx buffer ready? */
 176 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
 177
 178 #define SCK            1  /* P3.1 - Output: SPI Serial Clock (SCLK) */
 179 #define MOSI           2  /* P3.2 - Output: SPI Master out - slave in (MOSI) */
 180 #define MISO           3  /* P3.3 - Input:  SPI Master in - slave out (MISO) */
 181
 182 /*
 183  * SPI bus - M25P80 external flash configuration.
 184  */
 185
 186 #define FLASH_PWR       3       /* P4.3 Output */
 187 #define FLASH_CS        4       /* P4.4 Output */
 188 #define FLASH_HOLD      7       /* P4.7 Output */
 189
 190 /* Enable/disable flash access to the SPI bus (active low). */
 191
 192 #define SPI_FLASH_ENABLE()  ( P4OUT &= ~BV(FLASH_CS) )
 193 #define SPI_FLASH_DISABLE() ( P4OUT |=  BV(FLASH_CS) )
 194
 195 #define SPI_FLASH_HOLD()                ( P4OUT &= ~BV(FLASH_HOLD) )
 196 #define SPI_FLASH_UNHOLD()              ( P4OUT |=  BV(FLASH_HOLD) )
 197
 198 /*
 199  * SPI bus - CC2420 pin configuration.
 200  */
 201
 202 #define FIFO_P         0  /* P1.0 - Input: FIFOP from CC2420 */
 203 #define FIFO           3  /* P1.3 - Input: FIFO from CC2420 */
 204 #define CCA            4  /* P1.4 - Input: CCA from CC2420 */
 205
 206 #define SFD            1  /* P4.1 - Input:  SFD from CC2420 */
 207 #define CSN            2  /* P4.2 - Output: SPI Chip Select (CS_N) */
 208 #define VREG_EN        5  /* P4.5 - Output: VREG_EN to CC2420 */
 209 #define RESET_N        6  /* P4.6 - Output: RESET_N to CC2420 */
 210
 211 /* Pin status. */
 212
 213 #define FIFO_IS_1       (!!(P1IN & BV(FIFO)))
 214 #define CCA_IS_1        (!!(P1IN & BV(CCA) ))
 215 #define RESET_IS_1      (!!(P4IN & BV(RESET_N)))
 216 #define VREG_IS_1       (!!(P4IN & BV(VREG_EN)))
 217 #define FIFOP_IS_1      (!!(P1IN & BV(FIFO_P)))
 218 #define SFD_IS_1        (!!(P4IN & BV(SFD)))
 219
 220 /* The CC2420 reset pin. */
 221 #define SET_RESET_INACTIVE()    ( P4OUT |=  BV(RESET_N) )
 222 #define SET_RESET_ACTIVE()      ( P4OUT &= ~BV(RESET_N) )
 223
 224 /* CC2420 voltage regulator enable pin. */
 225 #define SET_VREG_ACTIVE()       ( P4OUT |=  BV(VREG_EN) )
 226 #define SET_VREG_INACTIVE()     ( P4OUT &= ~BV(VREG_EN) )
 227
 228 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
 229 #define FIFOP_INT_INIT() do {\
 230   P1IES &= ~BV(FIFO_P);\
 231   CLEAR_FIFOP_INT();\
 232 } while (0)
 233
 234 /* FIFOP on external interrupt 0. */
 235 #define ENABLE_FIFOP_INT()          do { P1IE |= BV(FIFO_P); } while (0)
 236 #define DISABLE_FIFOP_INT()         do { P1IE &= ~BV(FIFO_P); } while (0)
 237 #define CLEAR_FIFOP_INT()           do { P1IFG &= ~BV(FIFO_P); } while (0)
 238
 239 /* Enables/disables CC2420 access to the SPI bus (not the bus).
 240  *
 241  * These guys should really be renamed but are compatible with the
 242  * original Chipcon naming.
 243  *
 244  * SPI_CC2420_ENABLE/SPI_CC2420_DISABLE???
 245  * CC2420_ENABLE_SPI/CC2420_DISABLE_SPI???
 246  */
 247
 248 #define SPI_ENABLE()    ( P4OUT &= ~BV(CSN) ) /* ENABLE CSn (active low) */
 249 #define SPI_DISABLE()   ( P4OUT |=  BV(CSN) ) /* DISABLE CSn (active low) */
 250
 251 #ifdef PROJECT_CONF_H
 252 #include PROJECT_CONF_H
 253 #endif /* PROJECT_CONF_H */
 254
 255
 256
 257 #endif /* CONTIKI_CONF_H */