base/cpu_unittest.cc

   1 // Copyright (c) 2011 The Chromium Authors. All rights reserved.
   2 // Use of this source code is governed by a BSD-style license that can be
   3 // found in the LICENSE file.
   4
   5 #include "base/cpu.h"
   6
   7 #include "testing/gtest/include/gtest/gtest.h"
   8
   9 // Tests whether we can run extended instructions represented by the CPU
  10 // information. This test actually executes some extended instructions (such as
  11 // MMX, SSE, etc.) supported by the CPU and sees we can run them without
  12 // "undefined instruction" exceptions. That is, this test succeeds when this
  13 // test finishes without a crash.
  14 TEST(CPU, RunExtendedInstructions) {
  15 #if defined(ARCH_CPU_X86_FAMILY)
  16   // Retrieve the CPU information.
  17   base::CPU cpu;
  18
  19 #if defined(OS_WIN)
  20   ASSERT_TRUE(cpu.has_mmx());
  21
  22   // Execute an MMX instruction.
  23   __asm emms;
  24
  25   if (cpu.has_sse()) {
  26     // Execute an SSE instruction.
  27     __asm xorps xmm0, xmm0;
  28   }
  29
  30   if (cpu.has_sse2()) {
  31     // Execute an SSE 2 instruction.
  32     __asm psrldq xmm0, 0;
  33   }
  34
  35   if (cpu.has_sse3()) {
  36     // Execute an SSE 3 instruction.
  37     __asm addsubpd xmm0, xmm0;
  38   }
  39
  40   if (cpu.has_ssse3()) {
  41     // Execute a Supplimental SSE 3 instruction.
  42     __asm psignb xmm0, xmm0;
  43   }
  44
  45   if (cpu.has_sse41()) {
  46     // Execute an SSE 4.1 instruction.
  47     __asm pmuldq xmm0, xmm0;
  48   }
  49
  50   if (cpu.has_sse42()) {
  51     // Execute an SSE 4.2 instruction.
  52     __asm crc32 eax, eax;
  53   }
  54 #elif defined(OS_POSIX) && defined(__x86_64__)
  55   ASSERT_TRUE(cpu.has_mmx());
  56
  57   // Execute an MMX instruction.
  58   __asm__ __volatile__("emms\n" : : : "mm0");
  59
  60   if (cpu.has_sse()) {
  61     // Execute an SSE instruction.
  62     __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0");
  63   }
  64
  65   if (cpu.has_sse2()) {
  66     // Execute an SSE 2 instruction.
  67     __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0");
  68   }
  69
  70   if (cpu.has_sse3()) {
  71     // Execute an SSE 3 instruction.
  72     __asm__ __volatile__("addsubpd %%xmm0, %%xmm0\n" : : : "xmm0");
  73   }
  74
  75   if (cpu.has_ssse3()) {
  76     // Execute a Supplimental SSE 3 instruction.
  77     __asm__ __volatile__("psignb %%xmm0, %%xmm0\n" : : : "xmm0");
  78   }
  79
  80   if (cpu.has_sse41()) {
  81     // Execute an SSE 4.1 instruction.
  82     __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0");
  83   }
  84
  85   if (cpu.has_sse42()) {
  86     // Execute an SSE 4.2 instruction.
  87     __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax");
  88   }
  89 #endif
  90 #endif
  91 }