chibi/chb_drvr.h

   1 /*******************************************************************
   2     Copyright (C) 2009 FreakLabs
   3     All rights reserved.
   4
   5     Redistribution and use in source and binary forms, with or without
   6     modification, are permitted provided that the following conditions
   7     are met:
   8
   9     1. Redistributions of source code must retain the above copyright
  10        notice, this list of conditions and the following disclaimer.
  11     2. Redistributions in binary form must reproduce the above copyright
  12        notice, this list of conditions and the following disclaimer in the
  13        documentation and/or other materials provided with the distribution.
  14     3. Neither the name of the the copyright holder nor the names of its contributors
  15        may be used to endorse or promote products derived from this software
  16        without specific prior written permission.
  17
  18     THIS SOFTWARE IS PROVIDED BY THE THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
  19     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20     IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21     ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
  22     FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23     DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24     OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26     LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27     OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28     SUCH DAMAGE.
  29
  30     Originally written by Christopher Wang aka Akiba.
  31     Please post support questions to the FreakLabs forum.
  32
  33 *******************************************************************/
  34 #ifndef CHIBI_DRVR_H
  35 #define CHIBI_DRVR_H
  36
  37 #include <avr/io.h>
  38 #include <avr/interrupt.h>
  39 #include "types.h"
  40
  41 #define CHB_EEPROM_IEEE_ADDR    0x00
  42 #define CHB_EEPROM_SHORT_ADDR   0x09
  43
  44 #define CHB_SPI_CMD_RW      0xC0    /**<  Register Write (short mode). */
  45 #define CHB_SPI_CMD_RR      0x80    /**<  Register Read (short mode). */
  46 #define CHB_SPI_CMD_FW      0x60    /**<  Frame Transmit Mode (long mode). */
  47 #define CHB_SPI_CMD_FR      0x20    /**<  Frame Receive Mode (long mode). */
  48 #define CHB_SPI_CMD_SW      0x40    /**<  SRAM Write. */
  49 #define CHB_SPI_CMD_SR      0x00    /**<  SRAM Read. */
  50 #define CHB_SPI_CMD_RADDRM  0x7F    /**<  Register Address Mask. */
  51
  52 #define CHB_IRQ_BAT_LOW_MASK        0x80  /**< Mask for the BAT_LOW interrupt. */
  53 #define CHB_IRQ_TRX_UR_MASK         0x40  /**< Mask for the TRX_UR interrupt. */
  54 #define CHB_IRQ_TRX_END_MASK        0x08  /**< Mask for the TRX_END interrupt. */
  55 #define CHB_IRQ_RX_START_MASK       0x04  /**< Mask for the RX_START interrupt. */
  56 #define CHB_IRQ_PLL_UNLOCK_MASK     0x02  /**< Mask for the PLL_UNLOCK interrupt. */
  57 #define CHB_IRQ_PLL_LOCK_MASK       0x01  /**< Mask for the PLL_LOCK interrupt. */
  58
  59 #define CHB_RSTPORT     PORTB
  60 #define CHB_RSTPIN      4
  61 #define CHB_SLPTRPORT   PORTB
  62 #define CHB_SLPTRPIN    5
  63 #define CHB_DDR_SLPTR   DDRB
  64 #define CHB_DDR_RST     DDRB
  65 #define CHB_RADIO_IRQ   INT4_vect
  66
  67 #define CHB_ENTER_CRIT()    {U8 volatile saved_sreg = SREG; cli()
  68 #define CHB_LEAVE_CRIT()    SREG = saved_sreg;}
  69 #define CHB_RST_ENABLE()    do {CHB_RSTPORT &= ~(_BV(CHB_RSTPIN));} while (0)
  70 #define CHB_RST_DISABLE()   do {CHB_RSTPORT |= (_BV(CHB_RSTPIN));} while (0)
  71 #define CHB_SLPTR_ENABLE()  do {CHB_SLPTRPORT |= (_BV(CHB_SLPTRPIN));} while (0)
  72 #define CHB_SLPTR_DISABLE() do {CHB_SLPTRPORT &= ~(_BV(CHB_SLPTRPIN));} while (0)
  73
  74 enum
  75 {
  76     CCA_ED                    = 1,    /**< Use energy detection above threshold mode. */
  77     CCA_CARRIER_SENSE         = 2,    /**< Use carrier sense mode. */
  78     CCA_CARRIER_SENSE_WITH_ED = 3     /**< Use a combination of both energy detection and carrier sense. */
  79 };
  80
  81 enum
  82 {
  83     CHB_CHANNEL             = 11,
  84     CHB_PAN_ID              = 0x1234,
  85     CHB_TX_PWR              = 0x0,
  86     CHB_SHORT_ADDR          = 0x0,
  87     CHB_IEEE_ADDR           = 0x0,
  88     CHB_MAX_FRAME_RETRIES   = 3,
  89     CHB_MAX_CSMA_RETRIES    = 4,
  90     CHB_MIN_BE              = 0,
  91     CHB_CCA_MODE            = CCA_ED,
  92     CHB_CCA_ED_THRES        = 0x7,
  93     CHB_CSMA_SEED0          = 0,
  94     CHB_CSMA_SEED1          = 0
  95 };
  96
  97 enum
  98 {
  99     TRX_STATUS      = 0x01,
 100     TRX_STATE       = 0x02,
 101     TRX_CTRL0       = 0x03,
 102     TRX_CTRL1       = 0x04,
 103     PHY_TX_PWR      = 0x05,
 104     PHY_RSSI        = 0x06,
 105     PHY_ED_LEVEL    = 0x07,
 106     PHY_CC_CCA      = 0x08,
 107     CCA_THRES       = 0x09,
 108     IRQ_MASK        = 0x0e,
 109     IRQ_STATUS      = 0x0f,
 110     VREG_CTRL       = 0x10,
 111     BATMON          = 0x11,
 112     XOSC_CTRL       = 0x12,
 113     FTN_CTRL        = 0x18,
 114     PLL_CF          = 0x1a,
 115     PLL_DCU         = 0x1b,
 116     PART_NUM        = 0x1c,
 117     VERSION_NUM     = 0x1d,
 118     MAN_ID_0        = 0x1e,
 119     MAN_ID_1        = 0x1f,
 120     SHORT_ADDR_0    = 0x20,
 121     SHORT_ADDR_1    = 0x21,
 122     PAN_ID_0        = 0x22,
 123     PAN_ID_1        = 0x23,
 124     IEEE_ADDR_0     = 0x24,
 125     IEEE_ADDR_1     = 0x25,
 126     IEEE_ADDR_2     = 0x26,
 127     IEEE_ADDR_3     = 0x27,
 128     IEEE_ADDR_4     = 0x28,
 129     IEEE_ADDR_5     = 0x29,
 130     IEEE_ADDR_6     = 0x2a,
 131     IEEE_ADDR_7     = 0x2b,
 132     XAH_CTRL_0      = 0x2c,
 133     CSMA_SEED_0     = 0x2d,
 134     CSMA_SEED_1     = 0x2e
 135 };
 136
 137 enum
 138 {
 139     CHB_MAX_FRAME_RETRIES_POS   = 4,
 140     CHB_MAX_CSMA_RETIRES_POS    = 1,
 141     CHB_MIN_BE_POS              = 6,
 142     CHB_CSMA_SEED1_POS          = 0,
 143     CHB_CCA_MODE_POS            = 5,
 144     CHB_AUTO_CRC_POS            = 7,
 145     CHB_TRX_END_POS             = 3,
 146     CHB_TRAC_STATUS_POS         = 5,
 147     CHB_MIN_FRAME_LENGTH        = 3,
 148     CHB_MAX_FRAME_LENGTH        = 0x7f
 149 };
 150
 151 enum{
 152     TIME_TO_ENTER_P_ON               = 510,     /**<  Transition time from VCC is applied to P_ON. */
 153     TIME_P_ON_TO_TRX_OFF             = 510,     /**<  Transition time from P_ON to TRX_OFF. */
 154     TIME_SLEEP_TO_TRX_OFF            = 880,     /**<  Transition time from SLEEP to TRX_OFF. */
 155     TIME_RESET                       = 6,       /**<  Time to hold the RST pin low during reset */
 156     TIME_ED_MEASUREMENT              = 140,     /**<  Time it takes to do a ED measurement. */
 157     TIME_CCA                         = 140,     /**<  Time it takes to do a CCA. */
 158     TIME_PLL_LOCK                    = 150,     /**<  Maximum time it should take for the PLL to lock. */
 159     TIME_FTN_TUNING                  = 25,      /**<  Maximum time it should take to do the filter tuning. */
 160     TIME_NOCLK_TO_WAKE               = 6,       /**<  Transition time from *_NOCLK to being awake. */
 161     TIME_CMD_FORCE_TRX_OFF           = 1,       /**<  Time it takes to execute the FORCE_TRX_OFF command. */
 162     TIME_TRX_OFF_TO_PLL_ACTIVE       = 180,     /**<  Transition time from TRX_OFF to: RX_ON, PLL_ON, TX_ARET_ON and RX_AACK_ON. */
 163     TIME_STATE_TRANSITION_PLL_ACTIVE = 1,       /**<  Transition time from PLL active state to another. */
 164 };
 165
 166 enum{
 167     RADIO_SUCCESS = 0x40,                       /**< The requested service was performed successfully. */
 168     RADIO_UNSUPPORTED_DEVICE,                   /**< The connected device is not an Atmel AT86RF230. */
 169     RADIO_INVALID_ARGUMENT,                     /**< One or more of the supplied function arguments are invalid. */
 170     RADIO_TIMED_OUT,                            /**< The requested service timed out. */
 171     RADIO_WRONG_STATE,                          /**< The end-user tried to do an invalid state transition. */
 172     RADIO_BUSY_STATE,                           /**< The radio transceiver is busy receiving or transmitting. */
 173     RADIO_STATE_TRANSITION_FAILED,              /**< The requested state transition could not be completed. */
 174     RADIO_CCA_IDLE,                             /**< Channel is clear, available to transmit a new frame. */
 175     RADIO_CCA_BUSY,                             /**< Channel busy. */
 176     RADIO_TRX_BUSY,                             /**< Transceiver is busy receiving or transmitting data. */
 177     RADIO_BAT_LOW,                              /**< Measured battery voltage is lower than voltage threshold. */
 178     RADIO_BAT_OK,                               /**< Measured battery voltage is above the voltage threshold. */
 179     RADIO_CRC_FAILED,                           /**< The CRC failed for the actual frame. */
 180     RADIO_CHANNEL_ACCESS_FAILURE,               /**< The channel access failed during the auto mode. */
 181     RADIO_NO_ACK,                               /**< No acknowledge frame was received. */
 182 };
 183
 184 enum
 185 {
 186     CMD_NOP                  = 0,
 187     CMD_TX_START             = 2,
 188     CMD_FORCE_TRX_OFF        = 3,
 189     CMD_RX_ON                = 6,
 190     CMD_TRX_OFF              = 8,
 191     CMD_PLL_ON               = 9,
 192     CMD_RX_AACK_ON           = 22,
 193     CMD_TX_ARET_ON           = 25
 194 };
 195
 196 enum
 197 {
 198     P_ON                = 0,
 199     BUSY_RX             = 1,
 200     BUSY_TX             = 2,
 201     RX_ON               = 6,
 202     TRX_OFF             = 8,
 203     PLL_ON              = 9,
 204     SLEEP               = 15,
 205     BUSY_RX_AACK        = 17,
 206     BUSY_TX_ARET        = 18,
 207     RX_AACK_ON          = 22,
 208     TX_ARET_ON          = 25,
 209     RX_ON_NOCLK         = 28,
 210     RX_AACK_ON_NOCLK    = 29,
 211     BUSY_RX_AACK_NOCLK  = 30
 212 };
 213
 214 // init
 215 void chb_drvr_init();
 216
 217 // data access
 218 U8 chb_reg_read(U8 addr);
 219 U16 chb_reg_read16(U8 addr);
 220 void chb_reg_write(U8 addr, U8 val);
 221 void chb_reg_write16(U8 addr, U16 val);
 222 void chb_reg_write64(U8 addr, U8 *val);
 223 void chb_reg_read_mod_write(U8 addr, U8 val, U8 mask);
 224 void chb_frame_write(U8 *hdr, U8 hdr_len, U8 *data, U8 data_len);
 225
 226 // general configuration
 227 U8 chb_set_channel(U8 channel);
 228 void chb_set_ieee_addr(U8 *addr);
 229 void chb_get_ieee_addr(U8 *addr);
 230 void chb_set_short_addr(U16 addr);
 231 U16 chb_get_short_addr();
 232
 233 // data transmit
 234 U8 chb_tx(U8 *hdr, U8 *data, U8 len);
 235
 236 #ifdef CHB_DEBUG
 237 // sram access
 238 void chb_sram_read(U8 addr, U8 len, U8 *data);
 239 void chb_sram_write(U8 addr, U8 len, U8 *data);
 240 #endif
 241
 242 #endif
 243