arch/arm-cortex-m3/crt.c

   1 /* Author: Domen Puncer <domen@cba.si>.  License: WTFPL, see file LICENSE */
   2 #include "arch/crt.h"
   3
   4 extern void _ram_end;
   5
   6 void __naked reset_handler()
   7 {
   8         /* cortex-m3 trm 2.2.1 main stack and process stack */
   9         asm volatile (
  10                         //"ldr  sp, =_ram_end\n\t" /* isn't actually needed, cpu reads addr 0 */
  11                         /* select PSP as current stack pointer */
  12                         "mrs    r0, CONTROL\n\t"
  13                         "orr    r0, r0, #2\n\t"
  14                         "msr    CONTROL, r0\n\t"
  15                         "isb\n\t"
  16
  17                         /* hrm... this stack is ignored laters anyways, as the scheduler starts,
  18                          * so it could just be the same as for exceptions, yes? */
  19                         "ldr    sp, =_ram_end-1024\n\t" /* 1k for main stack */
  20
  21                         "bl     init\n\t"
  22                         "bl     main\n\t"
  23                         "b      generic_exception_handler\n\t"
  24         );
  25 }
  26
  27 /* cortex-m3 trm, 5.5.1, mcu stacks xPSR, PC, LR, R12, R3, R2, R1, R0 */
  28 void __naked generic_exception_handler()
  29 {
  30         asm volatile (
  31                         "tst    lr, #0x4\n\t" /* process task, see EXC_RETURN */
  32                         "ite    eq\n\t"
  33                         "mrseq  r0, MSP\n\t"
  34                         "mrsne  r0, PSP\n\t"
  35                         "push   {r4-r11, lr}\n\t" /* = stmfd/stmdb sp!, ... */
  36                         "mov    r1, sp\n\t"
  37                         "mrs    r2, IPSR\n\t"
  38                         "b      generic_exception_handler_c\n\t"
  39         );
  40 }
  41