arch/common/hidd.intelG33/intelG33_init.c

   1 /*
   2     Copyright © 2009-2010, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: intelG33_init.c
   6     Lang: English
   7 */
   8
   9
  10 #define DEBUG 1
  11 #include <aros/debug.h>
  12 #include <aros/libcall.h>
  13 #include <aros/asmcall.h>
  14 #include <aros/symbolsets.h>
  15 #include <aros/bootloader.h>
  16
  17 #define __OOP_NOATTRBASES__
  18
  19 #include <proto/exec.h>
  20 #include <proto/oop.h>
  21 #include <proto/bootloader.h>
  22
  23 #include <exec/types.h>
  24 #include <exec/lists.h>
  25 #include <exec/nodes.h>
  26
  27 #include <hidd/graphics.h>
  28 #include <hidd/irq.h>
  29 #include <hidd/pci.h>
  30 #include <hidd/graphics.h>
  31
  32 #include <oop/oop.h>
  33
  34 #include <utility/utility.h>
  35
  36 #include <inttypes.h>
  37
  38 #include LC_LIBDEFS_FILE
  39
  40 #include "intelG33_intern.h"
  41 #include "intelG33_regs.h"
  42
  43 static void IntelG33_int(HIDDT_IRQ_Handler *irq, HIDDT_IRQ_HwInfo *hw) {
  44     D(bug("[G33IRQ] IntelG33 INTERRUPT\n"));
  45 }
  46
  47 static inline __attribute__((always_inline)) ULONG pciReadLong(struct staticdata *sd, UBYTE bus, UBYTE dev, UBYTE sub, UBYTE reg) {
  48     struct pHidd_PCIDriver_ReadConfigLong __msg = {
  49             sd->mid_ReadLong,
  50             bus, dev, sub, reg
  51     }, *msg = &__msg;
  52
  53     return (ULONG)OOP_DoMethod(sd->pciDriver, (OOP_Msg)msg);
  54 }
  55
  56 static inline __attribute__((always_inline)) UWORD pciReadWord(struct staticdata *sd, UBYTE bus, UBYTE dev, UBYTE sub, UBYTE reg) {
  57     struct pHidd_PCIDriver_ReadConfigWord __msg = {
  58             sd->mid_ReadWord,
  59             bus, dev, sub, reg
  60     }, *msg = &__msg;
  61
  62     return (UWORD)OOP_DoMethod(sd->pciDriver, (OOP_Msg)msg);
  63 }
  64
  65 static inline __attribute__((always_inline)) UWORD pciReadByte(struct staticdata *sd, UBYTE bus, UBYTE dev, UBYTE sub, UBYTE reg) {
  66     struct pHidd_PCIDriver_ReadConfigByte __msg = {
  67             sd->mid_ReadByte,
  68             bus, dev, sub, reg
  69     }, *msg = &__msg;
  70
  71     return (UBYTE)OOP_DoMethod(sd->pciDriver, (OOP_Msg)msg);
  72 }
  73
  74 static BOOL Chip_Init(struct staticdata *sd) {
  75     D(bug("[G33] IntelG33 chip init\n"));
  76
  77 //    D(bug("[G33]   ADPA %08x\n",G33_RD_REGL(MMADR, ADPA) ));
  78 //    G33_SETBMASK_REGL(MMADR, ADPA, 0x0c00); // Warning! Turns monitor OFF! Just testing mmio register reads/writes...
  79 //    D(bug("[G33]   ADPA %08x\n",G33_RD_REGL(MMADR, ADPA) ));
  80 //    G33_CLRBMASK_REGL(MMADR, ADPA, 0x0c00); // Warning! Turns monitor ON! Just testing mmio register reads/writes...
  81 //    D(bug("[G33]   ADPA %08x\n",G33_RD_REGL(MMADR, ADPA) ));
  82
  83         if ( G33_RD_REGL(MMADR, ADPA) & (1<<31) )
  84         D(bug("[G33]    Analog display port A enabled\n"));
  85         if ( G33_RD_REGL(MMADR, DDPBC) & (1<<31) )
  86         D(bug("[G33]    Digital display port B enabled\n"));;
  87         if ( G33_RD_REGL(MMADR, DDPCC) & (1<<31) )
  88         D(bug("[G33]    Digital display port C enabled\n"));;
  89
  90     D(bug("[G33]   VGACNTRL %08x\n",G33_RD_REGL(MMADR, VGACNTRL) ));
  91     G33_SETBMASK_REGL(MMADR, VGACNTRL, VGADisable); //Disable VGA
  92     D(bug("[G33]   VGACNTRL %08x\n",G33_RD_REGL(MMADR, VGACNTRL) ));
  93
  94     init_GMBus(sd);
  95 //    D(bug("[G33]   GMBUS status %04x\n",status_GMBus(sd))); // Testing hardware "semaphore"
  96 //    D(bug("[G33]   GMBUS status %04x\n",status_GMBus(sd)));
  97     return TRUE;
  98 }
  99
 100 AROS_UFH3(void, Enumerator,
 101     AROS_UFHA(struct Hook *,    hook,       A0),
 102     AROS_UFHA(OOP_Object *,     pciDevice,  A2),
 103     AROS_UFHA(APTR,             message,    A1))
 104 {
 105     AROS_USERFUNC_INIT
 106
 107     LIBBASETYPEPTR LIBBASE = (LIBBASETYPEPTR)hook->h_Data;
 108     struct staticdata *sd = &LIBBASE->sd;
 109
 110     IPTR VendorID, ProductID;
 111
 112     /* Get the ID's */
 113     OOP_GetAttr(pciDevice, aHidd_PCIDevice_VendorID, &VendorID);
 114     OOP_GetAttr(pciDevice, aHidd_PCIDevice_ProductID, &ProductID);
 115
 116
 117     /* Intel doesn't produce any addon gfx cards so it might be pointless to check if allready found intel chip */
 118     if( (IS_G33(ProductID) & (sd->pciG33 == NULL)) ){
 119         D(bug("[G33]   found (%04x:%04x)",VendorID, ProductID));
 120
 121 /*-------- DO NOT CHANGE/REMOVE -------------*/
 122         bug("\003\n");
 123 /*-------- DO NOT CHANGE/REMOVE -------------*/
 124
 125         APTR Base0, Base1, Base2, Base3;
 126         IPTR sizeBase0, sizeBase1, sizeBase2, sizeBase3;
 127         IPTR bus, dev, sub;
 128         IPTR BSM, MGGC, MSAC, sizeGTT, sizeMemory;
 129
 130         OOP_Object *pciDriver;
 131
 132         sd->Chipset.ProductID = ProductID;
 133         sd->Chipset.VendorID = VendorID;
 134         sd->pciG33 = pciDevice;
 135
 136         sizeGTT = 0;
 137         sizeMemory = 0;
 138
 139         struct pHidd_PCIDriver_MapPCI mappci,*msg = &mappci;
 140
 141         struct TagItem attrs[] = {
 142             { aHidd_PCIDevice_isIO,    FALSE }, /* Don't listen IO transactions */
 143             { aHidd_PCIDevice_isMEM,    TRUE }, /* Listen to MEM transactions */
 144             { aHidd_PCIDevice_isMaster, TRUE }, /* Can work in BusMaster */
 145             { TAG_DONE, 0UL },
 146         };
 147         OOP_SetAttrs(pciDevice, (struct TagItem*)&attrs);
 148
 149         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Driver, (APTR)&pciDriver);
 150         sd->pciDriver = pciDriver;
 151
 152         sd->mid_ReadLong = OOP_GetMethodID(IID_Hidd_PCIDriver, moHidd_PCIDriver_ReadConfigLong);
 153         sd->mid_ReadWord = OOP_GetMethodID(IID_Hidd_PCIDriver, moHidd_PCIDriver_ReadConfigWord);
 154
 155         /*
 156           Read some PCI config registers
 157         */
 158         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Bus, (APTR)&bus);
 159         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Dev, (APTR)&dev);
 160         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Sub, (APTR)&sub);
 161
 162         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base0, (APTR)&Base0);
 163         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size0, (APTR)&sizeBase0);
 164         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base1, (APTR)&Base1);
 165         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size1, (APTR)&sizeBase1);
 166         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base2, (APTR)&Base2);
 167         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size2, (APTR)&sizeBase2);
 168         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Base3, (APTR)&Base3);
 169         OOP_GetAttr(pciDevice, aHidd_PCIDevice_Size3, (APTR)&sizeBase3);
 170
 171         OOP_GetAttr(pciDevice, aHidd_PCIDevice_INTLine, &sd->G33IntLine);
 172
 173         MGGC = pciReadWord(sd, bus, dev, sub, 0x52);
 174         MGGC = pciReadWord(sd, 0, 0, 0, 0x52);    //Read from bridge
 175
 176         BSM = pciReadLong(sd, bus, dev, sub, 0x5c);
 177         sd->Chipset.StolenMemory = (APTR *)BSM;
 178
 179         MSAC = pciReadByte(sd, bus, dev, sub, 0x62);
 180         D(bug("        MSAC =%x\n",MSAC));
 181
 182         switch((MSAC & 0x6)) {
 183             case 0:
 184                 D(bug("        Gfx Aperture size 128MB\n"));
 185                 break;
 186             case 3:
 187                 D(bug("        Gfx Aperture size 256MB\n"));
 188                 break;
 189             case 6:
 190                 D(bug("        Gfx Aperture size 512MB\n"));
 191                 break;
 192             default:
 193                 D(bug("        Gfx Aperture size is illegal!\n"));
 194                 break;
 195         }
 196
 197                 switch ((MGGC & GTT_MASK)) {
 198                         case GTT_1M:
 199                                 sizeGTT = 1*(1024*1024);
 200                                 break;
 201                         case GTT_2M:
 202                                 sizeGTT = 2*(1024*1024);
 203                                 break;
 204                 }
 205         sd->Chipset.sizeGTT = sizeGTT;
 206
 207         switch ((MGGC & STOLEN_MEMORY_MASK)) {
 208             case STOLEN_MEMORY_1M:
 209                 sizeMemory = 1*(1024*1024);
 210                 break;
 211             case STOLEN_MEMORY_4M:
 212                 sizeMemory = 4*(1024*1024);
 213                 break;
 214             case STOLEN_MEMORY_8M:
 215                 sizeMemory = 8*(1024*1024);
 216                 break;
 217             case STOLEN_MEMORY_16M:
 218                 sizeMemory = 16*(1024*1024);
 219                 break;
 220             case STOLEN_MEMORY_32M:
 221                 sizeMemory = 32*(1024*1024);
 222                 break;
 223             case STOLEN_MEMORY_48M:
 224                 sizeMemory = 48*(1024*1024);
 225                 break;
 226             case STOLEN_MEMORY_64M:
 227                 sizeMemory = 64*(1024*1024);
 228                 break;
 229             case STOLEN_MEMORY_96M:
 230                 sizeMemory = 96*(1024*1024);
 231                 break;
 232             case STOLEN_MEMORY_128M:
 233                 sizeMemory = 128*(1024*1024);
 234                 break;
 235             case STOLEN_MEMORY_160M:
 236                 sizeMemory = 160*(1024*1024);
 237                 break;
 238             case STOLEN_MEMORY_224M:
 239                 sizeMemory = 224*(1024*1024);
 240                 break;
 241             case STOLEN_MEMORY_256M:
 242                 sizeMemory = 256*(1024*1024);
 243                 break;
 244             case STOLEN_MEMORY_352M:
 245                 sizeMemory = 352*(1024*1024);
 246                 break;
 247         }
 248         sd->Chipset.sizeStolenMemory = sizeMemory;
 249
 250         D(bug("        Bus =%x, Dev =%x, Sub =%x\n",bus, dev, sub));
 251         D(bug("        MGGC      =%x\n\n",MGGC));
 252         D(bug("        MMADR     =%x (%x)\n",Base0, sizeBase0));   //MMADR
 253         D(bug("        IOBAR     =%x (%x)\n",Base1, sizeBase1));   //IOBAR
 254         D(bug("        GMADR     =%x (%dMB)\n",Base2, sizeBase2/(1024*1024)));   //GMADR
 255         D(bug("        GTTADR    =%x (%dMB)\n",Base3, sizeBase3/(1024*1024)));   //GTTADR
 256         D(bug("        IRQ       =%d\n",sd->G33IntLine));
 257
 258         D(bug("        StolenMem =%p (%dMB)\n",sd->Chipset.StolenMemory, sd->Chipset.sizeStolenMemory/(1024*1024)));
 259         D(bug("        %dMB for video memory\n",sd->Chipset.sizeVMemory/(1024*1024)));
 260         /*
 261           Map the PCI address space to CPU address space
 262         */
 263         mappci.mID = OOP_GetMethodID(IID_Hidd_PCIDriver, moHidd_PCIDriver_MapPCI);
 264         mappci.PCIAddress = Base0;
 265         mappci.Length = sizeBase0;
 266         sd->Chipset.MMADR = (APTR)OOP_DoMethod(pciDriver, (OOP_Msg)msg);
 267
 268         Chip_Init(sd);
 269
 270     }else{
 271         D(bug("[G33]   not supported (%04x:%04x)\n",VendorID, ProductID));
 272     }
 273
 274     AROS_USERFUNC_EXIT
 275 }
 276
 277 static int IntelG33_Init(LIBBASETYPEPTR LIBBASE) {
 278     D(bug("[G33] IntelG33 hidd init\n"));
 279
 280     struct staticdata *sd = &LIBBASE->sd;
 281
 282     sd->memPool = CreatePool(MEMF_CLEAR | MEMF_PUBLIC | MEMF_SEM_PROTECTED, 8192, 4096);
 283     if ((sd->memPool == NULL))
 284         return FALSE;
 285
 286     struct BootLoaderBase   *BootLoaderBase;
 287     BootLoaderBase = OpenResource("bootloader.resource");
 288
 289     /*
 290         Use default of 256MB for video memory, unless user want's less, then go down to 32MB
 291     */
 292     sd->Chipset.sizeVMemory = 256*(1024*1024);
 293
 294     if (BootLoaderBase != NULL) {
 295         struct List *list;
 296         struct Node *node;
 297
 298         list = (struct List *)GetBootInfo(BL_Args);
 299         if (list) {
 300             ForeachNode(list, node) {
 301                 if (strncmp(node->ln_Name, "iGfxMem", 7) == 0) {
 302                     if (strstr(node->ln_Name, "=128MB")) {
 303                         sd->Chipset.sizeVMemory = 128*(1024*1024);
 304                     }
 305                     if (strstr(node->ln_Name, "=64MB")) {
 306                         sd->Chipset.sizeVMemory = 64*(1024*1024);
 307                     }
 308                     if (strstr(node->ln_Name, "=32MB")) {
 309                         sd->Chipset.sizeVMemory = 32*(1024*1024);
 310                     }
 311                 }
 312             }
 313         }
 314     }
 315
 316         InitSemaphore(&sd->Chipset.Locks.DPMS);
 317
 318     struct OOP_ABDescr attrbases[] = {
 319         { (STRPTR)IID_Hidd_PCIDevice, &HiddPCIDeviceAttrBase },
 320         { (STRPTR)IID_Hidd_BitMap,    &HiddBitMapAttrBase },
 321         { (STRPTR)IID_Hidd_PixFmt,    &HiddPixFmtAttrBase },
 322         { (STRPTR)IID_Hidd_Sync,      &HiddSyncAttrBase },
 323         { (STRPTR)IID_Hidd_Gfx,       &HiddGfxAttrBase },
 324         { (STRPTR)IID_Hidd_PlanarBM,  &__IHidd_PlanarBM },
 325         { (STRPTR)IID_Hidd_G33BitMap, &HiddG33BitMapAttrBase },
 326         { NULL, NULL }
 327     };
 328
 329     {
 330         if (OOP_ObtainAttrBases(attrbases)) {
 331             sd->pci = OOP_NewObject(NULL, CLID_Hidd_PCI, NULL);
 332             if (sd->pci) {
 333                 struct Hook FindHook = {
 334                     h_Entry:    (IPTR (*)())Enumerator,
 335                     h_Data:     LIBBASE,
 336                 };
 337                 struct TagItem Requirements[] = {
 338                     { tHidd_PCI_Interface, 0x00 },
 339                     { tHidd_PCI_Class,     0x03 },
 340                     { tHidd_PCI_SubClass,  0x00 },
 341                     { tHidd_PCI_VendorID,  INTEL_VENDOR_ID },
 342                     { TAG_DONE, 0UL }
 343                 };
 344
 345                 HIDD_PCI_EnumDevices(LIBBASE->sd.pci, &FindHook, Requirements);
 346
 347                 if (sd->pciG33 != NULL) {
 348
 349                     OOP_Object *irq = OOP_NewObject(NULL, CLID_Hidd_IRQ, NULL);
 350
 351                     sd->G33IRQ = AllocVec(sizeof (HIDDT_IRQ_Handler), MEMF_CLEAR | MEMF_PUBLIC);
 352
 353                     if (sd->G33IRQ) {
 354                         struct pHidd_IRQ_AddHandler __msg__ = {
 355                             mID:         OOP_GetMethodID(CLID_Hidd_IRQ, moHidd_IRQ_AddHandler),
 356                             handlerinfo: sd->G33IRQ,
 357                             id:          sd->G33IntLine,
 358                         }, *msg = &__msg__;
 359
 360                         sd->G33IRQ->h_Node.ln_Pri = 0;
 361                         sd->G33IRQ->h_Node.ln_Name = "G33 Int";
 362                         sd->G33IRQ->h_Code = IntelG33_int;
 363                         sd->G33IRQ->h_Data = sd;
 364
 365                         OOP_DoMethod(irq, (OOP_Msg)msg);
 366                         OOP_DisposeObject(irq);
 367                         D(bug("[G33]   Created interrupt handler\n"));
 368                         D(bug("[G33] IntelG33 hidd init (exit TRUE)\n"));
 369                         return TRUE;
 370                     }
 371                 }
 372                 OOP_DisposeObject(sd->pci);
 373             }
 374             OOP_ReleaseAttrBases(attrbases);
 375         }
 376     }
 377
 378     DeletePool(sd->memPool);
 379     D(bug("[G33] IntelG33 hidd init (exit FALSE)\n"));
 380     return FALSE;
 381 }
 382
 383 ADD2INITLIB(IntelG33_Init, 0)