Initial import of work-in-progress of Poseidon port.
[cake.git] / rom / usb / pciusb / pciusb.h
blob214228808007ae78b4376fa6d0432ed9ed3d1f12
1 #ifndef PCIUSB_H
2 #define PCIUSB_H
4 /*
5 *----------------------------------------------------------------------------
6 * Includes for pciusb.device
7 *----------------------------------------------------------------------------
8 * By Chris Hodges <chrisly@platon42.de>
9 */
11 #include LC_LIBDEFS_FILE
13 #include <aros/libcall.h>
14 #include <aros/asmcall.h>
15 #include <aros/symbolsets.h>
17 #include <exec/types.h>
18 #include <exec/lists.h>
19 #include <exec/memory.h>
20 #include <exec/libraries.h>
21 #include <exec/interrupts.h>
22 #include <exec/semaphores.h>
23 #include <exec/execbase.h>
24 #include <exec/devices.h>
25 #include <exec/io.h>
26 #include <exec/ports.h>
27 #include <exec/errors.h>
28 #include <exec/resident.h>
29 #include <exec/initializers.h>
30 #include <dos/dos.h>
32 #include <devices/timer.h>
33 #include <utility/utility.h>
35 #include <devices/usbhardware.h>
36 #include <devices/newstyle.h>
38 #include <oop/oop.h>
39 #include <hidd/irq.h>
41 #include "debug.h"
43 /* Reply the iorequest with success */
44 #define RC_OK 0
46 /* Magic cookie, don't set error fields & don't reply the ioreq */
47 #define RC_DONTREPLY -1
49 #define MAX_ROOT_PORTS 16
51 #define PCI_CLASS_SERIAL_USB 0x0c03
53 /* The unit node - private */
54 struct PCIUnit
56 struct Unit hu_Unit;
57 LONG hu_UnitNo;
59 struct PCIDevice *hu_Device; /* Uplink */
60 struct MsgPort *hu_MsgPort;
61 struct timerequest *hu_TimerReq; /* Timer I/O Request */
62 struct timerequest hu_LateIOReq; /* Timer I/O Request */
63 struct MsgPort hu_LateMsgPort;
64 struct timerequest hu_NakTimeoutReq;
65 struct MsgPort hu_NakTimeoutMsgPort;
66 struct Interrupt hu_NakTimeoutInt;
68 BOOL hu_UnitAllocated; /* Unit opened */
70 ULONG hu_DevID; /* Device ID (BusID+DevNo) */
71 struct List hu_Controllers; /* List of controllers */
72 UWORD hu_RootHub11Ports;
73 UWORD hu_RootHub20Ports;
74 UWORD hu_RootHubPorts;
75 UWORD hu_RootHubAddr; /* Root Hub Address */
76 UWORD hu_RootPortChanges; /* Merged root hub changes */
77 ULONG hu_FrameCounter; /* Common frame counter */
78 struct List hu_RHIOQueue; /* Root Hub Pending IO Requests */
80 struct PCIController *hu_PortMap11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 controller */
81 struct PCIController *hu_PortMap20[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 2.0 controller */
82 UBYTE hu_PortNum11[MAX_ROOT_PORTS]; /* Maps from Global Port to USB 1.1 companion controller port */
83 UBYTE hu_EhciOwned[MAX_ROOT_PORTS]; /* TRUE, if currently owned by EHCI */
85 struct PCIController *hu_DevControllers[128]; /* maps from Device address to controller */
86 struct IOUsbHWReq *hu_DevBusyReq[128*16*2]; /* pointer to io assigned to the Endpoint */
87 ULONG hu_NakTimeoutFrame[128*16*2]; /* Nak Timeout framenumber */
88 UBYTE hu_DevDataToggle[128*16*2]; /* Data toggle bit for endpoints */
91 #define HCITYPE_UHCI 0x00
92 #define HCITYPE_OHCI 0x10
93 #define HCITYPE_EHCI 0x20
95 struct PCIController
97 struct Node hc_Node;
98 struct PCIDevice *hc_Device; /* Uplink */
99 struct PCIUnit *hc_Unit; /* Uplink */
101 OOP_Object *hc_PCIDeviceObject;
102 ULONG hc_DevID;
103 UWORD hc_FunctionNum;
104 UWORD hc_HCIType;
105 UWORD hc_NumPorts;
106 BOOL hc_BoardAllocated;
107 BOOL hc_Online;
109 volatile APTR hc_RegBase;
111 APTR hc_PCIMem;
112 ULONG hc_PCIMemSize;
113 ULONG hc_PCIVirtualAdjust;
114 IPTR hc_PCIIntLine;
115 HIDDT_IRQ_Handler hc_PCIIntHandler;
116 ULONG hc_PCIIntEnMask;
118 ULONG *hc_UhciFrameList;
119 struct UhciQH *hc_UhciQHPool;
120 struct UhciTD *hc_UhciTDPool;
122 struct UhciQH *hc_UhciCtrlQH;
123 struct UhciQH *hc_UhciBulkQH;
124 struct UhciQH *hc_UhciIntQH[9];
125 struct UhciTD *hc_UhciIsoTD;
126 struct UhciQH *hc_UhciTermQH;
128 ULONG hc_EhciUsbCmd;
129 ULONG *hc_EhciFrameList;
130 struct EhciQH *hc_EhciQHPool;
131 struct EhciTD *hc_EhciTDPool;
133 struct EhciQH *hc_EhciAsyncQH;
134 struct EhciQH *hc_EhciIntQH[11];
135 struct EhciQH *hc_EhciTermQH;
136 volatile BOOL hc_AsyncAdvanced;
137 struct EhciQH *hc_EhciAsyncFreeQH;
138 struct EhciTD *hc_ShortPktEndTD;
140 struct OhciED *hc_OhciCtrlHeadED;
141 struct OhciED *hc_OhciCtrlTailED;
142 struct OhciED *hc_OhciBulkHeadED;
143 struct OhciED *hc_OhciBulkTailED;
144 struct OhciED *hc_OhciIntED[5];
145 struct OhciED *hc_OhciTermED;
146 struct OhciTD *hc_OhciTermTD;
147 struct OhciHCCA *hc_OhciHCCA;
148 struct OhciED *hc_OhciEDPool;
149 struct OhciTD *hc_OhciTDPool;
150 struct OhciED *hc_OhciAsyncFreeED;
151 ULONG hc_OhciDoneQueue;
152 struct List hc_OhciRetireQueue;
154 ULONG hc_FrameCounter;
155 struct List hc_TDQueue;
156 struct List hc_PeriodicTDQueue;
157 struct List hc_CtrlXFerQueue;
158 struct List hc_IntXFerQueue;
159 struct List hc_IsoXFerQueue;
160 struct List hc_BulkXFerQueue;
162 struct Interrupt hc_CompleteInt;
164 UBYTE hc_PortNum20[MAX_ROOT_PORTS]; /* Global Port number the local controller port corresponds with */
166 UWORD hc_PortChangeMap[MAX_ROOT_PORTS]; /* Port Change Map */
170 /* The device node - private
172 struct PCIDevice
174 struct Library hd_Library; /* standard */
175 UWORD hd_Flags; /* various flags */
177 struct UtilityBase *hd_UtilityBase; /* for tags etc */
179 struct List hd_TempHCIList;
180 OOP_Object *hd_PCIHidd;
181 OOP_Object *hd_IRQHidd;
182 OOP_AttrBase hd_HiddAB;
183 OOP_AttrBase hd_HiddPCIDeviceAB;
184 OOP_AttrBase hd_HiddUSBDeviceAB;
185 OOP_AttrBase hd_HiddUSBHubAB;
186 OOP_AttrBase hd_HiddUSBDrvAB;
188 BOOL hd_ScanDone; /* PCI scan done? */
189 APTR hd_MemPool; /* Memory Pool */
191 struct Device *hd_TimerBase; /* timer device base */
193 struct List hd_Units; /* List of units */
196 #endif /* PCIUSB_H */