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Added a work-around for SATA controllers that seem to pretend to have two
[cake.git] / arch / common / ata.device / lowlevel.c
blob63e269cc3ce8a213d012ef13375264d5fe498360
1 /*
2 Copyright � 2004-2009, The AROS Development Team. All rights reserved
3 $Id$
4
5 Desc:
6 Lang: English
7 */
8
9 /*
10 * PARTIAL CHANGELOG:
11 * DATE NAME ENTRY
12 * ---------- ------------------ -------------------------------------------------------------------
13 * 2006-12-20 T. Wiszkowski Updated ATA Packet Interface to handle ATAPI/SCSI Commands
14 * 2008-01-06 T. Wiszkowski Corrected and completed ATA Packet Interface handling. PIO transfers fully operational.
15 * 2008-01-07 T. Wiszkowski Added initial DMA support for Direct SCSI commands. Corrected atapi
16 * READ and WRITE commands to pass proper transfer size to the atapi_SendPacket
17 * as discovered by mschulz
18 * 2008-01-25 T. Wiszkowski Rebuilt, rearranged and partially fixed 60% of the code here
19 * Enabled implementation to scan for other PCI IDE controllers
20 * Implemented ATAPI Packet Support for both read and write
21 * Corrected ATAPI DMA handling
22 * Fixed major IDE enumeration bugs severely handicapping transfers with more than one controller
23 * Compacted source and implemented major ATA support procedure
24 * Improved DMA and Interrupt management
25 * Removed obsolete code
26 * 2008-01-26 T. Wiszkowski Restored 32bit io
27 * Removed memory dump upon RequestSense
28 * 2008-02-08 T. Wiszkowski Fixed DMA accesses for direct scsi devices,
29 * Corrected IO Areas to allow ATA to talk to PCI controllers
30 * 2008-03-03 T. Wiszkowski Added drive reselection + setup delay on Init
31 * 2008-03-29 T. Wiszkowski Restored error on 64bit R/W access to non-64bit capable atapi devices
32 * cleared debug flag
33 * 2008-03-30 T. Wiszkowski Added workaround for interrupt collision handling; fixed SATA in LEGACY mode.
34 * nForce and Intel SATA chipsets should now be operational (nForce confirmed)
35 * 2008-03-31 M. Schulz The ins/outs function definitions used only in case of x86 and x86_64 architectures.
36 * Otherwise, function declaratons are emitted.
37 * 2008-04-01 M. Schulz Use C functions ata_ins[wl] ata_outs[wl]
38 * 2008-04-03 T. Wiszkowski Fixed IRQ flood issue, eliminated and reduced obsolete / redundant code
39 * 2008-04-05 T. Wiszkowski Improved IRQ management
40 * 2008-04-07 T. Wiszkowski Changed bus timeout mechanism
41 * increased failure timeout values to cover rainy day scenarios
42 * 2008-04-20 T. Wiszkowski Corrected the flaw in drive identification routines leading to ocassional system hangups
43 * 2008-05-11 T. Wiszkowski Remade the ata trannsfers altogether, corrected the pio/irq handling
44 * medium removal, device detection, bus management and much more
45 * 2008-05-12 P. Fedin Explicitly enable multisector transfers on the drive
46 * 2008-05-18 T. Wiszkowski Added extra checks to prevent duplicating drive0 in drive0 only configs
47 * 2008-05-18 T. Wiszkowski Replaced static C/H/S with more accurate calcs, should make HDTB and other tools see right capacity
48 * 2008-05-19 T. Wiszkowski Updated ATA DMA handling and transfer wait operation to allow complete transfer before dma_StopDMA()
49 * 2008-05-30 T. Wiszkowski Corrected CHS calculation for larger disks
50 * 2008-06-03 K. Smiechowicz Added 400ns delay in ata_WaitBusyTO before read of device status.
51 * 2008-06-25 P. Fedin Added "nomulti" flag
52 * PIO works correctly again
53 * 2008-11-28 T. Wiszkowski updated test unit ready to suit individual taste of hw manufacturers
54 * 2009-01-20 J. Koivisto Modified bus reseting scheme
55 * 2009-02-04 T. Wiszkowski Disabled ATA debug on official builds
56 * 2009-03-05 T. Wiszkowski remade timeouts, added timer-based and benchmark-based delays.
57 */
58 /*
59 * TODO:
60 * - put a critical section around DMA transfers (shared dma channels)
61 */
62
63 #define DEBUG 0
64 // use #define xxx(a) D(a) to enable particular sections.
65 #define DIRQ(a) D(a)
66 #define DIRQ_MORE(a) D(a)
67 #define DUMP(a)
68 #define DATA(a) D(a)
69 #define DATAPI(a) D(a)
70 #define DINIT(a) D(a)
71
72 #include <aros/debug.h>
73 #include <exec/types.h>
74 #include <exec/exec.h>
75 #include <exec/resident.h>
76 #include <utility/utility.h>
77 #include <oop/oop.h>
78
79 #include <proto/exec.h>
80 #include <devices/timer.h>
81
82 #include <asm/io.h>
83
84 #include "ata.h"
85 #include "timer.h"
86
87
88
89 /*
90 Prototypes of static functions from lowlevel.c. I do not want to make them
91 non-static as I'd like to remove as much symbols from global table as possible.
92 Besides some of this functions could conflict with old ide.device or any other
93 device.
94 */
95 static ULONG ata_ReadSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
96 static ULONG ata_ReadSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
97 static ULONG ata_ReadMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
98 static ULONG ata_ReadMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
99 static ULONG ata_ReadDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
100 static ULONG ata_ReadDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
101 static ULONG ata_WriteSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
102 static ULONG ata_WriteSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
103 static ULONG ata_WriteMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
104 static ULONG ata_WriteMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
105 static ULONG ata_WriteDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
106 static ULONG ata_WriteDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
107 static ULONG ata_Eject(struct ata_Unit *);
108 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq, UBYTE *stout);
109
110 static ULONG atapi_EndCmd(struct ata_Unit *unit);
111
112 static ULONG atapi_Read(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
113 static ULONG atapi_Write(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
114 static ULONG atapi_Eject(struct ata_Unit *);
115
116 static void common_SetBestXferMode(struct ata_Unit* unit);
117
118 /*
119 Again piece of code which shouldn't be here. Geee. After removing all this
120 asm constrictuins this ata.device will really deserve for location in
121 /arch/common
122 */
123 /*
124 * having an x86 assembly here i dare to assume that this is meant to be
125 * an x86[_64] device only.
126 *
127 * Not anymore.
128 *
129 * This functions will stay here for some time *IF* and only if the code is compiled for
130 * x86 or x86_64 architecture. Otherwise, function declarations will be emitted and the
131 * one who ports the driver will be reponsible for adding the missing code.
132 */
133
134 /*
135 * the outsl and insl commands improperly assumed that every transfer is sized to multiple of four
136 */
137 #if defined(__i386__) || defined(__x86_64__)
138
139 static VOID ata_insw(APTR address, UWORD port, ULONG count)
140 {
141 insw(port, address, count >> 1);
142 }
143
144 static VOID ata_insl(APTR address, UWORD port, ULONG count)
145 {
146 if (count & 2)
147 insw(port, address, count >> 1);
148 else
149 insl(port, address, count >> 2);
150 }
151
152 static VOID ata_outsw(APTR address, UWORD port, ULONG count)
153 {
154 outsw(port, address, count >> 1);
155 }
156
157 static VOID ata_outsl(APTR address, UWORD port, ULONG count)
158 {
159 if (count & 2)
160 outsw(port, address, count >> 1);
161 else
162 outsl(port, address, count >> 2);
163 }
164
165 #else
166 extern VOID ata_insw(APTR address, UWORD port, ULONG count);
167 extern VOID ata_insl(APTR address, UWORD port, ULONG count);
168 extern VOID ata_outsw(APTR address, UWORD port, ULONG count);
169 extern VOID ata_outsl(APTR address, UWORD port, ULONG count);
170 #endif
171
172 static void dump(APTR mem, ULONG len)
173 {
174 register int i,j;
175 for (j=0; j<(len+15)>>4; ++j)
176 {
177 bug("[ATA ] %06lx: ", j<<4);
178
179 for (i=0; i<len-(j<<4); i++)
180 {
181 bug("%02lx ", ((unsigned char*)mem)[(j<<4)|i]);
182 if (i == 15)
183 break;
184 }
185
186 for (i=0; i<len-(j<<4); i++)
187 {
188 unsigned char c = ((unsigned char*)mem)[(j<<4)|i];
189
190 bug("%c", c >= 0x20 ? c<=0x7f ? c : '.' : '.');
191 if (i == 15)
192 break;
193 }
194 bug("\n");
195 }
196 }
197
198 static void ata_strcpy(const UBYTE *str1, UBYTE *str2, ULONG size)
199 {
200 register int i = size;
201
202 while (size--)
203 {
204 str2[size^1] = str1[size];
205 }
206
207 while (i--)
208 {
209 if (str2[i] <= ' ')
210 str2[i] = 0;
211 }
212 }
213
214
215 /*
216 * a STUB function for commands not supported by this particular device
217 */
218 static ULONG ata_STUB(struct ata_Unit *au)
219 {
220 bug("[ATA%02ld] CALLED STUB FUNCTION (GENERIC). THIS OPERATION IS NOT "
221 "SUPPORTED BY DEVICE\n", au->au_UnitNum);
222 return CDERR_NOCMD;
223 }
224
225 static ULONG ata_STUB_IO32(struct ata_Unit *au, ULONG blk, ULONG len, APTR buf, ULONG* act)
226 {
227 bug("[ATA%02ld] CALLED STUB FUNCTION (IO32). THIS OPERATION IS NOT "
228 "SUPPORTED BY DEVICE\n", au->au_UnitNum);
229 return CDERR_NOCMD;
230 }
231
232 static ULONG ata_STUB_IO64(struct ata_Unit *au, UQUAD blk, ULONG len, APTR buf, ULONG* act)
233 {
234 bug("[ATA%02ld] CALLED STUB FUNCTION -- IO ACCESS TO BLOCK %08lx:%08lx, LENGTH %08lx. THIS OPERATION IS NOT SUPPORTED BY DEVICE\n", au->au_UnitNum, (blk >> 32), (blk & 0xffffffff), len);
235 return CDERR_NOCMD;
236 }
237
238 static ULONG ata_STUB_SCSI(struct ata_Unit *au, struct SCSICmd* cmd)
239 {
240 bug("[ATA%02ld] CALLED STUB FUNCTION. THIS OPERATION IS NOT SUPPORTED BY DEVICE\n", au->au_UnitNum);
241 return CDERR_NOCMD;
242 }
243
244 inline BOOL ata_SelectUnit(struct ata_Unit* unit)
245 {
246 ata_out(unit->au_DevMask, ata_DevHead, unit->au_Bus->ab_Port);
247
248 do
249 {
250 ata_WaitNano(400);
251 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
252 }
253 while (0 != (ATAF_BUSY & ata_ReadStatus(unit->au_Bus)));
254
255 return TRUE;
256 }
257
258 inline struct ata_Unit* ata_GetSelectedUnit(struct ata_Bus* bus)
259 {
260 register int id = (ata_in(ata_DevHead, bus->ab_Port) & 0x10) >> 4;
261 return bus->ab_Units[id];
262 }
263
264 UBYTE ata_ReadStatus(struct ata_Bus *bus)
265 {
266 return ata_in(ata_Status, bus->ab_Port);
267 }
268
269 UBYTE ata_ReadAltStatus(struct ata_Bus *bus)
270 {
271 return ata_in(ata_AltStatus, bus->ab_Alt);
272 }
273
274 /*
275 * handle IRQ; still fast and efficient, supposed to verify if this irq is for us and take adequate steps
276 * part of code moved here from ata.c to reduce containment
277 */
278 void ata_IRQSignalTask(struct ata_Bus *bus)
279 {
280 bus->ab_IntCnt++;
281 Signal(bus->ab_Task, 1UL << bus->ab_SleepySignal);
282 }
283
284 void ata_HandleIRQ(struct ata_Bus *bus)
285 {
286 struct ata_Unit *unit = ata_GetSelectedUnit(bus);
287 UBYTE status = ata_ReadStatus(bus);
288
289 /*
290 * don't waste your time on checking other devices.
291 * pass irq ONLY if task is expecting one;
292 */
293 if ((unit != NULL) && (0 != bus->ab_HandleIRQ)
294 && ((status & ATAF_BUSY) == 0))
295 {
296 /*
297 * ok, we have a routine to handle any form of transmission etc.
298 */
299 DIRQ(bug("[ATA ] IRQ: Calling dedicated handler... \n"));
300 bus->ab_HandleIRQ(unit, status);
301
302 /*
303 * Acknowledge DMA interrupt bit (some controllers require this for
304 * all interrupt types)
305 */
306 if (unit->au_DMAPort != 0)
307 ata_out(ata_in(dma_Status, unit->au_DMAPort) |
308 DMAF_Error | DMAF_Interrupt, dma_Status, unit->au_DMAPort);
309
310 return;
311 }
312
313 DIRQ_MORE({
314 /*
315 * if we got *here* then device is most likely not expected to have an irq.
316 */
317 bug("[ATA%02ld] IRQ: Checking busy flag: ", unit->au_UnitNum);
318
319 if (0 == (ATAF_BUSY & status))
320 {
321 bug("device ready. Dumping details:\n");
322
323 bug("[ATA ] STATUS: %02lx\n", status);
324 bug("[ATA ] ALT STATUS: %02lx\n", ata_in(ata_AltStatus, bus->ab_Alt));
325 bug("[ATA ] ERROR: %02lx\n", ata_in(ata_Error, bus->ab_Port));
326 bug("[ATA ] IRQ: REASON: %02lx\n", ata_in(atapi_Reason, bus->ab_Port));
327 }
328 else
329 {
330 bug("device still busy. ignoring irq.\n");
331 }
332 });
333 }
334
335 void ata_IRQSetHandler(struct ata_Unit *unit, void (*handler)(struct ata_Unit*, UBYTE), APTR piomem, ULONG blklen, ULONG piolen)
336 {
337 if (NULL != handler)
338 unit->au_cmd_error = 0;
339
340 unit->au_cmd_data = piomem;
341 unit->au_cmd_length = (piolen < blklen) ? piolen : blklen;
342 unit->au_cmd_total = piolen;
343 unit->au_Bus->ab_HandleIRQ = handler;
344 }
345
346 void ata_IRQNoData(struct ata_Unit *unit, UBYTE status)
347 {
348 if (status & ATAF_BUSY)
349 return;
350
351 if ((unit->au_cmd_error == 0) && (status & ATAF_ERROR))
352 unit->au_cmd_error = HFERR_BadStatus;
353
354 DIRQ(bug("[ATA%02ld] IRQ: NoData - done; status %02lx.\n", unit->au_UnitNum, status));
355 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
356 ata_IRQSignalTask(unit->au_Bus);
357 }
358
359 void ata_IRQPIORead(struct ata_Unit *unit, UBYTE status)
360 {
361 if (status & ATAF_DATAREQ) {
362 DIRQ(bug("[ATA ] IRQ: PIOReadData - DRQ.\n"));
363 unit->au_ins(unit->au_cmd_data, unit->au_Bus->ab_Port, unit->au_cmd_length);
364
365 /*
366 * indicate it's all done here
367 */
368 unit->au_cmd_data += unit->au_cmd_length;
369 unit->au_cmd_total -= unit->au_cmd_length;
370 if (unit->au_cmd_total) {
371 if (unit->au_cmd_length > unit->au_cmd_total)
372 unit->au_cmd_length = unit->au_cmd_total;
373 return;
374 }
375 DIRQ(bug("[ATA ] IRQ: PIOReadData - transfer completed.\n"));
376 }
377 ata_IRQNoData(unit, status);
378 }
379
380 void ata_PIOWriteBlk(struct ata_Unit *unit)
381 {
382 unit->au_outs(unit->au_cmd_data, unit->au_Bus->ab_Port, unit->au_cmd_length);
383
384 /*
385 * indicate it's all done here
386 */
387 unit->au_cmd_data += unit->au_cmd_length;
388 unit->au_cmd_total -= unit->au_cmd_length;
389 if (unit->au_cmd_length > unit->au_cmd_total)
390 unit->au_cmd_length = unit->au_cmd_total;
391 }
392
393 void ata_IRQPIOWrite(struct ata_Unit *unit, UBYTE status)
394 {
395 if (status & ATAF_DATAREQ) {
396 DIRQ(bug("[ATA ] IRQ: PIOWriteData - DRQ.\n"));
397 ata_PIOWriteBlk(unit);
398 return;
399 }
400 DIRQ(bug("[ATA ] IRQ: PIOWriteData - done.\n"));
401 ata_IRQNoData(unit, status);
402 }
403
404 void ata_IRQDMAReadWrite(struct ata_Unit *au, UBYTE status)
405 {
406 UBYTE stat = ata_in(dma_Status, au->au_DMAPort);
407 DIRQ(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %02lx\n", au->au_UnitNum, status, stat));
408
409 if (0 == (stat & DMAF_Interrupt))
410 {
411 bug("[ATA ] IRQ: Fake IRQ.\n");
412 }
413 else if ((status & ATAF_ERROR) || (stat & DMAF_Error))
414 {
415 /* This is turned on in order to help Phantom - Pavel Fedin <sonic_amiga@rambler.ru> */
416 bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %02lx\n", au->au_UnitNum, status, stat);
417 bug("[ATA%02ld] IRQ: ERROR %02lx\n", au->au_UnitNum, ata_in(atapi_Error, au->au_Bus->ab_Port));
418 bug("[ATA ] IRQ: DMA Failed.\n");
419 au->au_cmd_error = HFERR_DMA;
420 ata_IRQNoData(au, status);
421 }
422 else if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
423 {
424 DIRQ(bug("[ATA ] IRQ: DMA Done.\n"));
425 ata_IRQNoData(au, status);
426 }
427 }
428
429 void ata_IRQPIOReadAtapi(struct ata_Unit *unit, UBYTE status)
430 {
431 ULONG port = unit->au_Bus->ab_Port;
432 ULONG size = 0;
433 LONG remainder = 0;
434 UBYTE reason = ata_in(atapi_Reason, port);
435 DIRQ(bug("[DSCSI] Current status: %ld during READ\n", reason));
436
437 /* have we failed yet? */
438 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
439 ata_IRQNoData(unit, status);
440 if (status & ATAF_ERROR)
441 {
442 ata_IRQNoData(unit, status);
443 return;
444 }
445
446 /* anything for us please? */
447 if (ATAPIF_READ != (reason & ATAPIF_MASK))
448 return;
449
450 size = ata_in(atapi_ByteCntH, port) << 8 | ata_in(atapi_ByteCntL, port);
451 DIRQ(bug("[ATAPI] IRQ: data available for read (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
452
453 if (size > unit->au_cmd_total)
454 {
455 bug("[ATAPI] IRQ: CRITICAL! MORE DATA OFFERED THAN STORAGE CAN TAKE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total);
456 remainder = size - unit->au_cmd_total;
457 size = unit->au_cmd_total;
458 }
459
460 unit->au_ins(unit->au_cmd_data, port, size);
461 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
462 unit->au_cmd_total -= size;
463
464 DIRQ(bug("[ATAPI] IRQ: %lu bytes read.\n", size));
465
466 for (; remainder > 0; remainder -= 2)
467 unit->au_ins(&size, port, 2);
468
469 if (unit->au_cmd_total == 0)
470 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
471 }
472
473 void ata_IRQPIOWriteAtapi(struct ata_Unit *unit, UBYTE status)
474 {
475 ULONG port = unit->au_Bus->ab_Port;
476 ULONG size = 0;
477 UBYTE reason = ata_in(atapi_Reason, port);
478 DIRQ(bug("[ATAPI] IRQ: Current status: %ld during WRITE\n", reason));
479
480 /* have we failed yet? */
481 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
482 ata_IRQNoData(unit, status);
483 if (status & ATAF_ERROR)
484 {
485 ata_IRQNoData(unit, status);
486 return;
487 }
488
489 /* anything for us please? */
490 if (ATAPIF_WRITE != (reason & ATAPIF_MASK))
491 return;
492
493 size = ata_in(atapi_ByteCntH, port) << 8 | ata_in(atapi_ByteCntL, port);
494 DIRQ(bug("[ATAPI] IRQ: data requested for write (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
495
496 if (size > unit->au_cmd_total)
497 {
498 bug("[ATAPI] IRQ: CRITICAL! MORE DATA REQUESTED THAN STORAGE CAN GIVE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total);
499 size = unit->au_cmd_total;
500 }
501
502 unit->au_outs(unit->au_cmd_data, port, size);
503 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
504 unit->au_cmd_total -= size;
505
506 DIRQ(bug("[ATAPI] IRQ: %lu bytes written.\n", size));
507
508 if (unit->au_cmd_total == 0)
509 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
510 }
511
512 /*
513 * wait for timeout or drive ready
514 * polling-in-a-loop, but it should be safe to remove this already
515 */
516 BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq, UBYTE *stout)
517 {
518 UBYTE status;
519 ULONG sigs = SIGBREAKF_CTRL_C;
520 ULONG step = 0;
521 BOOL res = TRUE;
522
523 sigs |= (irq ? (1 << unit->au_Bus->ab_SleepySignal) : 0);
524
525 /*
526 * clear up all old signals
527 */
528 SetSignal(0, sigs);
529
530 /*
531 * set up bus timeout
532 */
533 Disable();
534 unit->au_Bus->ab_Timeout = tout;
535 Enable();
536
537 /*
538 * this loop may experience one of two scenarios
539 * 1) we get a valid irq and the drive wanted to let us know that it's ready
540 * 2) we get an invalid irq due to some collisions. We may still want to go ahead and get some extra irq breaks
541 * this would reduce system load a little
542 */
543
544 do
545 {
546 /*
547 * delay the check - this was found needed for some hardware
548 */
549
550 ata_WaitNano(400);
551 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
552
553 /*
554 * let's check if the drive is already good
555 */
556 status = ata_in(ata_AltStatus, unit->au_Bus->ab_Alt); //ata_in(ata_Status, unit->au_Bus->ab_Port);
557 if (0 == (status & (ATAF_DATAREQ | ATAF_BUSY)))
558 break;
559
560 /*
561 * so we're stuck in a loop?
562 */
563 DIRQ(bug("[ATA%02ld] Waiting (Current status: %02lx)...\n", unit->au_UnitNum, status));
564
565 /*
566 * if IRQ wait is requested then allow either timeout or irq;
567 * then clear irq flag so we don't keep receiving more of these (especially when system suffers collisions)
568 */
569 if (irq)
570 {
571 /*
572 * wait for either IRQ or TIMEOUT
573 */
574 step = Wait(sigs);
575
576 /*
577 * now if we did reach timeout, then there's no point in going ahead.
578 */
579 if (SIGBREAKF_CTRL_C & step)
580 {
581 bug("[ATA%02ld] Timeout while waiting for device to complete operation\n", unit->au_UnitNum);
582
583 res = FALSE;
584 }
585
586 /*
587 * if we get as far as this, there's no more signals to expect
588 * but we still want the status
589 */
590 status = ata_in(ata_Status, unit->au_Bus->ab_Port);
591 break;
592 }
593 else
594 {
595 ++step;
596
597 /*
598 * every 16n rounds do some extra stuff
599 */
600 if ((step & 16) == 0)
601 {
602 /*
603 * huhm. so it's been 16n rounds already. any timeout yet?
604 */
605 if (SetSignal(0, SIGBREAKF_CTRL_C) & SIGBREAKF_CTRL_C)
606 {
607 DIRQ(bug("[ATA%02ld] Device still busy after timeout. Aborting\n", unit->au_UnitNum));
608 res = FALSE;
609 break;
610 }
611
612 /*
613 * no timeout just yet, but it's not a good idea to keep spinning like that.
614 * let's give the system some time.
615 */
616 ata_WaitNano(400);
617 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
618 // TODO: Put some delay here!
619 }
620 }
621 } while(status & ATAF_BUSY);
622
623 /*
624 * be nice to frustrated developer
625 */
626 DIRQ(bug("[ATA%02ld] WaitBusy status: %lx / %ld\n", unit->au_UnitNum, status, res));
627
628 /*
629 * clear up all our expectations
630 */
631 Disable();
632 unit->au_Bus->ab_Timeout = -1;
633 Enable();
634
635 /*
636 * clear any interrupt (may be neccessary if we were polling, for example)
637 */
638 ata_in(ata_Status, unit->au_Bus->ab_Port);
639
640 /*
641 * release old junk
642 */
643 SetSignal(0, sigs);
644
645 /*
646 * and say it went fine (i mean it)
647 */
648 if (stout)
649 *stout = status;
650 return res;
651 }
652
653 /*
654 * Procedure for sending ATA command blocks
655 * it appears LARGE but there's a lot of COMMENTS here :)
656 * handles *all* ata commands (no data, pio and dma)
657 * naturally could be split at some point in the future
658 * depends if anyone believes that the change for 50 lines
659 * would make slow ATA transfers any faster
660 */
661 static ULONG ata_exec_cmd(struct ata_Unit* au, ata_CommandBlock *block)
662 {
663 ULONG port = au->au_Bus->ab_Port;
664 ULONG err = 0;
665 APTR mem = block->buffer;
666 UBYTE status;
667
668 if (FALSE == ata_SelectUnit(au))
669 return IOERR_UNITBUSY;
670
671 switch (block->type)
672 {
673 case CT_LBA28:
674 if (block->sectors > 256)
675 {
676 bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 256 sectors. Aborting.\n", au->au_UnitNum, block->sectors);
677 return IOERR_BADLENGTH;
678 }
679
680 /* note:
681 * we want the above to fall in here!
682 * we really do (checking for secmul)
683 */
684
685 case CT_LBA48:
686 if (block->sectors > 65536)
687 {
688 bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 65536 sectors. Aborting.\n", au->au_UnitNum, block->sectors);
689 return IOERR_BADLENGTH;
690 }
691 if (block->secmul == 0)
692 {
693 bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid transfer multiplier. Should be at least set to 1 (correcting)\n", au->au_UnitNum);
694 block->secmul = 1;
695 }
696 break;
697
698 case CT_NoBlock:
699 break;
700
701 default:
702 bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid command type %lx. Aborting.\n", au->au_UnitNum, block->type);
703 return IOERR_NOCMD;
704 }
705
706 block->actual = 0;
707 D(bug("[ATA%02ld] ata_exec_cmd: Executing command %02lx\n", au->au_UnitNum, block->command));
708
709 if (block->feature != 0)
710 ata_out(block->feature, ata_Feature, port);
711
712 /*
713 * - set LBA and sector count
714 */
715 switch (block->type)
716 {
717 case CT_LBA28:
718 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 28bit LBA addressing (OLD)\n", au->au_UnitNum));
719 ata_out(((block->blk >> 24) & 0x0f) | 0x40 | au->au_DevMask, ata_DevHead, port);
720 ata_out(block->blk >> 16, ata_LBAHigh, port);
721 ata_out(block->blk >> 8, ata_LBAMid, port);
722 ata_out(block->blk, ata_LBALow, port);
723 ata_out(block->sectors, ata_Count, port);
724 break;
725
726 case CT_LBA48:
727 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 48bit LBA addressing (NEW)\n", au->au_UnitNum));
728 ata_out(block->blk >> 40, ata_LBAHigh, port);
729 ata_out(block->blk >> 32, ata_LBAMid, port);
730 ata_out(block->blk >> 24, ata_LBALow, port);
731
732 ata_out(block->blk >> 16, ata_LBAHigh, port);
733 ata_out(block->blk >> 8, ata_LBAMid, port);
734 ata_out(block->blk, ata_LBALow, port);
735
736 ata_out(block->sectors >> 8, ata_Count, port);
737 ata_out(block->sectors, ata_Count, port);
738 break;
739
740 case CT_NoBlock:
741 DATA(bug("[ATA%02ld] ata_exec_cmd: Command does not address any block\n", au->au_UnitNum));
742 break;
743 }
744
745 switch (block->method)
746 {
747 case CM_PIOWrite:
748 ata_IRQSetHandler(au, &ata_IRQPIOWrite, mem, block->secmul << au->au_SectorShift, block->length);
749 break;
750
751 case CM_PIORead:
752 ata_IRQSetHandler(au, &ata_IRQPIORead, mem, block->secmul << au->au_SectorShift, block->length);
753 break;
754
755 case CM_DMARead:
756 if (FALSE == dma_SetupPRDSize(au, mem, block->length, TRUE))
757 return IOERR_ABORTED;
758 ata_IRQSetHandler(au, &ata_IRQDMAReadWrite, NULL, 0, 0);
759 dma_StartDMA(au);
760 break;
761
762 case CM_DMAWrite:
763 if (FALSE == dma_SetupPRDSize(au, mem, block->length, FALSE))
764 return IOERR_ABORTED;
765 ata_IRQSetHandler(au, &ata_IRQDMAReadWrite, NULL, 0, 0);
766 dma_StartDMA(au);
767 break;
768
769 case CM_NoData:
770 ata_IRQSetHandler(au, &ata_IRQNoData, NULL, 0, 0);
771 break;
772
773 default:
774 return IOERR_NOCMD;
775 break;
776 };
777
778 /*
779 * send command now
780 * let drive propagate its signals
781 */
782 DATA(bug("[ATA%02ld] ata_exec_cmd: Sending command\n", au->au_UnitNum));
783 ata_out(block->command, ata_Command, port);
784 ata_WaitNano(400);
785 //ata_WaitTO(au->au_Bus->ab_Timer, 0, 1, 0);
786
787 /*
788 * In case of PIO write the drive won't issue an IRQ before first
789 * data transfer, so we should poll the status and send the first
790 * block upon request.
791 */
792 if (block->method == CM_PIOWrite) {
793 if (FALSE == ata_WaitBusyTO(au, 30, FALSE, &status)) {
794 D(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - no response from device\n", au->au_UnitNum));
795 return IOERR_UNITBUSY;
796 }
797 if (status & ATAF_DATAREQ) {
798 DATA(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - DRQ.\n", au->au_UnitNum));
799 ata_PIOWriteBlk(au);
800 }
801 else
802 {
803 D(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - bad status: %02X\n", status));
804 return HFERR_BadStatus;
805 }
806 }
807
808 /*
809 * wait for drive to complete what it has to do
810 */
811 if (FALSE == ata_WaitBusyTO(au, 30, TRUE, NULL))
812 {
813 bug("[ATA%02ld] ata_exec_cmd: Device is late - no response\n", au->au_UnitNum);
814 err = IOERR_UNITBUSY;
815 }
816 else
817 err = au->au_cmd_error;
818
819 DATA(bug("[ATA%02ld] ata_exec_cmd: Command done\n", au->au_UnitNum));
820 /*
821 * clean up DMA
822 * don't use 'mem' pointer here as it's already invalid.
823 */
824 if (block->method == CM_DMARead)
825 {
826 dma_StopDMA(au);
827 dma_Cleanup(block->buffer, block->length, TRUE);
828 }
829 else if (block->method == CM_DMAWrite)
830 {
831 dma_StopDMA(au);
832 dma_Cleanup(block->buffer, block->length, FALSE);
833 }
834
835 D(bug("[ATA%02ld] ata_exec_cmd: return code %ld\n", au->au_UnitNum, err));
836 return err;
837 }
838
839 /*
840 * atapi packet iface
841 */
842 int atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data, LONG datalen, BOOL *dma, BOOL write)
843 {
844 *dma = *dma && (unit->au_XferModes & AF_XFER_DMA) ? TRUE : FALSE;
845 LONG err = 0;
846
847 UBYTE cmd[12] = {
848 0
849 };
850 register int t=5,l=0;
851 ULONG port = unit->au_Bus->ab_Port;
852
853 if (((UBYTE*)packet)[0] > 0x1f)
854 t+= 4;
855 if (((UBYTE*)packet)[0] > 0x5f)
856 t+= 2;
857
858 switch (((UBYTE*)packet)[0])
859 {
860 case 0x28: // read10
861 case 0xa8: // read12
862 case 0xbe: // readcd
863 case 0xb9: // readcdmsf
864 case 0x2f: // verify
865 case 0x2a: // write
866 case 0xaa: // write12
867 case 0x2e: // writeverify
868 case 0xad: // readdvdstructure
869 case 0xa4: // reportkey
870 case 0xa3: // sendkey
871 break;
872 default:
873 *dma = FALSE;
874 }
875
876 while (l<=t)
877 {
878 cmd[l] = ((UBYTE*)packet)[l];
879 ++l;
880 }
881
882 DATAPI({
883 bug("[ATA%02lx] Sending %s ATA packet: ", unit->au_UnitNum, (*dma) ? "DMA" : "PIO");
884 l=0;
885 while (l<=t)
886 {
887 bug("%02lx ", ((UBYTE*)cmd)[l]);
888 ++l;
889 }
890 bug("\n");
891
892 if (datalen & 1)
893 bug("[ATAPI] ERROR: DATA LENGTH NOT EVEN! Rounding Up! (%ld bytes requested)\n", datalen);
894 });
895
896 datalen = (datalen+1)&~1;
897
898 if (FALSE == ata_SelectUnit(unit))
899 {
900 DATAPI(bug("[ATAPI] WaitBusy failed at first check\n"));
901 return IOERR_UNITBUSY;
902 }
903
904 /*
905 * tell device whether we want to read or write and if we want a dma transfer
906 */
907 ata_out(((*dma) ? 1 : 0) |
908 (((unit->au_Drive->id_DMADir & 0x8000) && !write) ? 4 : 0),
909 atapi_Features, port);
910 ata_out((datalen & 0xff), atapi_ByteCntL, port);
911 ata_out((datalen >> 8) & 0xff, atapi_ByteCntH, port);
912
913 /*
914 * once we're done with that, we can go ahead and inform device that we're about to send atapi packet
915 * after command is dispatched, we are obliged to give 400ns for the unit to parse command and set status
916 */
917 DATAPI(bug("[ATAPI] Issuing ATA_PACKET command.\n"));
918 ata_out(ATA_PACKET, atapi_Command, port);
919 ata_WaitNano(400);
920 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
921
922 ata_WaitBusyTO(unit, 30, (unit->au_Drive->id_General & 0x60) == 0x20, NULL);
923 if (0 == (ata_ReadStatus(unit->au_Bus) & ATAF_DATAREQ))
924 return HFERR_BadStatus;
925
926 /*
927 * setup appropriate hooks
928 */
929 if (datalen == 0)
930 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
931 else if (*dma)
932 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
933 else if (write)
934 ata_IRQSetHandler(unit, &ata_IRQPIOWriteAtapi, data, 0, datalen);
935 else
936 ata_IRQSetHandler(unit, &ata_IRQPIOReadAtapi, data, 0, datalen);
937
938 if (*dma)
939 {
940 DATAPI(bug("[ATAPI] Starting DMA\n"));
941 dma_StartDMA(unit);
942 }
943
944 DATAPI(bug("[ATAPI] Sending packet\n"));
945 unit->au_outs(cmd, unit->au_Bus->ab_Port, 12);
946 ata_WaitNano(400);
947 DATAPI(bug("[ATAPI] Status after packet: %lx\n",
948 ata_ReadAltStatus(unit->au_Bus)));
949
950 /*
951 * Wait for command to complete. Note that two interrupts will occur
952 * before we wake up if this is a PIO data transfer
953 */
954 if (ata_WaitTO(unit->au_Bus->ab_Timer, 30, 0,
955 1 << unit->au_Bus->ab_SleepySignal) == 0)
956 {
957 DATAPI(bug("[DSCSI] Command timed out.\n"));
958 err = IOERR_UNITBUSY;
959 }
960 else
961 err = atapi_EndCmd(unit);
962
963 if (*dma)
964 {
965 dma_StopDMA(unit);
966 dma_Cleanup(data, datalen, !write);
967 }
968
969 DATAPI(bug("[ATAPI] IO error code %ld\n", err));
970 return err;
971 }
972
973 ULONG atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd)
974 {
975 APTR buffer = cmd->scsi_Data;
976 ULONG length = cmd->scsi_Length;
977 BOOL read = FALSE;
978 UBYTE err = 0;
979 BOOL dma = FALSE;
980
981 cmd->scsi_Actual = 0;
982
983 DATAPI(bug("[DSCSI] Sending packet!\n"));
984
985 /*
986 * setup DMA & push command
987 * it does not really mean we will use dma here btw
988 */
989 if ((unit->au_XferModes & AF_XFER_DMA) && (length !=0) && (buffer != 0))
990 {
991 dma = TRUE;
992 if ((cmd->scsi_Flags & SCSIF_READ) != 0)
993 {
994 read = TRUE;
995 if (FALSE == dma_SetupPRDSize(unit, buffer, length, TRUE))
996 dma = FALSE;
997 }
998 else
999 {
1000 if (FALSE == dma_SetupPRDSize(unit, buffer, length, FALSE))
1001 dma = FALSE;
1002 }
1003 }
1004
1005 err = atapi_SendPacket(unit, cmd->scsi_Command, cmd->scsi_Data, cmd->scsi_Length, &dma, (cmd->scsi_Flags & SCSIF_READ) == 0);
1006
1007 DUMP({ if (cmd->scsi_Data != 0) dump(cmd->scsi_Data, cmd->scsi_Length); });
1008
1009 /*
1010 * on check condition - grab sense data
1011 */
1012 DATAPI(bug("[ATA%02lx] atapi_DirectSCSI: SCSI Flags: %02lx / Error: %ld\n", unit->au_UnitNum, cmd->scsi_Flags, err));
1013 if ((err != 0) && (cmd->scsi_Flags & SCSIF_AUTOSENSE))
1014 {
1015 DATAPI(bug("[DSCSI] atapi_DirectSCSI: Packet Failed. Calling atapi_RequestSense\n"));
1016 atapi_RequestSense(unit, cmd->scsi_SenseData, cmd->scsi_SenseLength);
1017 DUMP(dump(cmd->scsi_SenseData, cmd->scsi_SenseLength));
1018 }
1019
1020 return err;
1021 }
1022
1023 /*
1024 * chops the large transfers into set of smaller transfers
1025 * specifically useful when requested transfer size is >256 sectors for 28bit commands
1026 */
1027 static ULONG ata_exec_blk(struct ata_Unit *unit, ata_CommandBlock *blk)
1028 {
1029 ULONG err=0;
1030 ULONG part;
1031 ULONG max=256;
1032 ULONG count=blk->sectors;
1033
1034 if (blk->type == CT_LBA48)
1035 max <<= 8;
1036
1037 DATA(bug("[ATA%02ld] ata_exec_blk: Accessing %ld sectors starting from %x%08x\n", unit->au_UnitNum, count, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
1038 while ((count > 0) && (err == 0))
1039 {
1040 part = (count > max) ? max : count;
1041 blk->sectors = part;
1042 blk->length = part << unit->au_SectorShift;
1043
1044 DATA(bug("[ATA%02ld] Transfer of %ld sectors from %x%08x\n", unit->au_UnitNum, part, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
1045 err = ata_exec_cmd(unit, blk);
1046 DATA(bug("[ATA%02ld] ata_exec_blk: ata_exec_cmd returned %lx\n", unit->au_UnitNum, err));
1047
1048 blk->blk += part;
1049 blk->buffer = &((char*)blk->buffer)[part << unit->au_SectorShift];
1050 count -= part;
1051 }
1052 return err;
1053 }
1054
1055 /*
1056 * Initial device configuration that suits *all* cases
1057 */
1058 BOOL ata_init_unit(struct ata_Bus *bus, UBYTE u)
1059 {
1060 struct ata_Unit *unit=NULL;
1061
1062 DINIT(bug("[ATA ] ata_init_unit(%ld)\n", u));
1063
1064 unit = bus->ab_Units[u];
1065 if (NULL == unit)
1066 return FALSE;
1067
1068 unit->au_Bus = bus;
1069 unit->au_Drive = AllocPooled(bus->ab_Base->ata_MemPool, sizeof(struct DriveIdent));
1070 unit->au_UnitNum = bus->ab_BusNum << 1 | u; // b << 8 | u
1071 unit->au_DevMask = 0xa0 | (u << 4);
1072 if (bus->ab_Base->ata_32bit)
1073 {
1074 unit->au_ins = ata_insl;
1075 unit->au_outs = ata_outsl;
1076 }
1077 else
1078 {
1079 unit->au_ins = ata_insw;
1080 unit->au_outs = ata_outsw;
1081 }
1082 unit->au_SectorShift= 9; /* this really has to be set here. */
1083
1084 NEWLIST(&unit->au_SoftList);
1085
1086 /*
1087 * since the stack is always handled by caller
1088 * it's safe to stub all calls with one function
1089 */
1090 unit->au_Read32 = ata_STUB_IO32;
1091 unit->au_Read64 = ata_STUB_IO64;
1092 unit->au_Write32 = ata_STUB_IO32;
1093 unit->au_Write64 = ata_STUB_IO64;
1094 unit->au_Eject = ata_STUB;
1095 unit->au_DirectSCSI = ata_STUB_SCSI;
1096 unit->au_Identify = ata_STUB;
1097 return TRUE;
1098 }
1099
1100 BOOL ata_setup_unit(struct ata_Bus *bus, UBYTE u)
1101 {
1102 struct ata_Unit *unit=NULL;
1103
1104 /*
1105 * this stuff always goes along the same way
1106 * WARNING: NO INTERRUPTS AT THIS POINT!
1107 */
1108 DINIT(bug("[ATA ] ata_setup_unit(%ld,%ld)\n", bus->ab_BusNum, u));
1109
1110 unit = bus->ab_Units[u];
1111 if (NULL == unit)
1112 return FALSE;
1113
1114 ata_SelectUnit(unit);
1115
1116 if (unit->au_DMAPort != 0
1117 && (ata_in(dma_Status, unit->au_DMAPort) & 0x80) != 0)
1118 bug("[ATA%02ld] ata_setup_unit: WARNING: Controller only supports "
1119 "DMA on one bus at a time. DMAStatus=%lx\n", unit->au_UnitNum,
1120 ata_in(dma_Status, unit->au_DMAPort));
1121
1122 if (FALSE == ata_WaitBusyTO(unit, 1, FALSE, NULL))
1123 {
1124 DINIT(bug("[ATA%02ld] ata_setup_unit: ERROR: Drive not ready for use. Keeping functions stubbed\n", unit->au_UnitNum));
1125 FreePooled(bus->ab_Base->ata_MemPool, unit->au_Drive, sizeof(struct DriveIdent));
1126 unit->au_Drive = 0;
1127 return FALSE;
1128 }
1129
1130 switch (bus->ab_Dev[u])
1131 {
1132 /*
1133 * safe fallback settings
1134 */
1135 case DEV_SATAPI:
1136 case DEV_ATAPI:
1137 unit->au_Identify = atapi_Identify;
1138 break;
1139
1140 case DEV_SATA:
1141 case DEV_ATA:
1142 unit->au_Identify = ata_Identify;
1143 break;
1144
1145 default:
1146 DINIT(bug("[ATA%02ld] ata_setup_unit: Unsupported device %lx. All functions will remain stubbed.\n", unit->au_UnitNum, bus->ab_Dev[u]));
1147 FreePooled(bus->ab_Base->ata_MemPool, unit->au_Drive, sizeof(struct DriveIdent));
1148 unit->au_Drive = 0;
1149 return FALSE;
1150 }
1151
1152 D(bug("[ATA ] ata_setup_unit: Enabling IRQs\n"));
1153 ata_out(0x0, ata_AltControl, bus->ab_Alt);
1154
1155 /*
1156 * now make unit self diagnose
1157 */
1158 if (unit->au_Identify(unit) != 0)
1159 {
1160 FreePooled(bus->ab_Base->ata_MemPool, unit->au_Drive, sizeof(struct DriveIdent));
1161 unit->au_Drive = NULL;
1162 return FALSE;
1163 }
1164
1165 return TRUE;
1166 }
1167
1168 /*
1169 * ata[pi] identify
1170 */
1171 static void common_SetXferMode(struct ata_Unit* unit, ata_XferMode mode)
1172 {
1173 UBYTE type=0;
1174 BOOL dma=FALSE;
1175 ata_CommandBlock acb =
1176 {
1177 ATA_SET_FEATURES,
1178 0x03,
1179 0x01,
1180 0x00,
1181 0x00,
1182 0x00,
1183 0x00,
1184 0x00,
1185 0x00,
1186 CM_NoData,
1187 CT_LBA28
1188 };
1189 DINIT(bug("[ATA%02ld] common_SetXferMode: Trying to set mode %d\n", unit->au_UnitNum, mode));
1190
1191 if ((unit->au_DMAPort == 0) && (mode >= AB_XFER_MDMA0))
1192 {
1193 DINIT(bug("[ATA%02ld] common_SetXferMode: This controller does not own DMA port! Will set best PIO\n", unit->au_UnitNum));
1194 common_SetBestXferMode(unit);
1195 return;
1196 }
1197
1198 /*
1199 * first, ONLY for ATA devices, set new commands
1200 */
1201 if (0 == (unit->au_XferModes & AF_XFER_PACKET))
1202 {
1203 if ((mode >= AB_XFER_PIO0) && (mode <= AB_XFER_PIO4))
1204 {
1205 if ((!unit->au_Bus->ab_Base->ata_NoMulti) && (unit->au_XferModes & AF_XFER_RWMULTI))
1206 {
1207 ata_IRQSetHandler(unit, ata_IRQNoData, NULL, 0, 0);
1208 ata_out(unit->au_Drive->id_RWMultipleSize & 0xFF, ata_Count, unit->au_Bus->ab_Port);
1209 ata_out(ATA_SET_MULTIPLE, ata_Command, unit->au_Bus->ab_Port);
1210 ata_WaitBusyTO(unit, -1, TRUE, NULL);
1211
1212 unit->au_Read32 = ata_ReadMultiple32;
1213 unit->au_Write32 = ata_WriteMultiple32;
1214 if (unit->au_XferModes & AF_XFER_48BIT)
1215 {
1216 unit->au_Read64 = ata_ReadMultiple64;
1217 unit->au_Write64 = ata_WriteMultiple64;
1218 }
1219 }
1220 else
1221 {
1222 unit->au_Read32 = ata_ReadSector32;
1223 unit->au_Write32 = ata_WriteSector32;
1224 if (unit->au_XferModes & AF_XFER_48BIT)
1225 {
1226 unit->au_Read64 = ata_ReadSector64;
1227 unit->au_Write64 = ata_WriteSector64;
1228 }
1229 }
1230 }
1231 else if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_MDMA2))
1232 {
1233 unit->au_Read32 = ata_ReadDMA32;
1234 unit->au_Write32 = ata_WriteDMA32;
1235 if (unit->au_XferModes & AF_XFER_48BIT)
1236 {
1237 unit->au_Read64 = ata_ReadDMA64;
1238 unit->au_Write64 = ata_WriteDMA64;
1239 }
1240 }
1241 else if ((mode >= AB_XFER_UDMA0) && (mode <= AB_XFER_UDMA6))
1242 {
1243 unit->au_Read32 = ata_ReadDMA32;
1244 unit->au_Write32 = ata_WriteDMA32;
1245 if (unit->au_XferModes & AF_XFER_48BIT)
1246 {
1247 unit->au_Read64 = ata_ReadDMA64;
1248 unit->au_Write64 = ata_WriteDMA64;
1249 }
1250 }
1251 else
1252 {
1253 unit->au_Read32 = ata_ReadSector32;
1254 unit->au_Write32 = ata_WriteSector32;
1255 if (unit->au_XferModes & AF_XFER_48BIT)
1256 {
1257 unit->au_Read64 = ata_ReadSector64;
1258 unit->au_Write64 = ata_WriteSector64;
1259 }
1260 }
1261 }
1262
1263 if ((mode >= AB_XFER_PIO0) && (mode <= AB_XFER_PIO4))
1264 {
1265 type = 8 + (mode - AB_XFER_PIO0);
1266 }
1267 else if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_MDMA2))
1268 {
1269 type = 32 + (mode - AB_XFER_MDMA0);
1270 dma=TRUE;
1271 }
1272 else if ((mode >= AB_XFER_UDMA0) && (mode <= AB_XFER_UDMA6))
1273 {
1274 type = 64 + (mode - AB_XFER_UDMA0);
1275 dma=TRUE;
1276 }
1277 else
1278 {
1279 type = 0;
1280 }
1281
1282 #if 0 // We can't set drive modes unless we also set the controller's timing registers
1283 acb.sectors = type;
1284 if (0 != ata_exec_cmd(unit, &acb))
1285 {
1286 DINIT(bug("[ATA%02ld] common_SetXferMode: ERROR: Failed to apply new xfer mode.\n", unit->au_UnitNum));
1287 }
1288 #endif
1289
1290 if (unit->au_DMAPort)
1291 {
1292 type = ata_in(dma_Status, unit->au_DMAPort);
1293 type &= 0x60;
1294 if (dma)
1295 {
1296 type |= 1 << (5 + (unit->au_UnitNum & 1));
1297 }
1298 else
1299 {
1300 type &= ~(1 << (5 + (unit->au_UnitNum & 1)));
1301 }
1302
1303 DINIT(bug("[DSCSI] common_SetXferMode: Trying to apply new DMA (%lx) status: %02lx (unit %ld)\n", unit->au_DMAPort, type, unit->au_UnitNum & 1));
1304
1305 ata_SelectUnit(unit);
1306 ata_out(type, dma_Status, unit->au_DMAPort);
1307 if (type == (ata_in(dma_Status, unit->au_DMAPort) & 0x60))
1308 {
1309 DINIT(bug("[DSCSI] common_SetXferMode: New DMA Status: %02lx\n", type));
1310 }
1311 else
1312 {
1313 DINIT(bug("[DSCSI] common_SetXferMode: Failed to modify DMA state for this device\n"));
1314 dma = FALSE;
1315 }
1316 }
1317
1318 if (dma)
1319 unit->au_XferModes |= AF_XFER_DMA;
1320 else
1321 unit->au_XferModes &= ~AF_XFER_DMA;
1322 }
1323
1324 static void common_SetBestXferMode(struct ata_Unit* unit)
1325 {
1326 int iter;
1327 int max = AB_XFER_UDMA6;
1328
1329 if (unit->au_DMAPort == 0
1330 || !(unit->au_Drive->id_MWDMASupport & 0x0700)
1331 && !(unit->au_Drive->id_UDMASupport & 0x7f00))
1332 {
1333 /*
1334 * make sure you reduce scan search to pio here!
1335 * otherwise this and above function will fall into infinite loop
1336 */
1337 DINIT(bug("[ATA%02ld] common_SetBestXferMode: This controller does not own DMA port\n", unit->au_UnitNum));
1338 max = AB_XFER_PIO4;
1339 }
1340 else if (!(unit->au_Flags & AF_80Wire))
1341 {
1342 DINIT(bug("[ATA%02ld] common_SetBestXferMode: "
1343 "An 80-wire cable has not been detected for this drive. "
1344 "Disabling modes above UDMA2.\n", unit->au_UnitNum));
1345 max = AB_XFER_UDMA2;
1346 }
1347
1348 for (iter=max; iter>=AB_XFER_PIO0; --iter)
1349 {
1350 if (unit->au_XferModes & (1<<iter))
1351 {
1352 common_SetXferMode(unit, iter);
1353 return;
1354 }
1355 }
1356 bug("[ATA%02ld] common_SetBestXferMode: ERROR: device never reported any valid xfer modes. will continue at default\n", unit->au_UnitNum);
1357 common_SetXferMode(unit, AB_XFER_PIO0);
1358 }
1359
1360 void common_DetectXferModes(struct ata_Unit* unit)
1361 {
1362 int iter;
1363
1364 DINIT(bug("[ATA%02ld] common_DetectXferModes: Supports\n", unit->au_UnitNum));
1365
1366 if (unit->au_Drive->id_Commands4 & (1 << 4))
1367 {
1368 DINIT(bug("[ATA%02ld] common_DetectXferModes: - Packet interface\n", unit->au_UnitNum));
1369 unit->au_XferModes |= AF_XFER_PACKET;
1370 unit->au_DirectSCSI = atapi_DirectSCSI;
1371 }
1372 else if (unit->au_Drive->id_Commands5 & (1 << 10))
1373 {
1374 /* ATAPI devices do not use this bit. */
1375 DINIT(bug("[ATA%02ld] common_DetectXferModes: - 48bit I/O\n", unit->au_UnitNum));
1376 unit->au_XferModes |= AF_XFER_48BIT;
1377 }
1378
1379 if ((unit->au_XferModes & AF_XFER_PACKET) || (unit->au_Drive->id_Capabilities & (1<< 9)))
1380 {
1381 DINIT(bug("[ATA%02ld] common_DetectXferModes: - LBA Addressing\n", unit->au_UnitNum));
1382 unit->au_XferModes |= AF_XFER_LBA;
1383 }
1384 else
1385 {
1386 DINIT(bug("[ATA%02ld] common_DetectXferModes: - DEVICE DOES NOT SUPPORT LBA ADDRESSING >> THIS IS A POTENTIAL PROBLEM <<\n", unit->au_UnitNum));
1387 }
1388
1389 if (unit->au_Drive->id_RWMultipleSize & 0xff)
1390 {
1391 DINIT(bug("[ATA%02ld] common_DetectXferModes: - R/W Multiple (%ld sectors per xfer)\n", unit->au_UnitNum, unit->au_Drive->id_RWMultipleSize & 0xff));
1392 unit->au_XferModes |= AF_XFER_RWMULTI;
1393 }
1394
1395 DINIT(bug("[ATA%02ld] common_DetectXferModes: - PIO0 PIO1 PIO2 ",
1396 unit->au_UnitNum));
1397 unit->au_XferModes |= AF_XFER_PIO(0) | AF_XFER_PIO(1) | AF_XFER_PIO(2);
1398 if (unit->au_Drive->id_ConfigAvailable & (1 << 1))
1399 {
1400 for (iter = 0; iter < 2; iter++)
1401 {
1402 if (unit->au_Drive->id_PIOSupport & (1 << iter))
1403 {
1404 DINIT(bug("PIO%ld ", 3 + iter));
1405 unit->au_XferModes |= AF_XFER_PIO(3 + iter);
1406 }
1407 }
1408 DINIT(bug("\n"));
1409 }
1410
1411 if ((unit->au_Drive->id_ConfigAvailable & (1 << 1)) &&
1412 (unit->au_Drive->id_Capabilities & (1<<8)))
1413 {
1414 DINIT(bug("[ATA%02ld] common_DetectXferModes: DMA:\n", unit->au_UnitNum));
1415 if (unit->au_Drive->id_MWDMASupport & 0xff)
1416 {
1417 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1418 for (iter = 0; iter < 3; iter++)
1419 {
1420 if (unit->au_Drive->id_MWDMASupport & (1 << iter))
1421 {
1422 unit->au_XferModes |= AF_XFER_MDMA(iter);
1423 if (unit->au_Drive->id_MWDMASupport & (256 << iter))
1424 {
1425 DINIT(bug("[MDMA%ld] ", iter));
1426 }
1427 else
1428 {
1429 DINIT(bug("MDMA%ld ", iter));
1430 }
1431 }
1432 }
1433 DINIT(bug("\n"));
1434 }
1435
1436 if (unit->au_Drive->id_UDMASupport & 0xff)
1437 {
1438 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1439 for (iter = 0; iter < 7; iter++)
1440 {
1441 if (unit->au_Drive->id_UDMASupport & (1 << iter))
1442 {
1443 unit->au_XferModes |= AF_XFER_UDMA(iter);
1444 if (unit->au_Drive->id_UDMASupport & (256 << iter))
1445 {
1446 DINIT(bug("[UDMA%ld] ", iter));
1447 }
1448 else
1449 {
1450 DINIT(bug("UDMA%ld ", iter));
1451 }
1452 }
1453 }
1454 DINIT(bug("\n"));
1455 }
1456 }
1457 }
1458
1459 #define SWAP_LE_WORD(x) (x) = AROS_LE2WORD((x))
1460 #define SWAP_LE_LONG(x) (x) = AROS_LE2LONG((x))
1461 #define SWAP_LE_QUAD(x) (x) = AROS_LE2LONG((x)>>32) | AROS_LE2LONG((x) & 0xffffffff) << 32
1462
1463 BYTE atapi_Identify(struct ata_Unit* unit)
1464 {
1465 ata_CommandBlock acb =
1466 {
1467 ATA_IDENTIFY_ATAPI,
1468 0,
1469 1,
1470 0,
1471 0,
1472 0,
1473 unit->au_Drive,
1474 sizeof(struct DriveIdent),
1475 0,
1476 CM_PIORead,
1477 CT_NoBlock
1478 };
1479
1480 ata_SelectUnit(unit);
1481
1482 if (ata_exec_cmd(unit, &acb))
1483 {
1484 return IOERR_OPENFAIL;
1485 }
1486
1487 #if (AROS_BIG_ENDIAN != 0)
1488 SWAP_LE_WORD(unit->au_Drive->id_General);
1489 SWAP_LE_WORD(unit->au_Drive->id_OldCylinders);
1490 SWAP_LE_WORD(unit->au_Drive->id_SpecificConfig);
1491 SWAP_LE_WORD(unit->au_Drive->id_OldHeads);
1492 SWAP_LE_WORD(unit->au_Drive->id_OldSectors);
1493 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleSize);
1494 SWAP_LE_WORD(unit->au_Drive->id_Capabilities);
1495 SWAP_LE_WORD(unit->au_Drive->id_OldCaps);
1496 SWAP_LE_WORD(unit->au_Drive->id_OldPIO);
1497 SWAP_LE_WORD(unit->au_Drive->id_ConfigAvailable);
1498 SWAP_LE_WORD(unit->au_Drive->id_OldLCylinders);
1499 SWAP_LE_WORD(unit->au_Drive->id_OldLHeads);
1500 SWAP_LE_WORD(unit->au_Drive->id_OldLSectors);
1501 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleTrans);
1502 SWAP_LE_WORD(unit->au_Drive->id_MWDMASupport);
1503 SWAP_LE_WORD(unit->au_Drive->id_PIOSupport);
1504 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_MinCycleTime);
1505 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_DefCycleTime);
1506 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTime);
1507 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTImeIORDY);
1508 SWAP_LE_WORD(unit->au_Drive->id_QueueDepth);
1509 SWAP_LE_WORD(unit->au_Drive->id_ATAVersion);
1510 SWAP_LE_WORD(unit->au_Drive->id_ATARevision);
1511 SWAP_LE_WORD(unit->au_Drive->id_Commands1);
1512 SWAP_LE_WORD(unit->au_Drive->id_Commands2);
1513 SWAP_LE_WORD(unit->au_Drive->id_Commands3);
1514 SWAP_LE_WORD(unit->au_Drive->id_Commands4);
1515 SWAP_LE_WORD(unit->au_Drive->id_Commands5);
1516 SWAP_LE_WORD(unit->au_Drive->id_Commands6);
1517 SWAP_LE_WORD(unit->au_Drive->id_UDMASupport);
1518 SWAP_LE_WORD(unit->au_Drive->id_SecurityEraseTime);
1519 SWAP_LE_WORD(unit->au_Drive->id_ESecurityEraseTime);
1520 SWAP_LE_WORD(unit->au_Drive->id_CurrentAdvPowerMode);
1521 SWAP_LE_WORD(unit->au_Drive->id_MasterPwdRevision);
1522 SWAP_LE_WORD(unit->au_Drive->id_HWResetResult);
1523 SWAP_LE_WORD(unit->au_Drive->id_AcousticManagement);
1524 SWAP_LE_WORD(unit->au_Drive->id_StreamMinimunReqSize);
1525 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimeDMA);
1526 SWAP_LE_WORD(unit->au_Drive->id_StreamingLatency);
1527 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimePIO);
1528 SWAP_LE_WORD(unit->au_Drive->id_PhysSectorSize);
1529 SWAP_LE_WORD(unit->au_Drive->id_RemMediaStatusNotificationFeatures);
1530 SWAP_LE_WORD(unit->au_Drive->id_SecurityStatus);
1531
1532 SWAP_LE_LONG(unit->au_Drive->id_WordsPerLogicalSector);
1533 SWAP_LE_LONG(unit->au_Drive->id_LBASectors);
1534 SWAP_LE_LONG(unit->au_Drive->id_StreamingGranularity);
1535
1536 SWAP_LE_QUAD(unit->au_Drive->id_LBA48Sectors);
1537 #endif
1538
1539 /*
1540 * Some SATA controllers in legacy mode emulate a non-existent ATAPI
1541 * device so well that we have to wait until we get an empty identify
1542 * structure to find out that the drive isn't real
1543 */
1544 if ((unit->au_Drive->id_General & 0x8000) == 0)
1545 {
1546 bug("[ATA%02ld] atapi_Identify: Identify data is invalid."
1547 " Disabling drive.\n", unit->au_UnitNum);
1548 return IOERR_OPENFAIL;
1549 }
1550
1551 DUMP(dump(unit->au_Drive, sizeof(struct DriveIdent)));
1552
1553 unit->au_SectorShift = 11;
1554 unit->au_Read32 = atapi_Read;
1555 unit->au_Write32 = atapi_Write;
1556 unit->au_DirectSCSI = atapi_DirectSCSI;
1557 unit->au_Eject = atapi_Eject;
1558 unit->au_Flags |= AF_DiscChanged;
1559 unit->au_DevType = (unit->au_Drive->id_General >>8) & 0x1f;
1560 unit->au_XferModes = AF_XFER_PACKET;
1561
1562 ata_strcpy(unit->au_Drive->id_Model, unit->au_Model, 40);
1563 ata_strcpy(unit->au_Drive->id_SerialNumber, unit->au_SerialNumber, 20);
1564 ata_strcpy(unit->au_Drive->id_FirmwareRev, unit->au_FirmwareRev, 8);
1565
1566 bug("[ATA%02ld] atapi_Identify: Unit info: %s / %s / %s\n", unit->au_UnitNum, unit->au_Model, unit->au_SerialNumber, unit->au_FirmwareRev);
1567 common_DetectXferModes(unit);
1568 common_SetBestXferMode(unit);
1569
1570 if (unit->au_Drive->id_General & 0x80)
1571 {
1572 DINIT(bug("[ATA%02ld] Device is removable.\n", unit->au_UnitNum));
1573 unit->au_Flags |= AF_Removable;
1574 }
1575
1576 unit->au_Capacity = unit->au_Drive->id_LBASectors;
1577 unit->au_Capacity48 = unit->au_Drive->id_LBA48Sectors;
1578 bug("[ATA%02ld] atapi_Identify: Unit info: %07lx 28bit / %04lx:%08lx 48bit addressable blocks\n", unit->au_UnitNum, unit->au_Capacity, (ULONG)(unit->au_Capacity48 >> 32), (ULONG)(unit->au_Capacity48 & 0xfffffffful));
1579
1580 /*
1581 * ok, this is not very original, but quite compatible :P
1582 */
1583 switch (unit->au_DevType)
1584 {
1585 case DG_CDROM:
1586 case DG_WORM:
1587 case DG_OPTICAL_DISK:
1588 unit->au_SectorShift = 11;
1589 unit->au_Heads = 1;
1590 unit->au_Sectors = 75;
1591 unit->au_Cylinders = 4440;
1592 break;
1593
1594 case DG_DIRECT_ACCESS:
1595 unit->au_SectorShift = 9;
1596 if (!strcmp("LS-120", &unit->au_Model[0]))
1597 {
1598 unit->au_Heads = 2;
1599 unit->au_Sectors = 18;
1600 unit->au_Cylinders = 6848;
1601 }
1602 else if (!strcmp("ZIP 100 ", &unit->au_Model[8]))
1603 {
1604 unit->au_Heads = 1;
1605 unit->au_Sectors = 64;
1606 unit->au_Cylinders = 3072;
1607 }
1608 break;
1609 }
1610
1611 atapi_TestUnitOK(unit);
1612
1613 return 0;
1614 }
1615
1616 BYTE ata_Identify(struct ata_Unit* unit)
1617 {
1618 ata_CommandBlock acb =
1619 {
1620 ATA_IDENTIFY_DEVICE,
1621 0,
1622 1,
1623 0,
1624 0,
1625 0,
1626 unit->au_Drive,
1627 sizeof(struct DriveIdent),
1628 0,
1629 CM_PIORead,
1630 CT_NoBlock
1631 };
1632
1633 if (ata_exec_cmd(unit, &acb))
1634 {
1635 return IOERR_OPENFAIL;
1636 }
1637
1638 #if (AROS_BIG_ENDIAN != 0)
1639 SWAP_LE_WORD(unit->au_Drive->id_General);
1640 SWAP_LE_WORD(unit->au_Drive->id_OldCylinders);
1641 SWAP_LE_WORD(unit->au_Drive->id_SpecificConfig);
1642 SWAP_LE_WORD(unit->au_Drive->id_OldHeads);
1643 SWAP_LE_WORD(unit->au_Drive->id_OldSectors);
1644 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleSize);
1645 SWAP_LE_WORD(unit->au_Drive->id_Capabilities);
1646 SWAP_LE_WORD(unit->au_Drive->id_OldCaps);
1647 SWAP_LE_WORD(unit->au_Drive->id_OldPIO);
1648 SWAP_LE_WORD(unit->au_Drive->id_ConfigAvailable);
1649 SWAP_LE_WORD(unit->au_Drive->id_OldLCylinders);
1650 SWAP_LE_WORD(unit->au_Drive->id_OldLHeads);
1651 SWAP_LE_WORD(unit->au_Drive->id_OldLSectors);
1652 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleTrans);
1653 SWAP_LE_WORD(unit->au_Drive->id_MWDMASupport);
1654 SWAP_LE_WORD(unit->au_Drive->id_PIOSupport);
1655 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_MinCycleTime);
1656 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_DefCycleTime);
1657 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTime);
1658 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTImeIORDY);
1659 SWAP_LE_WORD(unit->au_Drive->id_QueueDepth);
1660 SWAP_LE_WORD(unit->au_Drive->id_ATAVersion);
1661 SWAP_LE_WORD(unit->au_Drive->id_ATARevision);
1662 SWAP_LE_WORD(unit->au_Drive->id_Commands1);
1663 SWAP_LE_WORD(unit->au_Drive->id_Commands2);
1664 SWAP_LE_WORD(unit->au_Drive->id_Commands3);
1665 SWAP_LE_WORD(unit->au_Drive->id_Commands4);
1666 SWAP_LE_WORD(unit->au_Drive->id_Commands5);
1667 SWAP_LE_WORD(unit->au_Drive->id_Commands6);
1668 SWAP_LE_WORD(unit->au_Drive->id_UDMASupport);
1669 SWAP_LE_WORD(unit->au_Drive->id_SecurityEraseTime);
1670 SWAP_LE_WORD(unit->au_Drive->id_ESecurityEraseTime);
1671 SWAP_LE_WORD(unit->au_Drive->id_CurrentAdvPowerMode);
1672 SWAP_LE_WORD(unit->au_Drive->id_MasterPwdRevision);
1673 SWAP_LE_WORD(unit->au_Drive->id_HWResetResult);
1674 SWAP_LE_WORD(unit->au_Drive->id_AcousticManagement);
1675 SWAP_LE_WORD(unit->au_Drive->id_StreamMinimunReqSize);
1676 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimeDMA);
1677 SWAP_LE_WORD(unit->au_Drive->id_StreamingLatency);
1678 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimePIO);
1679 SWAP_LE_WORD(unit->au_Drive->id_PhysSectorSize);
1680 SWAP_LE_WORD(unit->au_Drive->id_RemMediaStatusNotificationFeatures);
1681 SWAP_LE_WORD(unit->au_Drive->id_SecurityStatus);
1682
1683 SWAP_LE_LONG(unit->au_Drive->id_WordsPerLogicalSector);
1684 SWAP_LE_LONG(unit->au_Drive->id_LBASectors);
1685 SWAP_LE_LONG(unit->au_Drive->id_StreamingGranularity);
1686
1687 SWAP_LE_QUAD(unit->au_Drive->id_LBA48Sectors);
1688 #endif
1689
1690 DUMP(dump(unit->au_Drive, sizeof(struct DriveIdent)));
1691
1692 unit->au_SectorShift = 9;
1693 unit->au_DevType = DG_DIRECT_ACCESS;
1694 unit->au_Read32 = ata_ReadSector32;
1695 unit->au_Write32 = ata_WriteSector32;
1696 unit->au_DirectSCSI = atapi_DirectSCSI;
1697 unit->au_Eject = ata_Eject;
1698 unit->au_XferModes = 0;
1699 unit->au_Flags |= AF_DiscPresent | AF_DiscChanged;
1700 unit->au_DevType = DG_DIRECT_ACCESS;
1701
1702 ata_strcpy(unit->au_Drive->id_Model, unit->au_Model, 40);
1703 ata_strcpy(unit->au_Drive->id_SerialNumber, unit->au_SerialNumber, 20);
1704 ata_strcpy(unit->au_Drive->id_FirmwareRev, unit->au_FirmwareRev, 8);
1705
1706 bug("[ATA%02ld] ata_Identify: Unit info: %s / %s / %s\n", unit->au_UnitNum, unit->au_Model, unit->au_SerialNumber, unit->au_FirmwareRev);
1707 common_DetectXferModes(unit);
1708 common_SetBestXferMode(unit);
1709
1710 if (unit->au_Drive->id_General & 0x80)
1711 {
1712 DINIT(bug("[ATA%02ld] ata_Identify: Device is removable.\n", unit->au_UnitNum));
1713 unit->au_Flags |= AF_Removable;
1714 }
1715
1716 unit->au_Capacity = unit->au_Drive->id_LBASectors;
1717 unit->au_Capacity48 = unit->au_Drive->id_LBA48Sectors;
1718 bug("[ATA%02ld] ata_Identify: Unit info: %07lx 28bit / %04lx:%08lx 48bit addressable blocks\n", unit->au_UnitNum, unit->au_Capacity, (ULONG)(unit->au_Capacity48 >> 32), (ULONG)(unit->au_Capacity48 & 0xfffffffful));
1719
1720 /*
1721 For drive capacities > 8.3GB assume maximal possible layout.
1722 It really doesn't matter here, as BIOS will not handle them in
1723 CHS way anyway :)
1724 i guess this just solves that weirdo div-by-zero crash, if nothing else...
1725 */
1726 if ((unit->au_Drive->id_LBA48Sectors > (63 * 255 * 1024)) ||
1727 (unit->au_Drive->id_LBASectors > (63 * 255 * 1024)))
1728 {
1729 ULONG div = 1;
1730 /*
1731 * TODO: this shouldn't be casted down here.
1732 */
1733 ULONG sec = unit->au_Capacity48;
1734
1735 if (sec < unit->au_Capacity48)
1736 sec = ~0ul;
1737
1738 if (sec < unit->au_Capacity)
1739 sec = unit->au_Capacity;
1740
1741 unit->au_Sectors = 63;
1742 sec /= 63;
1743 /*
1744 * keep dividing by 2
1745 */
1746 do
1747 {
1748 if (((sec >> 1) << 1) != sec)
1749 break;
1750 if ((div << 1) > 255)
1751 break;
1752 div <<= 1;
1753 sec >>= 1;
1754 } while (1);
1755
1756 do
1757 {
1758 if (((sec / 3) * 3) != sec)
1759 break;
1760 if ((div * 3) > 255)
1761 break;
1762 div *= 3;
1763 sec /= 3;
1764 } while (1);
1765
1766 unit->au_Cylinders = sec;
1767 unit->au_Heads = div;
1768 }
1769 else
1770 {
1771 unit->au_Cylinders = unit->au_Drive->id_OldLCylinders;
1772 unit->au_Heads = unit->au_Drive->id_OldLHeads;
1773 unit->au_Sectors = unit->au_Drive->id_OldLSectors;
1774 }
1775 return 0;
1776 }
1777
1778
1779 /*
1780 * ata read32 commands
1781 */
1782 static ULONG ata_ReadSector32(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
1783 {
1784 ata_CommandBlock acb =
1785 {
1786 ATA_READ,
1787 0,
1788 1,
1789 0,
1790 block,
1791 count,
1792 buffer,
1793 count << unit->au_SectorShift,
1794 0,
1795 CM_PIORead,
1796 CT_LBA28
1797 };
1798 register ULONG err;
1799
1800 D(bug("[ATA%02ld] ata_ReadSector32()\n", unit->au_UnitNum));
1801
1802 *act = 0;
1803 if (0 != (err = ata_exec_blk(unit, &acb)))
1804 return err;
1805
1806 *act = count << unit->au_SectorShift;
1807 return 0;
1808 }
1809
1810 static ULONG ata_ReadMultiple32(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
1811 {
1812 ata_CommandBlock acb =
1813 {
1814 ATA_READ_MULTIPLE,
1815 0,
1816 unit->au_Drive->id_RWMultipleSize & 0xff,
1817 0,
1818 block,
1819 count,
1820 buffer,
1821 count << unit->au_SectorShift,
1822 0,
1823 CM_PIORead,
1824 CT_LBA28
1825 };
1826 register ULONG err;
1827
1828 D(bug("[ATA%02ld] ata_ReadMultiple32()\n", unit->au_UnitNum));
1829
1830 *act = 0;
1831 if (0 != (err = ata_exec_blk(unit, &acb)))
1832 return err;
1833
1834 *act = count << unit->au_SectorShift;
1835 return 0;
1836 }
1837
1838 static ULONG ata_ReadDMA32(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
1839 {
1840 register ULONG err;
1841 ata_CommandBlock acb =
1842 {
1843 ATA_READ_DMA,
1844 0,
1845 1,
1846 0,
1847 block,
1848 count,
1849 buffer,
1850 count << unit->au_SectorShift,
1851 0,
1852 CM_DMARead,
1853 CT_LBA28
1854 };
1855
1856 D(bug("[ATA%02ld] ata_ReadDMA32()\n", unit->au_UnitNum));
1857
1858 *act = 0;
1859 if (0 != (err = ata_exec_blk(unit, &acb)))
1860 return err;
1861
1862 *act = count << unit->au_SectorShift;
1863 return 0;
1864 }
1865
1866
1867 /*
1868 * ata read64 commands
1869 */
1870 static ULONG ata_ReadSector64(struct ata_Unit *unit, UQUAD block, ULONG count, APTR buffer, ULONG *act)
1871 {
1872 ata_CommandBlock acb =
1873 {
1874 ATA_READ64,
1875 0,
1876 1,
1877 0,
1878 block,
1879 count,
1880 buffer,
1881 count << unit->au_SectorShift,
1882 0,
1883 CM_PIORead,
1884 CT_LBA48
1885 };
1886 register ULONG err = 0;
1887
1888 D(bug("[ATA%02ld] ata_ReadSector64()\n", unit->au_UnitNum));
1889
1890 *act = 0;
1891 if (0 != (err = ata_exec_blk(unit, &acb)))
1892 return err;
1893
1894 *act = count << unit->au_SectorShift;
1895 return 0;
1896 }
1897
1898 static ULONG ata_ReadMultiple64(struct ata_Unit *unit, UQUAD block, ULONG count, APTR buffer, ULONG *act)
1899 {
1900 ata_CommandBlock acb =
1901 {
1902 ATA_READ_MULTIPLE64,
1903 0,
1904 unit->au_Drive->id_RWMultipleSize & 0xff,
1905 0,
1906 block,
1907 count,
1908 buffer,
1909 count << unit->au_SectorShift,
1910 0,
1911 CM_PIORead,
1912 CT_LBA48
1913 };
1914 register ULONG err;
1915
1916 D(bug("[ATA%02ld] ata_ReadMultiple64()\n", unit->au_UnitNum));
1917
1918 *act = 0;
1919 if (0 != (err = ata_exec_blk(unit, &acb)))
1920 return err;
1921
1922 *act = count << unit->au_SectorShift;
1923 return 0;
1924 }
1925
1926 static ULONG ata_ReadDMA64(struct ata_Unit *unit, UQUAD block, ULONG count, APTR buffer, ULONG *act)
1927 {
1928 ata_CommandBlock acb =
1929 {
1930 ATA_READ_DMA64,
1931 0,
1932 1,
1933 0,
1934 block,
1935 count,
1936 buffer,
1937 count << unit->au_SectorShift,
1938 0,
1939 CM_DMARead,
1940 CT_LBA48
1941 };
1942 register ULONG err;
1943
1944 D(bug("[ATA%02ld] ata_ReadDMA64()\n", unit->au_UnitNum));
1945
1946 *act = 0;
1947 if (0 != (err = ata_exec_blk(unit, &acb)))
1948 return err;
1949
1950 *act = count << unit->au_SectorShift;
1951 return 0;
1952 }
1953
1954
1955 /*
1956 * ata write32 commands
1957 */
1958 static ULONG ata_WriteSector32(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
1959 {
1960 ata_CommandBlock acb =
1961 {
1962 ATA_WRITE,
1963 0,
1964 1,
1965 0,
1966 block,
1967 count,
1968 buffer,
1969 count << unit->au_SectorShift,
1970 0,
1971 CM_PIOWrite,
1972 CT_LBA28
1973 };
1974 register ULONG err;
1975
1976 D(bug("[ATA%02ld] ata_WriteSector32()\n", unit->au_UnitNum));
1977
1978 *act = 0;
1979 if (0 != (err = ata_exec_blk(unit, &acb)))
1980 return err;
1981
1982 *act = count << unit->au_SectorShift;
1983 return 0;
1984 }
1985
1986 static ULONG ata_WriteMultiple32(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
1987 {
1988 ata_CommandBlock acb =
1989 {
1990 ATA_WRITE_MULTIPLE,
1991 0,
1992 unit->au_Drive->id_RWMultipleSize & 0xff,
1993 0,
1994 block,
1995 count,
1996 buffer,
1997 count << unit->au_SectorShift,
1998 0,
1999 CM_PIOWrite,
2000 CT_LBA28
2001 };
2002 register ULONG err;
2003
2004 D(bug("[ATA%02ld] ata_WriteMultiple32()\n", unit->au_UnitNum));
2005
2006 *act = 0;
2007 if (0 != (err = ata_exec_blk(unit, &acb)))
2008 return err;
2009
2010 *act = count << unit->au_SectorShift;
2011 return 0;
2012 }
2013
2014 static ULONG ata_WriteDMA32(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
2015 {
2016 ata_CommandBlock acb =
2017 {
2018 ATA_WRITE_DMA,
2019 0,
2020 1,
2021 0,
2022 block,
2023 count,
2024 buffer,
2025 count << unit->au_SectorShift,
2026 0,
2027 CM_DMAWrite,
2028 CT_LBA28
2029 };
2030 register ULONG err;
2031
2032 D(bug("[ATA%02ld] ata_WriteDMA32()\n", unit->au_UnitNum));
2033
2034 *act = 0;
2035 if (0 != (err = ata_exec_blk(unit, &acb)))
2036 return err;
2037
2038 *act = count << unit->au_SectorShift;
2039 return 0;
2040 }
2041
2042
2043 /*
2044 * ata write64 commands
2045 */
2046 static ULONG ata_WriteSector64(struct ata_Unit *unit, UQUAD block, ULONG count, APTR buffer, ULONG *act)
2047 {
2048 ata_CommandBlock acb =
2049 {
2050 ATA_WRITE64,
2051 0,
2052 1,
2053 0,
2054 block,
2055 count,
2056 buffer,
2057 count << unit->au_SectorShift,
2058 0,
2059 CM_PIOWrite,
2060 CT_LBA48
2061 };
2062 register ULONG err;
2063
2064 D(bug("[ATA%02ld] ata_WriteSector64()\n", unit->au_UnitNum));
2065
2066 *act = 0;
2067 if (0 != (err = ata_exec_blk(unit, &acb)))
2068 return err;
2069
2070 *act = count << unit->au_SectorShift;
2071 return 0;
2072 }
2073
2074 static ULONG ata_WriteMultiple64(struct ata_Unit *unit, UQUAD block, ULONG count, APTR buffer, ULONG *act)
2075 {
2076 ata_CommandBlock acb =
2077 {
2078 ATA_WRITE_MULTIPLE64,
2079 0,
2080 unit->au_Drive->id_RWMultipleSize & 0xff,
2081 0,
2082 block,
2083 count,
2084 buffer,
2085 count << unit->au_SectorShift,
2086 0,
2087 CM_PIOWrite,
2088 CT_LBA48
2089 };
2090 register ULONG err;
2091
2092 D(bug("[ATA%02ld] ata_WriteMultiple64()\n", unit->au_UnitNum));
2093
2094 *act = 0;
2095 if (0 != (err = ata_exec_blk(unit, &acb)))
2096 return err;
2097
2098 *act = count << unit->au_SectorShift;
2099 return 0;
2100 }
2101
2102 static ULONG ata_WriteDMA64(struct ata_Unit *unit, UQUAD block, ULONG count, APTR buffer, ULONG *act)
2103 {
2104 ata_CommandBlock acb =
2105 {
2106 ATA_WRITE_DMA64,
2107 0,
2108 1,
2109 0,
2110 block,
2111 count,
2112 buffer,
2113 count << unit->au_SectorShift,
2114 0,
2115 CM_DMAWrite,
2116 CT_LBA48
2117 };
2118 register ULONG err;
2119
2120 D(bug("[ATA%02ld] ata_WriteDMA64()\n", unit->au_UnitNum));
2121
2122 *act = 0;
2123 if (0 != (err = ata_exec_blk(unit, &acb)))
2124 return err;
2125
2126 *act = count << unit->au_SectorShift;
2127 return 0;
2128 }
2129
2130 /*
2131 * ata miscellaneous commands
2132 */
2133 static ULONG ata_Eject(struct ata_Unit *unit)
2134 {
2135 ata_CommandBlock acb =
2136 {
2137 ATA_MEDIA_EJECT,
2138 0,
2139 0,
2140 0,
2141 0,
2142 0,
2143 0,
2144 0,
2145 0,
2146 CM_NoData,
2147 CT_NoBlock
2148 };
2149
2150 D(bug("[ATA%02ld] ata_Eject()\n", unit->au_UnitNum));
2151
2152 return ata_exec_cmd(unit, &acb);
2153 }
2154
2155 /*
2156 * atapi commands
2157 */
2158 int atapi_TestUnitOK(struct ata_Unit *unit)
2159 {
2160 UBYTE cmd[6] = {
2161 0
2162 };
2163 UBYTE sense[16] = {
2164 0
2165 };
2166 struct SCSICmd sc = {
2167 0
2168 };
2169
2170 D(bug("[ATA%02ld] atapi_TestUnitOK()\n", unit->au_UnitNum));
2171
2172 sc.scsi_Command = (void*) &cmd;
2173 sc.scsi_CmdLength = sizeof(cmd);
2174 sc.scsi_SenseData = (void*)&sense;
2175 sc.scsi_SenseLength = sizeof(sense);
2176 sc.scsi_Flags = SCSIF_AUTOSENSE;
2177
2178 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Testing Unit Ready sense...\n", unit->au_UnitNum));
2179 unit->au_DirectSCSI(unit, &sc);
2180 unit->au_SenseKey = sense[2];
2181
2182 /*
2183 * we may have just lost the disc...?
2184 */
2185 /*
2186 * per MMC, drives are expected to return 02-3a-0# status, when disc is not present
2187 * that would translate into following code:
2188 * int p1 = ((sense[2] == 2) && (sense[12] == 0x3a)) ? 1 : 0;
2189 * unfortunately, it's what MMC says, not what vendors code.
2190 */
2191 int p1 = (sense[2] == 2) ? 1 : 0;
2192 int p2 = (0 != (AF_DiscPresent & unit->au_Flags)) ? 1 : 0;
2193
2194 if (p1 == p2)
2195 {
2196 //unit->au_Flags ^= AF_DiscPresent;
2197 if (p1 == 0)
2198 unit->au_Flags |= AF_DiscPresent;
2199 else
2200 unit->au_Flags &= ~AF_DiscPresent;
2201
2202 unit->au_Flags |= AF_DiscChanged;
2203 }
2204
2205 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Test Unit Ready sense: %02lx, Media %s\n", unit->au_UnitNum, sense[2], unit->au_Flags & AF_DiscPresent ? "PRESENT" : "ABSENT"));
2206 return sense[2];
2207 }
2208
2209 static ULONG atapi_Read(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
2210 {
2211 UBYTE cmd[] = {
2212 SCSI_READ10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
2213 };
2214 struct SCSICmd sc = {
2215 0
2216 };
2217
2218 D(bug("[ATA%02ld] atapi_Read()\n", unit->au_UnitNum));
2219
2220 sc.scsi_Command = (void*) &cmd;
2221 sc.scsi_CmdLength = sizeof(cmd);
2222 sc.scsi_Data = buffer;
2223 sc.scsi_Length = count << unit->au_SectorShift;
2224 sc.scsi_Flags = SCSIF_READ;
2225
2226 return unit->au_DirectSCSI(unit, &sc);
2227 }
2228
2229 static ULONG atapi_Write(struct ata_Unit *unit, ULONG block, ULONG count, APTR buffer, ULONG *act)
2230 {
2231 UBYTE cmd[] = {
2232 SCSI_WRITE10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
2233 };
2234 struct SCSICmd sc = {
2235 0
2236 };
2237
2238 D(bug("[ATA%02ld] atapi_Write()\n", unit->au_UnitNum));
2239
2240 sc.scsi_Command = (void*) &cmd;
2241 sc.scsi_CmdLength = sizeof(cmd);
2242 sc.scsi_Data = buffer;
2243 sc.scsi_Length = count << unit->au_SectorShift;
2244 sc.scsi_Flags = SCSIF_WRITE;
2245
2246 return unit->au_DirectSCSI(unit, &sc);
2247 }
2248
2249 static ULONG atapi_Eject(struct ata_Unit *unit)
2250 {
2251 struct atapi_StartStop cmd = {
2252 command: SCSI_STARTSTOP,
2253 immediate: 1,
2254 flags: ATAPI_SS_EJECT,
2255 };
2256
2257 struct SCSICmd sc = {
2258 0
2259 };
2260
2261 D(bug("[ATA%02ld] atapi_Eject()\n", unit->au_UnitNum));
2262
2263 sc.scsi_Command = (void*) &cmd;
2264 sc.scsi_CmdLength = sizeof(cmd);
2265 sc.scsi_Flags = SCSIF_READ;
2266
2267 return unit->au_DirectSCSI(unit, &sc);
2268 }
2269
2270 ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense, ULONG senselen)
2271 {
2272 UBYTE cmd[] = {
2273 3, 0, 0, 0, senselen & 0xfe, 0
2274 };
2275 struct SCSICmd sc = {
2276 0
2277 };
2278
2279 D(bug("[ATA%02ld] atapi_RequestSense()\n", unit->au_UnitNum));
2280
2281 if ((senselen == 0) || (sense == 0))
2282 {
2283 return 0;
2284 }
2285 sc.scsi_Data = (void*)sense;
2286 sc.scsi_Length = senselen & 0xfe;
2287 sc.scsi_Command = (void*)&cmd;
2288 sc.scsi_CmdLength = 6;
2289 sc.scsi_Flags = SCSIF_READ;
2290
2291 unit->au_DirectSCSI(unit, &sc);
2292
2293 DATAPI(dump(sense, senselen));
2294 DATAPI(bug("[SENSE] atapi_RequestSense: sensed data: %lx %lx %lx\n", sense[2]&0xf, sense[12], sense[13]));
2295 return ((sense[2]&0xf)<<16) | (sense[12]<<8) | (sense[13]);
2296 }
2297
2298 ULONG ata_ReadSignature(struct ata_Bus *bus, int unit)
2299 {
2300 ULONG port = bus->ab_Port;
2301 UBYTE tmp1, tmp2;
2302
2303 D(bug("[ATA ] ata_ReadSignature(%02ld)\n", unit));
2304
2305 ata_out(0xa0 | (unit << 4), ata_DevHead, port);
2306 ata_WaitNano(400);
2307 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2308
2309 /* Check basic signature. All live devices should provide it */
2310 tmp1 = ata_in(ata_Count, port);
2311 tmp2 = ata_in(ata_LBALow, port);
2312 DINIT(bug("[ATA ] ata_ReadSignature: Checking Count / LBA against expected values (%d:%d)\n", tmp1, tmp2));
2313
2314 DINIT(bug("[ATA ] ata_ReadSignature: Status %08lx Device %08lx\n", ata_in(ata_Status, port), ata_in(ata_DevHead, port)));
2315
2316 if ((tmp1 == 0x01) && (tmp2 == 0x01))
2317 {
2318 /* Ok, ATA/ATAPI device. Get detailed signature */
2319 DINIT(bug("[ATA ] ata_ReadSignature: Found an ATA[PI] Device. Attempting to detect specific subtype\n"));
2320
2321 tmp1 = ata_in(ata_LBAMid, port);
2322 tmp2 = ata_in(ata_LBAHigh, port);
2323
2324 DINIT(bug("[ATA ] ata_ReadSignature: Subtype check returned %02lx:%02lx (%04lx)\n", tmp1, tmp2, (tmp1 << 8) | tmp2));
2325
2326 switch ((tmp1 << 8) | tmp2)
2327 {
2328 case 0x0000:
2329 if (0 == (ata_ReadStatus(bus) & 0xfe))
2330 return DEV_NONE;
2331 ata_out(ATA_EXECUTE_DIAG, ata_Command, port);
2332
2333 ata_WaitTO(bus->ab_Timer, 0, 2000, 0);
2334 while (ata_ReadStatus(bus) & ATAF_BUSY)
2335 ata_WaitNano(400);
2336 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2337
2338 ata_out(0xa0 | (unit << 4), ata_DevHead, port);
2339 do
2340 {
2341 ata_WaitNano(400);
2342 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
2343 }
2344 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
2345 DINIT(bug("[ATA ] ata_ReadSignature: Further validating ATA signature: %lx & 0x7f = 1, %lx & 0x10 = unit\n", ata_in(ata_Error, port), ata_in(ata_DevHead, port)));
2346
2347 if ((ata_in(ata_Error, port) & 0x7f) == 1)
2348 {
2349 DINIT(bug("[ATA ] ata_ReadSignature: Found *valid* signature for ATA device\n"));
2350 return DEV_ATA;
2351 }
2352 bug("[ATA ] ata_ReadSignature: Found signature for ATA "
2353 "device, but further validation failed\n");
2354 return DEV_NONE;
2355
2356 case 0x14eb:
2357 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for ATAPI device\n"));
2358 return DEV_ATAPI;
2359
2360 case 0x3cc3:
2361 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATA device\n"));
2362 return DEV_SATA;
2363
2364 case 0x6996:
2365 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATAPI device\n"));
2366 return DEV_SATAPI;
2367
2368 default:
2369 if (((tmp1 | tmp2) == 0xff) &&
2370 ((tmp1 & tmp2) == 0x00))
2371 {
2372 bug("[ATA ] ata_ReadSignature: Found valid subtype, but don't know how to handle this device: %02lx %02lx\n", tmp1, tmp2);
2373 }
2374 else
2375 {
2376 bug("[ATA ] ata_ReadSignature: Invalid signature: %02lx %02lx\n", tmp1, tmp2);
2377 }
2378 return DEV_NONE;
2379 }
2380 }
2381
2382 return DEV_NONE;
2383 }
2384
2385 void ata_ResetBus(struct ata_Bus *bus)
2386 {
2387
2388 ULONG alt = bus->ab_Alt;
2389 ULONG port = bus->ab_Port;
2390 ULONG TimeOut;
2391
2392 /* Set and then reset the soft reset bit in the Device Control
2393 * register. This causes device 0 be selected */
2394 D(bug("[ATA ] ata_ResetBus(%d)\n", bus->ab_BusNum));
2395 ata_out(0xa0 | (0 << 4), ata_DevHead, port); /* Select it never the less */
2396 ata_WaitNano(400);
2397 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2398
2399 ata_out(0x04, ata_AltControl, alt);
2400 ata_WaitTO(bus->ab_Timer, 0, 10, 0); /* sleep 10us; min: 5us */
2401 ata_out(0x02, ata_AltControl, alt);
2402 ata_WaitTO(bus->ab_Timer, 0, 20000, 0); /* sleep 20ms; min: 2ms */
2403
2404 /* If there is a device 0, wait for device 0 to clear BSY */
2405 if (DEV_NONE != bus->ab_Dev[0]) {
2406 D(bug("[ATA%02ld] ata_ResetBus: Wait for Device to clear BSY\n", ((bus->ab_BusNum << 1 ) + 0)));
2407 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2408 while ( 1 ) {
2409 if( (ata_ReadStatus(bus) & ATAF_BUSY) == 0 )
2410 break;
2411 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2412 if (!(--TimeOut)) {
2413 D(bug("[ATA%02ld] ata_ResetBus: Device Timed Out!\n", ((bus->ab_BusNum << 1 ) + 0)));
2414 bus->ab_Dev[0] = DEV_NONE;
2415 break;
2416 }
2417 }
2418 D(bug("[ATA%02ld] ata_ResetBus: Wait left after %d ms\n", ((bus->ab_BusNum << 1 ) + 0), (1000 - TimeOut)));
2419 }
2420
2421 /* If there is a device 1, wait until device 1 allows
2422 * register access */
2423 if (DEV_NONE != bus->ab_Dev[1]) {
2424 D(bug("[ATA ] ata_ResetBus: Wait DEV1 to allow access\n"));
2425 ata_out(0xa0 | (1 << 4), ata_DevHead, port);
2426 ata_WaitNano(400);
2427 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2428 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2429 while ( 1 ) {
2430 if ( (ata_in(2, port) == 0x01) && (ata_in(3, port) == 0x01) )
2431 break;
2432 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2433 if (!(--TimeOut)) {
2434 D(bug("[ATA ] ata_ResetBus: DEV1 1/2 TimeOut!\n"));
2435 bus->ab_Dev[1] = DEV_NONE;
2436 break;
2437 }
2438 }
2439 D(bug("[ATA ] ata_ResetBus: DEV1 1/2 Wait left after %d ms\n", (1000 - TimeOut)));
2440
2441 if (DEV_NONE != bus->ab_Dev[1]) {
2442 D(bug("[ATA%02ld] ata_ResetBus: Wait for Device to clear BSY\n", ((bus->ab_BusNum << 1 ) + 1)));
2443 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2444 while ( 1 ) {
2445 if( (ata_ReadStatus(bus) & ATAF_BUSY) == 0 )
2446 break;
2447 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2448 if (!(--TimeOut)) {
2449 D(bug("[ATA%02ld] ata_ResetBus: Device Timed Out!\n", ((bus->ab_BusNum << 1 ) + 1)));
2450 bus->ab_Dev[1] = DEV_NONE;
2451 break;
2452 }
2453 }
2454 D(bug("[ATA%02ld] ata_ResetBus: Wait left after %d ms\n", ((bus->ab_BusNum << 1 ) + 1), 1000 - TimeOut));
2455 }
2456 }
2457
2458 if (DEV_NONE != bus->ab_Dev[0])
2459 bus->ab_Dev[0] = ata_ReadSignature(bus, 0);
2460 if (DEV_NONE != bus->ab_Dev[1])
2461 bus->ab_Dev[1] = ata_ReadSignature(bus, 1);
2462 }
2463
2464 void ata_InitBus(struct ata_Bus *bus)
2465 {
2466 ULONG port = bus->ab_Port;
2467 UBYTE tmp1, tmp2;
2468
2469 /*
2470 * initialize timer for the sake of scanning
2471 */
2472 bus->ab_Timer = ata_OpenTimer();
2473
2474 D(bug("[ATA ] ata_InitBus(%d)\n", bus->ab_BusNum));
2475
2476 bus->ab_Dev[0] = DEV_NONE;
2477 bus->ab_Dev[1] = DEV_NONE;
2478
2479 /* Select device 0 and disable IRQs */
2480 ata_out(0xa0, ata_DevHead, port);
2481 ata_WaitTO(bus->ab_Timer, 0, 100, 0);
2482 ata_out(0x2, ata_AltControl, bus->ab_Alt);
2483
2484 /* Write some pattern to registers */
2485 ata_out(0x55, ata_Count, port);
2486 ata_out(0xaa, ata_LBALow, port);
2487 ata_out(0xaa, ata_Count, port);
2488 ata_out(0x55, ata_LBALow, port);
2489 ata_out(0x55, ata_Count, port);
2490 ata_out(0xaa, ata_LBALow, port);
2491
2492 tmp1 = ata_in(ata_Count, port);
2493 tmp2 = ata_in(ata_LBALow, port);
2494
2495 if ((tmp1 == 0x55) && (tmp2 == 0xaa))
2496 bus->ab_Dev[0] = DEV_UNKNOWN;
2497 D(bug("[ATA%02ld] ata_InitBus: Device type = %x\n", (bus->ab_BusNum << 1 ) + 0, bus->ab_Dev[0]));
2498
2499 /* Select device 1 and disable IRQs */
2500 ata_out(0xb0, ata_DevHead, port);
2501 ata_WaitTO(bus->ab_Timer, 0, 100, 0);
2502 ata_out(0x2, ata_AltControl, bus->ab_Alt);
2503
2504 /* Write some pattern to registers */
2505 ata_out(0x55, ata_Count, port);
2506 ata_out(0xaa, ata_LBALow, port);
2507 ata_out(0xaa, ata_Count, port);
2508 ata_out(0x55, ata_LBALow, port);
2509 ata_out(0x55, ata_Count, port);
2510 ata_out(0xaa, ata_LBALow, port);
2511
2512 tmp1 = ata_in(ata_Count, port);
2513 tmp2 = ata_in(ata_LBALow, port);
2514
2515 if ((tmp1 == 0x55) && (tmp2 == 0xaa))
2516 bus->ab_Dev[1] = DEV_UNKNOWN;
2517 D(bug("[ATA%02ld] ata_InitBus: Device type = %x\n", (bus->ab_BusNum << 1 ) + 1, bus->ab_Dev[1]));
2518
2519 ata_ResetBus(bus);
2520 ata_CloseTimer(bus->ab_Timer);
2521 D(bug("[ATA ] ata_InitBus: Finished\n"));
2522 }
2523
2524 /*
2525 * not really sure what this is meant to be - TO BE REPLACED
2526 */
2527 static const ULONG ErrorMap[] = {
2528 CDERR_NotSpecified,
2529 CDERR_NoSecHdr,
2530 CDERR_NoDisk,
2531 CDERR_NoSecHdr,
2532 CDERR_NoSecHdr,
2533 CDERR_NOCMD,
2534 CDERR_NoDisk,
2535 CDERR_WriteProt,
2536 CDERR_NotSpecified,
2537 CDERR_NotSpecified,
2538 CDERR_NotSpecified,
2539 CDERR_ABORTED,
2540 CDERR_NotSpecified,
2541 CDERR_NotSpecified,
2542 CDERR_NoSecHdr,
2543 CDERR_NotSpecified,
2544 };
2545
2546 static ULONG atapi_EndCmd(struct ata_Unit *unit)
2547 {
2548 UBYTE status;
2549
2550 DATAPI(bug("[ATA%02ld] atapi_EndCmd()\n", unit->au_UnitNum));
2551
2552 /*
2553 * read alternate status register (per specs)
2554 */
2555 status = ata_in(ata_AltStatus, unit->au_Bus->ab_Alt);
2556 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Alternate status: %lx\n", unit->au_UnitNum, status));
2557
2558 status = ata_in(atapi_Status, unit->au_Bus->ab_Port);
2559
2560 DATAPI(bug("[ATAPI] atapi_EndCmd: Command complete. Status: %lx\n", unit->au_UnitNum, status));
2561
2562 if (!(status & ATAPIF_CHECK))
2563 {
2564 return 0;
2565 }
2566 else
2567 {
2568 status = ata_in(atapi_Error, unit->au_Bus->ab_Port);
2569 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Error code 0x%lx\n", unit->au_UnitNum, status >> 4));
2570 return ErrorMap[status >> 4];
2571 }
2572 }
2573
2574 /*
2575 * vim: ts=4 et sw=4 fdm=marker fmr={,}
2576 */
The AROS cake. Goodness baked in, have it and eat it too. Delicious!