arch/common/hidd.intelG33/intelG33_regs.h

   1
   2 #include <inttypes.h>
   3
   4 /*
   5 Address Range Description
   6 MMADR+
   7 00000h 00FFFh VGA and Extended VGA Control Registers. These registers are located in both
   8               I/O space and memory space. The VGA and Extended VGA registers contain the
   9               following register sets: General Control/Status, Sequencer (SRxx), Graphics
  10               Controller (GRxx), Attribute Controller (Arxx), VGA Color Palette, and CRT Controller
  11               (CRxx) registers. Detailed bit descriptions are provided in the VGA and Extended VGA
  12               Register Chapter. The registers within a set are accessed using an indirect addressing
  13               mechanism as described at the beginning of each section. Note that some of the
  14               register description sections have additional operational information at the beginning
  15               of the section
  16 01000h 01FFFh Reserved
  17 02000h 02FFFh Instruction, Memory, and Interrupt Control Registers:
  18               Instruction Control Registers Ring Buffer registers and page table control
  19               registers are located in this address range. Various instruction status, error, and
  20               operating registers are located in this group of registers.
  21               Graphics Memory Fence Registers. The Graphics Memory Fence registers are
  22               used for memory tiling capabilities.
  23               Interrupt Control/Status Registers. This register set provides interrupt
  24               control/status for various GC functions.
  25               Display Interface Control Register. This register controls the FIFO watermark and
  26               provides burst length control.
  27               Logical Context Registers
  28               Software Visible Counters
  29 03000h 031FFh FENCE & Per Process GTT Control registers
  30 03200h 03FFFh Frame Buffer Compression Registers
  31 04000h 043FFh Reserved.
  32 04400h 04FFFh Reserved.
  33 05000h 05FFFh I/O Control Registers
  34 06000h 06FFFh Clock Control Registers. This memory address space is the location of the GC clock
  35               control and power management registers
  36 07000h 073FFh 3D Internal Debug Registers
  37 07400h 088FFh GPE Debug Registers (3D/Media Fixed Functions)
  38 08900h 08FFFh Reserved for Subsystem Debug Registers
  39 09000h 09FFFh Reserved
  40 0A000h 0AFFFh Display Palette Registers
  41 0B000h 0FFFFh Reserved
  42 10000h 13FFFh MMIO MCHBAR. Alias through which the graphics driver can access registers in the
  43               MCHBAR accessed through device 0.
  44 14000h 2FFFFh Reserved
  45 30000h 3FFFFh Overlay Registers. These registers provide control of the overlay engine. The
  46               overlay registers are double-buffered with one register buffer located in graphics
  47               memory and the other on the device. On-chip registers are not directly writeable. To
  48               update the on-chip registers software writes to the register buffer area in graphics
  49               memory and instructs the device to update the on-chip registers.
  50 40000h 5FFFFh Reserved
  51 60000h 6FFFFh Display Engine Pipeline Registers
  52 70000h 72FFFh Display and Cursor Registers
  53 73000h 73FFFh Performance Counters
  54 74000h 7FFFFh Reserved
  55 */
  56
  57 #define INTEL_VENDOR_ID     0x8086
  58
  59 #define IS_G33(id) (id == 0x29b2 || \
  60                     id == 0x29c2 || \
  61                     id == 0x29d2)
  62
  63 #define readl(addr) ( *(volatile uint32_t *) (addr) )
  64 #define readw(addr) ( *(volatile uint16_t *) (addr) )
  65 #define readb(addr) ( *(volatile uint8_t *)  (addr) )
  66
  67 #define writeb(b,addr) ( (*(volatile uint8_t *)  (addr)) = (b) )
  68 #define writew(b,addr) ( (*(volatile uint16_t *) (addr)) = (b) )
  69 #define writel(b,addr) ( (*(volatile uint32_t *) (addr)) = (b) )
  70
  71 #define G33_RD_REGL(a, reg) ( readl(sd->Chipset.a + reg) )
  72 #define G33_RD_REGW(a, reg) ( readw(sd->Chipset.a + reg) )
  73 #define G33_RD_REGB(a, reg) ( readb(sd->Chipset.a + reg) )
  74
  75 #define G33_WR_REGL(a, reg, value) ( writel((value), (sd->Chipset.a + reg)) )
  76 #define G33_WR_REGW(a, reg, value) ( writew((value), (sd->Chipset.a + reg)) )
  77 #define G33_WR_REGB(a, reg, value) ( writeb((value), (sd->Chipset.a + reg)) )
  78
  79 /* Should get away with this... or not... */
  80 #define G33_SETBMASK_REGL(a, reg, value) ( writel((readl(sd->Chipset.a + reg )|value), (sd->Chipset.a + reg)) )
  81 #define G33_SETBMASK_REGW(a, reg, value) ( writew((readw(sd->Chipset.a + reg )|value), (sd->Chipset.a + reg)) )
  82 #define G33_SETBMASK_REGB(a, reg, value) ( writeb((readb(sd->Chipset.a + reg )|value), (sd->Chipset.a + reg)) )
  83
  84 #define G33_CLRBMASK_REGL(a, reg, value) ( writel((readl(sd->Chipset.a + reg )&(~value)), (sd->Chipset.a + reg)) )
  85 #define G33_CLRBMASK_REGW(a, reg, value) ( writew((readw(sd->Chipset.a + reg )&(~value)), (sd->Chipset.a + reg)) )
  86 #define G33_CLRBMASK_REGB(a, reg, value) ( writeb((readb(sd->Chipset.a + reg )&(~value)), (sd->Chipset.a + reg)) )
  87
  88 #define G33_WRM_REGL(a, reg, value, mask) ( writel( (((readl(sd->Chipset.a + reg )&(~mask)))&value), (sd->Chipset.a + reg)) )
  89 #define G33_WRM_REGW(a, reg, value, mask) ( writew( (((readw(sd->Chipset.a + reg )&(~mask)))&value), (sd->Chipset.a + reg)) )
  90 #define G33_WRM_REGB(a, reg, value, mask) ( writeb( (((readb(sd->Chipset.a + reg )&(~mask)))&value), (sd->Chipset.a + reg)) )
  91
  92 #define G33_RD_REG_ARRAY(a, reg, offset) ( readl((sd->Chipset.a + reg) + ((offset) << 2)) )
  93 #define G33_WR_REG_ARRAY(a, reg, offset, value) ( writel((value), ((sd->Chipset.a + reg) + ((offset) << 2))) )
  94
  95 #define MEMORY_CONTROL_ENABLED      0x0004
  96 #define MEMORY_MASK                 0x0001
  97
  98 #define STOLEN_MEMORY_MASK          0x00f0
  99 #define STOLEN_MEMORY_1M            0x0010
 100 #define STOLEN_MEMORY_4M            0x0020
 101 #define STOLEN_MEMORY_8M            0x0030
 102 #define STOLEN_MEMORY_16M           0x0040
 103 #define STOLEN_MEMORY_32M           0x0050
 104 #define STOLEN_MEMORY_48M           0x0060
 105 #define STOLEN_MEMORY_64M           0x0070
 106 #define STOLEN_MEMORY_128M          0x0080
 107 #define STOLEN_MEMORY_256M          0x0090
 108 #define STOLEN_MEMORY_96M           0x00a0
 109 #define STOLEN_MEMORY_160M          0x00b0
 110 #define STOLEN_MEMORY_224M          0x00c0
 111 #define STOLEN_MEMORY_352M          0x00d0
 112
 113 #define GTT_MASK                    0x0300
 114 #define GTT_1M                      0x0100
 115 #define GTT_2M                      0x0200
 116
 117 /* I/O Control Registers (05000h−05FFFh) */
 118 #define GMBUSRate1MHz               3<<8
 119 #define GMBUSRate400KHz             2<<8
 120 #define GMBUSRate100KHz             0
 121 #define GMBUSRate50KHz              1<<8
 122 #define GMBUSHTimeExt               1<<7
 123
 124 #define GMBUS0      0x5100
 125 #define GMBUS1      0x5104
 126 #define GMBUS2      0x5108
 127 #define GMBUS3      0x510c
 128 #define GMBUS4      0x5110
 129 #define GMBUS5      0x5120
 130
 131 #define ADPA        0x61100     /* Analog display port A*/
 132 #define DDPBC       0x61140     /* Digital display port B control */
 133 #define DDPCC       0x61160     /* Digital display port C control */
 134 #define LVDS        0x61180     /* Digital display port control*/
 135
 136 #define DPMSMASK    0x0c00
 137
 138 #define VGADisable  1<<31
 139 #define VGACNTRL    0x71400
 140
 141