arch/common/hidd.pci/pci.h

   1 #ifndef _PCI_H
   2 #define _PCI_H
   3
   4 /*
   5     Copyright © 2004-2007, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8
   9 /*
  10  * 2008-03-30 T. Wiszkowski  Corrected typo and added InterruptStatus, CapabilitiesPresent attributes
  11  */
  12
  13 #include <exec/types.h>
  14 #include <exec/libraries.h>
  15 #include <exec/execbase.h>
  16 #include <exec/nodes.h>
  17 #include <exec/lists.h>
  18 #include <exec/semaphores.h>
  19 #include <dos/bptr.h>
  20
  21 #include <aros/libcall.h>
  22 #include <aros/asmcall.h>
  23
  24 #include <oop/oop.h>
  25
  26 #include <aros/arossupportbase.h>
  27 #include <exec/execbase.h>
  28
  29 #include LC_LIBDEFS_FILE
  30
  31 /* Private data and structures unavailable outside the pci base classes */
  32
  33 struct DriverNode {
  34     struct Node         node;
  35     OOP_Class           *driverClass;   /* Driver class */
  36     OOP_Object          *driverObject;  /* Driver object */
  37     ULONG               highBus;
  38     struct List         devices;        /* List of defices behind this node */
  39 };
  40
  41 struct DrvInstData {
  42     BOOL DirectBus;
  43 };
  44
  45 struct PciDevice {
  46     struct MinNode      node;
  47     OOP_Object          *device;
  48 };
  49
  50 typedef struct DeviceData {
  51     OOP_Object          *driver;
  52     UBYTE               bus,dev,sub;
  53     UBYTE               isBridge;
  54     UBYTE               subbus;
  55     UWORD               VendorID;
  56     UWORD               ProductID;
  57     UBYTE               RevisionID;
  58     UBYTE               Interface;
  59     UBYTE               SubClass;
  60     UBYTE               Class;
  61     UWORD               SubsysVID;
  62     UWORD               SubsystemID;
  63     UBYTE               INTLine;
  64     UBYTE               IRQLine;
  65     UBYTE               HeaderType;
  66     struct {
  67         IPTR            addr;
  68         IPTR            size;
  69     } BaseReg[6];
  70     ULONG               RomBase;
  71     ULONG               RomSize;
  72
  73     STRPTR              strClass;
  74     STRPTR              strSubClass;
  75     STRPTR              strInterface;
  76 } tDeviceData;
  77
  78 struct pci_staticdata {
  79     struct SignalSemaphore driver_lock;
  80     struct List         drivers;
  81
  82     APTR                MemPool;
  83
  84     OOP_AttrBase        hiddAB;
  85     OOP_AttrBase        hiddPCIAB;
  86     OOP_AttrBase        hiddPCIDriverAB;
  87     OOP_AttrBase        hiddPCIBusAB;
  88     OOP_AttrBase        hiddPCIDeviceAB;
  89
  90     OOP_Class           *pciClass;
  91     OOP_Class           *pciDeviceClass;
  92     OOP_Class           *pciDriverClass;
  93
  94     ULONG               users;
  95
  96     /* Most commonly used methods have already the mID's stored here */
  97     OOP_MethodID        mid_RB;
  98     OOP_MethodID        mid_RW;
  99     OOP_MethodID        mid_RL;
 100     OOP_MethodID        mid_WB;
 101     OOP_MethodID        mid_WW;
 102     OOP_MethodID        mid_WL;
 103 };
 104
 105 struct pcibase {
 106     struct Library              LibNode;
 107     APTR                        MemPool;
 108     struct pci_staticdata       psd;
 109 };
 110
 111 OOP_Class *init_pcideviceclass(struct pci_staticdata *);
 112 void free_pcideviceclass(struct pci_staticdata *, OOP_Class *cl);
 113
 114 #define BASE(lib) ((struct pcibase*)(lib))
 115
 116 #define PSD(cl) (&BASE(cl->UserData)->psd)
 117
 118 /* PCI Configspace offsets */
 119 #define PCICS_VENDOR            0x00
 120 #define PCICS_PRODUCT           0x02
 121 #define PCICS_COMMAND           0x04
 122 #define PCICS_STATUS            0x06
 123 #define PCICS_REVISION          0x08
 124 #define PCICS_PROGIF            0x09
 125 #define PCICS_SUBCLASS          0x0a
 126 #define PCICS_CLASS             0x0b
 127 #define PCICS_CACHELS           0x0c
 128 #define PCICS_LATENCY           0x0d
 129 #define PCICS_HEADERTYPE        0x0e
 130 #define PCICS_BIST              0x0f
 131 #define PCICS_BAR0              0x10
 132 #define PCICS_BAR1              0x14
 133 #define PCICS_BAR2              0x18
 134 #define PCICS_BAR3              0x1c
 135 #define PCICS_BAR4              0x20
 136 #define PCICS_BAR5              0x24
 137 #define PCICS_CARDBUS_CIS       0x28
 138 #define PCICS_SUBVENDOR         0x2c
 139 #define PCICS_SUBSYSTEM         0x2e
 140 #define PCICS_EXPROM_BASE       0x30
 141 #define PCICS_CAP_PTR           0x34
 142 #define PCICS_INT_LINE          0x3c
 143 #define PCICS_INT_PIN           0x3d
 144 #define PCICS_MIN_GNT           0x3e
 145 #define PCICS_MAX_LAT           0x3f
 146
 147 /* PCI Headertypes */
 148 #define PCIHT_MASK              0x7f
 149 #define PCIHT_MULTIFUNC         0x80
 150
 151 #define PCIHT_NORMAL            0x00
 152 #define PCIHT_BRIDGE            0x01
 153 #define PCIHT_CARDBUS           0x02
 154
 155 /* PCI Command register bits */
 156 #define PCICMB_IODECODE         0
 157 #define PCICMB_MEMDECODE        1
 158 #define PCICMB_BUSMASTER        2
 159 #define PCICMB_SPECIAL          3
 160 #define PCICMB_INVALIDATE       4
 161 #define PCICMB_VGASNOOP         5
 162 #define PCICMB_PARITY           6
 163 #define PCICMB_STEPPING         7
 164 #define PCICMB_SERR             8
 165 #define PCICMB_FASTB2B          9
 166
 167 #define PCICMF_IODECODE         (1 << PCICMB_IODECODE)
 168 #define PCICMF_MEMDECODE        (1 << PCICMB_MEMDECODE)
 169 #define PCICMF_BUSMASTER        (1 << PCICMB_BUSMASTER)
 170 #define PCICMF_SPECIAL          (1 << PCICMB_SPECIAL)
 171 #define PCICMF_INVALIDATE       (1 << PCICMB_INVALIDATE)
 172 #define PCICMF_VGASNOOP         (1 << PCICMB_VGASNOOP)
 173 #define PCICMF_PARITY           (1 << PCICMB_PARITY)
 174 #define PCICMF_STEPPING         (1 << PCICMB_STEPPING)
 175 #define PCICMF_SERR             (1 << PCICMB_SERR)
 176 #define PCICMF_FASTB2B          (1 << PCICMB_FASTB2B)
 177
 178 /* PCI Status register bits */
 179 #define PCISTB_INTERRUPT_STATUS 3       /* might be AHCI specific */
 180 #define PCISTB_CAPABILITES      4
 181 #define PCISTB_66MHZ            5
 182 #define PCISTB_FASTB2B          7
 183 #define PCISTB_PARITY           8
 184 #define PCISTB_SIG_TGT_ABORT    11
 185 #define PCISTB_REC_TGT_ABORT    12
 186 #define PCISTB_REC_MAS_ABORT    13
 187 #define PCISTB_SIG_SYSERR       14
 188 #define PCISTB_PARITYERR        15
 189
 190 #define PCISTF_INTERRUPT_STATUS (1 << PCISTB_INTERRUPT_STATUS)
 191 #define PCISTF_CAPABILITIES     (1 << PCISTB_CAPABILITES)
 192 #define PCISTF_66MHZ            (1 << PCISTB_66MHZ)
 193 #define PCISTF_FASTB2B          (1 << PCISTB_FASTB2B)
 194 #define PCISTF_PARITY           (1 << PCISTB_PARITY)
 195 #define PCISTF_SIG_TGT_ABORT    (1 << PCISTB_SIG_TGT_ABORT)
 196 #define PCISTF_REC_TGT_ABORT    (1 << PCISTB_REC_TGT_ABORT)
 197 #define PCISTF_REC_MAS_ABORT    (1 << PCISTB_REC_MAS_ABORT)
 198 #define PCISTF_SIG_SYSERR       (1 << PCISTB_SIG_SYSERR)
 199 #define PCISTF_PARITYERR        (1 << PCISTB_PARITYERR)
 200
 201 #define PCIST_DEVSEL_MASK       0x600
 202 #define PCIST_DEVSEL_FAST       0x000
 203 #define PCIST_DEVSEL_MEDIUM     0x200
 204 #define PCIST_DEVSEL_SLOW       0x400
 205
 206 /* PCI BIST register */
 207 #define PCIBSB_START            6
 208 #define PCIBSB_CAPABLE          7
 209
 210 #define PCIBSF_START            (1 << PCIBSB_START)
 211 #define PCIBSF_CAPABLE          (1 << PCIBSB_CAPABLE)
 212
 213 #define PCIBS_CODEMASK          0x0f
 214
 215 /* PCI BaseAddressRegister defines */
 216 #define PCIBAR_MASK_TYPE        0x01
 217 #define PCIBAR_TYPE_MMAP        0x00
 218 #define PCIBAR_TYPE_IO          0x01
 219 #define PCIBAR_MASK_MEM         0xfffffff0
 220 #define PCIBAR_MASK_IO          0xfffffffc
 221
 222 #define PCIBAR_MEMTYPE_MASK     0x06
 223 #define PCIBAR_MEMTYPE_32BIT    0x00
 224 #define PCIBAR_MEMTYPE_64BIT    0x04
 225
 226 #define PCIBARB_PREFETCHABLE    3
 227 #define PCIBARF_PREFETCHABLE    (1 << PCIBARB_PREFETCHABLE)
 228
 229 /*
 230  * PCI-to-PCI bridge header defines
 231  * First 16 bytes are the same as normal PCI dev
 232  */
 233 #define PCIBR_BAR0              0x10
 234 #define PCIBR_BAR1              0x14
 235 #define PCIBR_PRIBUS            0x18
 236 #define PCIBR_SECBUS            0x19
 237 #define PCIBR_SUBBUS            0x1a
 238 #define PCIBR_SECLATENCY        0x1b
 239 #define PCIBR_IOBASE            0x1c
 240 #define PCIBR_IOLIMIT           0x1d
 241 #define PCIBR_SECSTATUS         0x1e
 242 #define PCIBR_MEMBASE           0x20
 243 #define PCIBR_MEMLIMIT          0x22
 244 #define PCIBR_PREFETCHBASE      0x24
 245 #define PCIBR_PREFETCHLIMIT     0x26
 246 #define PCIBR_PREBASEUPPER      0x28
 247 #define PCIBR_PRELIMITUPPER     0x2c
 248 #define PCIBR_IOBASEUPPER       0x30
 249 #define PCIBR_IOLIMITUPPER      0x32
 250 #define PCIBR_CAPPTR            0x34
 251 #define PCIBR_EXPROMBASE        0x38
 252 #define PCIBR_INT_LINE          0x3c
 253 #define PCIBR_INT_PIN           0x3d
 254 #define PCIBR_CONTROL           0x3e
 255
 256 #define PCICTRLB_ISAENABLE      2
 257 #define PCICTRLB_VGAENABLE      3
 258
 259 #define PCICTRLF_ISAENABLE      (1 << PCICTRLB_ISAENABLE)
 260 #define PCICTRLF_VGAENABLE      (1 << PCICTRLF_ISAENABLE)
 261
 262 #endif /* _PCI_H */
 263