1 /* Instruction opcode table for fr30.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #include "fr30-desc.h"
32 /* The hash functions are recorded here to help keep assembler code out of
33 the disassembler and vice versa. */
35 static int asm_hash_insn_p
PARAMS ((const CGEN_INSN
*));
36 static unsigned int asm_hash_insn
PARAMS ((const char *));
37 static int dis_hash_insn_p
PARAMS ((const CGEN_INSN
*));
38 static unsigned int dis_hash_insn
PARAMS ((const char *, CGEN_INSN_INT
));
40 /* Instruction formats. */
42 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
44 static const CGEN_IFMT ifmt_empty
= {
48 static const CGEN_IFMT ifmt_add
= {
49 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RJ
), F (F_RI
), 0 }
52 static const CGEN_IFMT ifmt_addi
= {
53 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U4
), F (F_RI
), 0 }
56 static const CGEN_IFMT ifmt_add2
= {
57 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_M4
), F (F_RI
), 0 }
60 static const CGEN_IFMT ifmt_div0s
= {
61 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
64 static const CGEN_IFMT ifmt_div3
= {
65 16, 16, 0xffff, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_OP4
), 0 }
68 static const CGEN_IFMT ifmt_ldi8
= {
69 16, 16, 0xf000, { F (F_OP1
), F (F_I8
), F (F_RI
), 0 }
72 static const CGEN_IFMT ifmt_ldi20
= {
73 16, 32, 0xff00, { F (F_OP1
), F (F_I20
), F (F_OP2
), F (F_RI
), 0 }
76 static const CGEN_IFMT ifmt_ldi32
= {
77 16, 48, 0xfff0, { F (F_OP1
), F (F_I32
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
80 static const CGEN_IFMT ifmt_ldr14
= {
81 16, 16, 0xf000, { F (F_OP1
), F (F_DISP10
), F (F_RI
), 0 }
84 static const CGEN_IFMT ifmt_ldr14uh
= {
85 16, 16, 0xf000, { F (F_OP1
), F (F_DISP9
), F (F_RI
), 0 }
88 static const CGEN_IFMT ifmt_ldr14ub
= {
89 16, 16, 0xf000, { F (F_OP1
), F (F_DISP8
), F (F_RI
), 0 }
92 static const CGEN_IFMT ifmt_ldr15
= {
93 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_UDISP6
), F (F_RI
), 0 }
96 static const CGEN_IFMT ifmt_ldr15dr
= {
97 16, 16, 0xfff0, { F (F_OP1
), F (F_OP2
), F (F_OP3
), F (F_RS2
), 0 }
100 static const CGEN_IFMT ifmt_movdr
= {
101 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_RS1
), F (F_RI
), 0 }
104 static const CGEN_IFMT ifmt_call
= {
105 16, 16, 0xf800, { F (F_OP1
), F (F_OP5
), F (F_REL12
), 0 }
108 static const CGEN_IFMT ifmt_int
= {
109 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U8
), 0 }
112 static const CGEN_IFMT ifmt_brad
= {
113 16, 16, 0xff00, { F (F_OP1
), F (F_CC
), F (F_REL9
), 0 }
116 static const CGEN_IFMT ifmt_dmovr13
= {
117 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR10
), 0 }
120 static const CGEN_IFMT ifmt_dmovr13h
= {
121 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR9
), 0 }
124 static const CGEN_IFMT ifmt_dmovr13b
= {
125 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_DIR8
), 0 }
128 static const CGEN_IFMT ifmt_copop
= {
129 16, 32, 0xfff0, { F (F_OP1
), F (F_CCC
), F (F_OP2
), F (F_OP3
), F (F_CRJ
), F (F_U4C
), F (F_CRI
), 0 }
132 static const CGEN_IFMT ifmt_copld
= {
133 16, 32, 0xfff0, { F (F_OP1
), F (F_CCC
), F (F_OP2
), F (F_OP3
), F (F_RJC
), F (F_U4C
), F (F_CRI
), 0 }
136 static const CGEN_IFMT ifmt_copst
= {
137 16, 32, 0xfff0, { F (F_OP1
), F (F_CCC
), F (F_OP2
), F (F_OP3
), F (F_CRJ
), F (F_U4C
), F (F_RIC
), 0 }
140 static const CGEN_IFMT ifmt_addsp
= {
141 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_S10
), 0 }
144 static const CGEN_IFMT ifmt_ldm0
= {
145 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_LOW_LD
), 0 }
148 static const CGEN_IFMT ifmt_ldm1
= {
149 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_HI_LD
), 0 }
152 static const CGEN_IFMT ifmt_stm0
= {
153 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_LOW_ST
), 0 }
156 static const CGEN_IFMT ifmt_stm1
= {
157 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_REGLIST_HI_ST
), 0 }
160 static const CGEN_IFMT ifmt_enter
= {
161 16, 16, 0xff00, { F (F_OP1
), F (F_OP2
), F (F_U10
), 0 }
166 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
167 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
168 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
169 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
171 /* The instruction table. */
173 static const CGEN_OPCODE fr30_cgen_insn_opcode_table
[MAX_INSNS
] =
175 /* Special null first entry.
176 A `num' value of zero is thus invalid.
177 Also, the special `invalid' insn resides here. */
182 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
183 & ifmt_add
, { 0xa600 }
188 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
189 & ifmt_addi
, { 0xa400 }
194 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
195 & ifmt_add2
, { 0xa500 }
200 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
201 & ifmt_add
, { 0xa700 }
206 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
207 & ifmt_add
, { 0xa200 }
212 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
213 & ifmt_addi
, { 0xa000 }
218 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
219 & ifmt_add2
, { 0xa100 }
224 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
225 & ifmt_add
, { 0xac00 }
230 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
231 & ifmt_add
, { 0xad00 }
236 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
237 & ifmt_add
, { 0xae00 }
242 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
243 & ifmt_add
, { 0xaa00 }
248 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
249 & ifmt_addi
, { 0xa800 }
254 { { MNEM
, ' ', OP (M4
), ',', OP (RI
), 0 } },
255 & ifmt_add2
, { 0xa900 }
260 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
261 & ifmt_add
, { 0x8200 }
266 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
267 & ifmt_add
, { 0x9200 }
272 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
273 & ifmt_add
, { 0x9a00 }
278 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
279 & ifmt_add
, { 0x8400 }
284 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
285 & ifmt_add
, { 0x8500 }
290 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
291 & ifmt_add
, { 0x8600 }
296 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
297 & ifmt_add
, { 0x9400 }
302 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
303 & ifmt_add
, { 0x9500 }
308 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
309 & ifmt_add
, { 0x9600 }
314 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
315 & ifmt_add
, { 0x9c00 }
320 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
321 & ifmt_add
, { 0x9d00 }
326 { { MNEM
, ' ', OP (RJ
), ',', '@', OP (RI
), 0 } },
327 & ifmt_add
, { 0x9e00 }
332 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
333 & ifmt_addi
, { 0x8000 }
338 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
339 & ifmt_addi
, { 0x9000 }
344 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
345 & ifmt_addi
, { 0x9800 }
350 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
351 & ifmt_addi
, { 0x8100 }
356 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
357 & ifmt_addi
, { 0x9100 }
362 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
363 & ifmt_addi
, { 0x9900 }
368 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
369 & ifmt_addi
, { 0x8800 }
374 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), 0 } },
375 & ifmt_addi
, { 0x8900 }
380 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
381 & ifmt_add
, { 0xaf00 }
386 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
387 & ifmt_add
, { 0xab00 }
392 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
393 & ifmt_add
, { 0xbf00 }
398 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
399 & ifmt_add
, { 0xbb00 }
404 { { MNEM
, ' ', OP (RI
), 0 } },
405 & ifmt_div0s
, { 0x9740 }
410 { { MNEM
, ' ', OP (RI
), 0 } },
411 & ifmt_div0s
, { 0x9750 }
416 { { MNEM
, ' ', OP (RI
), 0 } },
417 & ifmt_div0s
, { 0x9760 }
422 { { MNEM
, ' ', OP (RI
), 0 } },
423 & ifmt_div0s
, { 0x9770 }
429 & ifmt_div3
, { 0x9f60 }
435 & ifmt_div3
, { 0x9f70 }
440 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
441 & ifmt_add
, { 0xb600 }
446 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
447 & ifmt_addi
, { 0xb400 }
452 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
453 & ifmt_addi
, { 0xb500 }
458 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
459 & ifmt_add
, { 0xb200 }
464 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
465 & ifmt_addi
, { 0xb000 }
470 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
471 & ifmt_addi
, { 0xb100 }
476 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
477 & ifmt_add
, { 0xba00 }
482 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
483 & ifmt_addi
, { 0xb800 }
488 { { MNEM
, ' ', OP (U4
), ',', OP (RI
), 0 } },
489 & ifmt_addi
, { 0xb900 }
494 { { MNEM
, ' ', OP (I8
), ',', OP (RI
), 0 } },
495 & ifmt_ldi8
, { 0xc000 }
497 /* ldi:20 $i20,$Ri */
500 { { MNEM
, ' ', OP (I20
), ',', OP (RI
), 0 } },
501 & ifmt_ldi20
, { 0x9b00 }
503 /* ldi:32 $i32,$Ri */
506 { { MNEM
, ' ', OP (I32
), ',', OP (RI
), 0 } },
507 & ifmt_ldi32
, { 0x9f80 }
512 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
513 & ifmt_add
, { 0x400 }
518 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
519 & ifmt_add
, { 0x500 }
524 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
525 & ifmt_add
, { 0x600 }
527 /* ld @($R13,$Rj),$Ri */
530 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
533 /* lduh @($R13,$Rj),$Ri */
536 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
537 & ifmt_add
, { 0x100 }
539 /* ldub @($R13,$Rj),$Ri */
542 { { MNEM
, ' ', '@', '(', OP (R13
), ',', OP (RJ
), ')', ',', OP (RI
), 0 } },
543 & ifmt_add
, { 0x200 }
545 /* ld @($R14,$disp10),$Ri */
548 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP10
), ')', ',', OP (RI
), 0 } },
549 & ifmt_ldr14
, { 0x2000 }
551 /* lduh @($R14,$disp9),$Ri */
554 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP9
), ')', ',', OP (RI
), 0 } },
555 & ifmt_ldr14uh
, { 0x4000 }
557 /* ldub @($R14,$disp8),$Ri */
560 { { MNEM
, ' ', '@', '(', OP (R14
), ',', OP (DISP8
), ')', ',', OP (RI
), 0 } },
561 & ifmt_ldr14ub
, { 0x6000 }
563 /* ld @($R15,$udisp6),$Ri */
566 { { MNEM
, ' ', '@', '(', OP (R15
), ',', OP (UDISP6
), ')', ',', OP (RI
), 0 } },
567 & ifmt_ldr15
, { 0x300 }
572 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (RI
), 0 } },
573 & ifmt_div0s
, { 0x700 }
578 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (RS2
), 0 } },
579 & ifmt_ldr15dr
, { 0x780 }
584 { { MNEM
, ' ', '@', OP (R15
), '+', ',', OP (PS
), 0 } },
585 & ifmt_div3
, { 0x790 }
590 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
591 & ifmt_add
, { 0x1400 }
596 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
597 & ifmt_add
, { 0x1500 }
602 { { MNEM
, ' ', OP (RI
), ',', '@', OP (RJ
), 0 } },
603 & ifmt_add
, { 0x1600 }
605 /* st $Ri,@($R13,$Rj) */
608 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
609 & ifmt_add
, { 0x1000 }
611 /* sth $Ri,@($R13,$Rj) */
614 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
615 & ifmt_add
, { 0x1100 }
617 /* stb $Ri,@($R13,$Rj) */
620 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R13
), ',', OP (RJ
), ')', 0 } },
621 & ifmt_add
, { 0x1200 }
623 /* st $Ri,@($R14,$disp10) */
626 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP10
), ')', 0 } },
627 & ifmt_ldr14
, { 0x3000 }
629 /* sth $Ri,@($R14,$disp9) */
632 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP9
), ')', 0 } },
633 & ifmt_ldr14uh
, { 0x5000 }
635 /* stb $Ri,@($R14,$disp8) */
638 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R14
), ',', OP (DISP8
), ')', 0 } },
639 & ifmt_ldr14ub
, { 0x7000 }
641 /* st $Ri,@($R15,$udisp6) */
644 { { MNEM
, ' ', OP (RI
), ',', '@', '(', OP (R15
), ',', OP (UDISP6
), ')', 0 } },
645 & ifmt_ldr15
, { 0x1300 }
650 { { MNEM
, ' ', OP (RI
), ',', '@', '-', OP (R15
), 0 } },
651 & ifmt_div0s
, { 0x1700 }
656 { { MNEM
, ' ', OP (RS2
), ',', '@', '-', OP (R15
), 0 } },
657 & ifmt_ldr15dr
, { 0x1780 }
662 { { MNEM
, ' ', OP (PS
), ',', '@', '-', OP (R15
), 0 } },
663 & ifmt_div3
, { 0x1790 }
668 { { MNEM
, ' ', OP (RJ
), ',', OP (RI
), 0 } },
669 & ifmt_add
, { 0x8b00 }
674 { { MNEM
, ' ', OP (RS1
), ',', OP (RI
), 0 } },
675 & ifmt_movdr
, { 0xb700 }
680 { { MNEM
, ' ', OP (PS
), ',', OP (RI
), 0 } },
681 & ifmt_div0s
, { 0x1710 }
686 { { MNEM
, ' ', OP (RI
), ',', OP (RS1
), 0 } },
687 & ifmt_movdr
, { 0xb300 }
692 { { MNEM
, ' ', OP (RI
), ',', OP (PS
), 0 } },
693 & ifmt_div0s
, { 0x710 }
698 { { MNEM
, ' ', '@', OP (RI
), 0 } },
699 & ifmt_div0s
, { 0x9700 }
704 { { MNEM
, ' ', '@', OP (RI
), 0 } },
705 & ifmt_div0s
, { 0x9f00 }
710 { { MNEM
, ' ', '@', OP (RI
), 0 } },
711 & ifmt_div0s
, { 0x9710 }
716 { { MNEM
, ' ', '@', OP (RI
), 0 } },
717 & ifmt_div0s
, { 0x9f10 }
722 { { MNEM
, ' ', OP (LABEL12
), 0 } },
723 & ifmt_call
, { 0xd000 }
725 /* call:d $label12 */
728 { { MNEM
, ' ', OP (LABEL12
), 0 } },
729 & ifmt_call
, { 0xd800 }
735 & ifmt_div3
, { 0x9720 }
741 & ifmt_div3
, { 0x9f20 }
746 { { MNEM
, ' ', OP (U8
), 0 } },
747 & ifmt_int
, { 0x1f00 }
753 & ifmt_div3
, { 0x9f30 }
759 & ifmt_div3
, { 0x9730 }
764 { { MNEM
, ' ', OP (LABEL9
), 0 } },
765 & ifmt_brad
, { 0xf000 }
770 { { MNEM
, ' ', OP (LABEL9
), 0 } },
771 & ifmt_brad
, { 0xe000 }
776 { { MNEM
, ' ', OP (LABEL9
), 0 } },
777 & ifmt_brad
, { 0xf100 }
782 { { MNEM
, ' ', OP (LABEL9
), 0 } },
783 & ifmt_brad
, { 0xe100 }
788 { { MNEM
, ' ', OP (LABEL9
), 0 } },
789 & ifmt_brad
, { 0xf200 }
794 { { MNEM
, ' ', OP (LABEL9
), 0 } },
795 & ifmt_brad
, { 0xe200 }
800 { { MNEM
, ' ', OP (LABEL9
), 0 } },
801 & ifmt_brad
, { 0xf300 }
806 { { MNEM
, ' ', OP (LABEL9
), 0 } },
807 & ifmt_brad
, { 0xe300 }
812 { { MNEM
, ' ', OP (LABEL9
), 0 } },
813 & ifmt_brad
, { 0xf400 }
818 { { MNEM
, ' ', OP (LABEL9
), 0 } },
819 & ifmt_brad
, { 0xe400 }
824 { { MNEM
, ' ', OP (LABEL9
), 0 } },
825 & ifmt_brad
, { 0xf500 }
830 { { MNEM
, ' ', OP (LABEL9
), 0 } },
831 & ifmt_brad
, { 0xe500 }
836 { { MNEM
, ' ', OP (LABEL9
), 0 } },
837 & ifmt_brad
, { 0xf600 }
842 { { MNEM
, ' ', OP (LABEL9
), 0 } },
843 & ifmt_brad
, { 0xe600 }
848 { { MNEM
, ' ', OP (LABEL9
), 0 } },
849 & ifmt_brad
, { 0xf700 }
854 { { MNEM
, ' ', OP (LABEL9
), 0 } },
855 & ifmt_brad
, { 0xe700 }
860 { { MNEM
, ' ', OP (LABEL9
), 0 } },
861 & ifmt_brad
, { 0xf800 }
866 { { MNEM
, ' ', OP (LABEL9
), 0 } },
867 & ifmt_brad
, { 0xe800 }
872 { { MNEM
, ' ', OP (LABEL9
), 0 } },
873 & ifmt_brad
, { 0xf900 }
878 { { MNEM
, ' ', OP (LABEL9
), 0 } },
879 & ifmt_brad
, { 0xe900 }
884 { { MNEM
, ' ', OP (LABEL9
), 0 } },
885 & ifmt_brad
, { 0xfa00 }
890 { { MNEM
, ' ', OP (LABEL9
), 0 } },
891 & ifmt_brad
, { 0xea00 }
896 { { MNEM
, ' ', OP (LABEL9
), 0 } },
897 & ifmt_brad
, { 0xfb00 }
902 { { MNEM
, ' ', OP (LABEL9
), 0 } },
903 & ifmt_brad
, { 0xeb00 }
908 { { MNEM
, ' ', OP (LABEL9
), 0 } },
909 & ifmt_brad
, { 0xfc00 }
914 { { MNEM
, ' ', OP (LABEL9
), 0 } },
915 & ifmt_brad
, { 0xec00 }
920 { { MNEM
, ' ', OP (LABEL9
), 0 } },
921 & ifmt_brad
, { 0xfd00 }
926 { { MNEM
, ' ', OP (LABEL9
), 0 } },
927 & ifmt_brad
, { 0xed00 }
932 { { MNEM
, ' ', OP (LABEL9
), 0 } },
933 & ifmt_brad
, { 0xfe00 }
938 { { MNEM
, ' ', OP (LABEL9
), 0 } },
939 & ifmt_brad
, { 0xee00 }
944 { { MNEM
, ' ', OP (LABEL9
), 0 } },
945 & ifmt_brad
, { 0xff00 }
950 { { MNEM
, ' ', OP (LABEL9
), 0 } },
951 & ifmt_brad
, { 0xef00 }
953 /* dmov $R13,@$dir10 */
956 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR10
), 0 } },
957 & ifmt_dmovr13
, { 0x1800 }
959 /* dmovh $R13,@$dir9 */
962 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR9
), 0 } },
963 & ifmt_dmovr13h
, { 0x1900 }
965 /* dmovb $R13,@$dir8 */
968 { { MNEM
, ' ', OP (R13
), ',', '@', OP (DIR8
), 0 } },
969 & ifmt_dmovr13b
, { 0x1a00 }
971 /* dmov @$R13+,@$dir10 */
974 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR10
), 0 } },
975 & ifmt_dmovr13
, { 0x1c00 }
977 /* dmovh @$R13+,@$dir9 */
980 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR9
), 0 } },
981 & ifmt_dmovr13h
, { 0x1d00 }
983 /* dmovb @$R13+,@$dir8 */
986 { { MNEM
, ' ', '@', OP (R13
), '+', ',', '@', OP (DIR8
), 0 } },
987 & ifmt_dmovr13b
, { 0x1e00 }
989 /* dmov @$R15+,@$dir10 */
992 { { MNEM
, ' ', '@', OP (R15
), '+', ',', '@', OP (DIR10
), 0 } },
993 & ifmt_dmovr13
, { 0x1b00 }
995 /* dmov @$dir10,$R13 */
998 { { MNEM
, ' ', '@', OP (DIR10
), ',', OP (R13
), 0 } },
999 & ifmt_dmovr13
, { 0x800 }
1001 /* dmovh @$dir9,$R13 */
1004 { { MNEM
, ' ', '@', OP (DIR9
), ',', OP (R13
), 0 } },
1005 & ifmt_dmovr13h
, { 0x900 }
1007 /* dmovb @$dir8,$R13 */
1010 { { MNEM
, ' ', '@', OP (DIR8
), ',', OP (R13
), 0 } },
1011 & ifmt_dmovr13b
, { 0xa00 }
1013 /* dmov @$dir10,@$R13+ */
1016 { { MNEM
, ' ', '@', OP (DIR10
), ',', '@', OP (R13
), '+', 0 } },
1017 & ifmt_dmovr13
, { 0xc00 }
1019 /* dmovh @$dir9,@$R13+ */
1022 { { MNEM
, ' ', '@', OP (DIR9
), ',', '@', OP (R13
), '+', 0 } },
1023 & ifmt_dmovr13h
, { 0xd00 }
1025 /* dmovb @$dir8,@$R13+ */
1028 { { MNEM
, ' ', '@', OP (DIR8
), ',', '@', OP (R13
), '+', 0 } },
1029 & ifmt_dmovr13b
, { 0xe00 }
1031 /* dmov @$dir10,@-$R15 */
1034 { { MNEM
, ' ', '@', OP (DIR10
), ',', '@', '-', OP (R15
), 0 } },
1035 & ifmt_dmovr13
, { 0xb00 }
1037 /* ldres @$Ri+,$u4 */
1040 { { MNEM
, ' ', '@', OP (RI
), '+', ',', OP (U4
), 0 } },
1041 & ifmt_addi
, { 0xbc00 }
1043 /* stres $u4,@$Ri+ */
1046 { { MNEM
, ' ', OP (U4
), ',', '@', OP (RI
), '+', 0 } },
1047 & ifmt_addi
, { 0xbd00 }
1049 /* copop $u4c,$ccc,$CRj,$CRi */
1052 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (CRI
), 0 } },
1053 & ifmt_copop
, { 0x9fc0 }
1055 /* copld $u4c,$ccc,$Rjc,$CRi */
1058 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (RJC
), ',', OP (CRI
), 0 } },
1059 & ifmt_copld
, { 0x9fd0 }
1061 /* copst $u4c,$ccc,$CRj,$Ric */
1064 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (RIC
), 0 } },
1065 & ifmt_copst
, { 0x9fe0 }
1067 /* copsv $u4c,$ccc,$CRj,$Ric */
1070 { { MNEM
, ' ', OP (U4C
), ',', OP (CCC
), ',', OP (CRJ
), ',', OP (RIC
), 0 } },
1071 & ifmt_copst
, { 0x9ff0 }
1077 & ifmt_div3
, { 0x9fa0 }
1082 { { MNEM
, ' ', OP (U8
), 0 } },
1083 & ifmt_int
, { 0x8300 }
1088 { { MNEM
, ' ', OP (U8
), 0 } },
1089 & ifmt_int
, { 0x9300 }
1094 { { MNEM
, ' ', OP (U8
), 0 } },
1095 & ifmt_int
, { 0x8700 }
1100 { { MNEM
, ' ', OP (S10
), 0 } },
1101 & ifmt_addsp
, { 0xa300 }
1106 { { MNEM
, ' ', OP (RI
), 0 } },
1107 & ifmt_div0s
, { 0x9780 }
1112 { { MNEM
, ' ', OP (RI
), 0 } },
1113 & ifmt_div0s
, { 0x9790 }
1118 { { MNEM
, ' ', OP (RI
), 0 } },
1119 & ifmt_div0s
, { 0x97a0 }
1124 { { MNEM
, ' ', OP (RI
), 0 } },
1125 & ifmt_div0s
, { 0x97b0 }
1127 /* ldm0 ($reglist_low_ld) */
1130 { { MNEM
, ' ', '(', OP (REGLIST_LOW_LD
), ')', 0 } },
1131 & ifmt_ldm0
, { 0x8c00 }
1133 /* ldm1 ($reglist_hi_ld) */
1136 { { MNEM
, ' ', '(', OP (REGLIST_HI_LD
), ')', 0 } },
1137 & ifmt_ldm1
, { 0x8d00 }
1139 /* stm0 ($reglist_low_st) */
1142 { { MNEM
, ' ', '(', OP (REGLIST_LOW_ST
), ')', 0 } },
1143 & ifmt_stm0
, { 0x8e00 }
1145 /* stm1 ($reglist_hi_st) */
1148 { { MNEM
, ' ', '(', OP (REGLIST_HI_ST
), ')', 0 } },
1149 & ifmt_stm1
, { 0x8f00 }
1154 { { MNEM
, ' ', OP (U10
), 0 } },
1155 & ifmt_enter
, { 0xf00 }
1161 & ifmt_div3
, { 0x9f90 }
1166 { { MNEM
, ' ', '@', OP (RJ
), ',', OP (RI
), 0 } },
1167 & ifmt_add
, { 0x8a00 }
1176 /* Formats for ALIAS macro-insns. */
1178 #define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
1180 static const CGEN_IFMT ifmt_ldi8m
= {
1181 16, 16, 0xf000, { F (F_OP1
), F (F_I8
), F (F_RI
), 0 }
1184 static const CGEN_IFMT ifmt_ldi20m
= {
1185 16, 32, 0xff00, { F (F_OP1
), F (F_I20
), F (F_OP2
), F (F_RI
), 0 }
1188 static const CGEN_IFMT ifmt_ldi32m
= {
1189 16, 48, 0xfff0, { F (F_OP1
), F (F_I32
), F (F_OP2
), F (F_OP3
), F (F_RI
), 0 }
1194 /* Each non-simple macro entry points to an array of expansion possibilities. */
1196 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
1197 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1198 #define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
1199 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1201 /* The macro instruction table. */
1203 static const CGEN_IBASE fr30_cgen_macro_insn_table
[] =
1207 -1, "ldi8m", "ldi8", 16,
1208 { 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
) } }
1210 /* ldi20 $i20,$Ri */
1212 -1, "ldi20m", "ldi20", 32,
1213 { 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
) } }
1215 /* ldi32 $i32,$Ri */
1217 -1, "ldi32m", "ldi32", 48,
1218 { 0|A(NO_DIS
)|A(ALIAS
), { (1<<MACH_BASE
) } }
1222 /* The macro instruction opcode table. */
1224 static const CGEN_OPCODE fr30_cgen_macro_insn_opcode_table
[] =
1229 { { MNEM
, ' ', OP (I8
), ',', OP (RI
), 0 } },
1230 & ifmt_ldi8m
, { 0xc000 }
1232 /* ldi20 $i20,$Ri */
1235 { { MNEM
, ' ', OP (I20
), ',', OP (RI
), 0 } },
1236 & ifmt_ldi20m
, { 0x9b00 }
1238 /* ldi32 $i32,$Ri */
1241 { { MNEM
, ' ', OP (I32
), ',', OP (RI
), 0 } },
1242 & ifmt_ldi32m
, { 0x9f80 }
1251 #ifndef CGEN_ASM_HASH_P
1252 #define CGEN_ASM_HASH_P(insn) 1
1255 #ifndef CGEN_DIS_HASH_P
1256 #define CGEN_DIS_HASH_P(insn) 1
1259 /* Return non-zero if INSN is to be added to the hash table.
1260 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1263 asm_hash_insn_p (insn
)
1264 const CGEN_INSN
*insn
;
1266 return CGEN_ASM_HASH_P (insn
);
1270 dis_hash_insn_p (insn
)
1271 const CGEN_INSN
*insn
;
1273 /* If building the hash table and the NO-DIS attribute is present,
1275 if (CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_NO_DIS
))
1277 return CGEN_DIS_HASH_P (insn
);
1280 #ifndef CGEN_ASM_HASH
1281 #define CGEN_ASM_HASH_SIZE 127
1282 #ifdef CGEN_MNEMONIC_OPERANDS
1283 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1285 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1289 /* It doesn't make much sense to provide a default here,
1290 but while this is under development we do.
1291 BUFFER is a pointer to the bytes of the insn, target order.
1292 VALUE is the first base_insn_bitsize bits as an int in host order. */
1294 #ifndef CGEN_DIS_HASH
1295 #define CGEN_DIS_HASH_SIZE 256
1296 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1299 /* The result is the hash value of the insn.
1300 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1303 asm_hash_insn (mnem
)
1306 return CGEN_ASM_HASH (mnem
);
1309 /* BUF is a pointer to the bytes of the insn, target order.
1310 VALUE is the first base_insn_bitsize bits as an int in host order. */
1313 dis_hash_insn (buf
, value
)
1315 CGEN_INSN_INT value
;
1317 return CGEN_DIS_HASH (buf
, value
);
1320 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1323 set_fields_bitsize (fields
, size
)
1324 CGEN_FIELDS
*fields
;
1327 CGEN_FIELDS_BITSIZE (fields
) = size
;
1330 /* Function to call before using the operand instance table.
1331 This plugs the opcode entries and macro instructions into the cpu table. */
1334 fr30_cgen_init_opcode_table (cd
)
1338 int num_macros
= (sizeof (fr30_cgen_macro_insn_table
) /
1339 sizeof (fr30_cgen_macro_insn_table
[0]));
1340 const CGEN_IBASE
*ib
= & fr30_cgen_macro_insn_table
[0];
1341 const CGEN_OPCODE
*oc
= & fr30_cgen_macro_insn_opcode_table
[0];
1342 CGEN_INSN
*insns
= (CGEN_INSN
*) xmalloc (num_macros
* sizeof (CGEN_INSN
));
1343 memset (insns
, 0, num_macros
* sizeof (CGEN_INSN
));
1344 for (i
= 0; i
< num_macros
; ++i
)
1346 insns
[i
].base
= &ib
[i
];
1347 insns
[i
].opcode
= &oc
[i
];
1349 cd
->macro_insn_table
.init_entries
= insns
;
1350 cd
->macro_insn_table
.entry_size
= sizeof (CGEN_IBASE
);
1351 cd
->macro_insn_table
.num_init_entries
= num_macros
;
1353 oc
= & fr30_cgen_insn_opcode_table
[0];
1354 insns
= (CGEN_INSN
*) cd
->insn_table
.init_entries
;
1355 for (i
= 0; i
< MAX_INSNS
; ++i
)
1356 insns
[i
].opcode
= &oc
[i
];
1358 cd
->sizeof_fields
= sizeof (CGEN_FIELDS
);
1359 cd
->set_fields_bitsize
= set_fields_bitsize
;
1361 cd
->asm_hash_p
= asm_hash_insn_p
;
1362 cd
->asm_hash
= asm_hash_insn
;
1363 cd
->asm_hash_size
= CGEN_ASM_HASH_SIZE
;
1365 cd
->dis_hash_p
= dis_hash_insn_p
;
1366 cd
->dis_hash
= dis_hash_insn
;
1367 cd
->dis_hash_size
= CGEN_DIS_HASH_SIZE
;