opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* SSE support required */
  54 #define CpuSSE          (CpuMMX + 1)
  55 /* SSE2 support required */
  56 #define CpuSSE2         (CpuSSE + 1)
  57 /* 3dnow! support required */
  58 #define Cpu3dnow        (CpuSSE2 + 1)
  59 /* 3dnow! Extensions support required */
  60 #define Cpu3dnowA       (Cpu3dnow + 1)
  61 /* SSE3 support required */
  62 #define CpuSSE3         (Cpu3dnowA + 1)
  63 /* VIA PadLock required */
  64 #define CpuPadLock      (CpuSSE3 + 1)
  65 /* AMD Secure Virtual Machine Ext-s required */
  66 #define CpuSVME         (CpuPadLock + 1)
  67 /* VMX Instructions required */
  68 #define CpuVMX          (CpuSVME + 1)
  69 /* SMX Instructions required */
  70 #define CpuSMX          (CpuVMX + 1)
  71 /* SSSE3 support required */
  72 #define CpuSSSE3        (CpuSMX + 1)
  73 /* SSE4a support required */
  74 #define CpuSSE4a        (CpuSSSE3 + 1)
  75 /* ABM New Instructions required */
  76 #define CpuABM          (CpuSSE4a + 1)
  77 /* SSE4.1 support required */
  78 #define CpuSSE4_1       (CpuABM + 1)
  79 /* SSE4.2 support required */
  80 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  81 /* SSE5 support required */
  82 #define CpuSSE5         (CpuSSE4_2 + 1)
  83 /* 64bit support available, used by -march= in assembler.  */
  84 #define CpuLM           (CpuSSE5 + 1)
  85 /* 64bit support required  */
  86 #define Cpu64           (CpuLM + 1)
  87 /* Not supported in the 64bit mode  */
  88 #define CpuNo64         (Cpu64 + 1)
  89 /* The last bitfield in i386_cpu_flags.  */
  90 #define CpuMax          CpuNo64
  91
  92 #define CpuNumOfUints \
  93   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
  94 #define CpuNumOfBits \
  95   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
  96
  97 /* If you get a compiler error for zero width of the unused field,
  98    comment it out.  */
  99 #define CpuUnused       (CpuMax + 1)
 100
 101 /* We can check if an instruction is available with array instead
 102    of bitfield. */
 103 typedef union i386_cpu_flags
 104 {
 105   struct
 106     {
 107       unsigned int cpui186:1;
 108       unsigned int cpui286:1;
 109       unsigned int cpui386:1;
 110       unsigned int cpui486:1;
 111       unsigned int cpui586:1;
 112       unsigned int cpui686:1;
 113       unsigned int cpup4:1;
 114       unsigned int cpuk6:1;
 115       unsigned int cpuk8:1;
 116       unsigned int cpummx:1;
 117       unsigned int cpusse:1;
 118       unsigned int cpusse2:1;
 119       unsigned int cpua3dnow:1;
 120       unsigned int cpua3dnowa:1;
 121       unsigned int cpusse3:1;
 122       unsigned int cpupadlock:1;
 123       unsigned int cpusvme:1;
 124       unsigned int cpuvmx:1;
 125       unsigned int cpusmx:1;
 126       unsigned int cpussse3:1;
 127       unsigned int cpusse4a:1;
 128       unsigned int cpuabm:1;
 129       unsigned int cpusse4_1:1;
 130       unsigned int cpusse4_2:1;
 131       unsigned int cpusse5:1;
 132       unsigned int cpulm:1;
 133       unsigned int cpu64:1;
 134       unsigned int cpuno64:1;
 135 #ifdef CpuUnused
 136       unsigned int unused:(CpuNumOfBits - CpuUnused);
 137 #endif
 138     } bitfield;
 139   unsigned int array[CpuNumOfUints];
 140 } i386_cpu_flags;
 141
 142 /* Position of opcode_modifier bits.  */
 143
 144 /* has direction bit. */
 145 #define D                       0
 146 /* set if operands can be words or dwords encoded the canonical way */
 147 #define W                       (D + 1)
 148 /* insn has a modrm byte. */
 149 #define Modrm                   (W + 1)
 150 /* register is in low 3 bits of opcode */
 151 #define ShortForm               (Modrm + 1)
 152 /* special case for jump insns.  */
 153 #define Jump                    (ShortForm + 1)
 154 /* call and jump */
 155 #define JumpDword               (Jump + 1)
 156 /* loop and jecxz */
 157 #define JumpByte                (JumpDword + 1)
 158 /* special case for intersegment leaps/calls */
 159 #define JumpInterSegment        (JumpByte + 1)
 160 /* FP insn memory format bit, sized by 0x4 */
 161 #define FloatMF                 (JumpInterSegment + 1)
 162 /* src/dest swap for floats. */
 163 #define FloatR                  (FloatMF + 1)
 164 /* has float insn direction bit. */
 165 #define FloatD                  (FloatR + 1)
 166 /* needs size prefix if in 32-bit mode */
 167 #define Size16                  (FloatD + 1)
 168 /* needs size prefix if in 16-bit mode */
 169 #define Size32                  (Size16 + 1)
 170 /* needs size prefix if in 64-bit mode */
 171 #define Size64                  (Size32 + 1)
 172 /* instruction ignores operand size prefix and in Intel mode ignores
 173    mnemonic size suffix check.  */
 174 #define IgnoreSize              (Size64 + 1)
 175 /* default insn size depends on mode */
 176 #define DefaultSize             (IgnoreSize + 1)
 177 /* b suffix on instruction illegal */
 178 #define No_bSuf                 (DefaultSize + 1)
 179 /* w suffix on instruction illegal */
 180 #define No_wSuf                 (No_bSuf + 1)
 181 /* l suffix on instruction illegal */
 182 #define No_lSuf                 (No_wSuf + 1)
 183 /* s suffix on instruction illegal */
 184 #define No_sSuf                 (No_lSuf + 1)
 185 /* q suffix on instruction illegal */
 186 #define No_qSuf                 (No_sSuf + 1)
 187 /* long double suffix on instruction illegal */
 188 #define No_ldSuf                (No_qSuf + 1)
 189 /* instruction needs FWAIT */
 190 #define FWait                   (No_ldSuf + 1)
 191 /* quick test for string instructions */
 192 #define IsString                (FWait + 1)
 193 /* fake an extra reg operand for clr, imul and special register
 194    processing for some instructions.  */
 195 #define RegKludge               (IsString + 1)
 196 /* The first operand must be xmm0 */
 197 #define FirstXmm0               (RegKludge + 1)
 198 /* BYTE is OK in Intel syntax. */
 199 #define ByteOkIntel             (FirstXmm0 + 1)
 200 /* Convert to DWORD */
 201 #define ToDword                 (ByteOkIntel + 1)
 202 /* Convert to QWORD */
 203 #define ToQword                 (ToDword + 1)
 204 /* Address prefix changes operand 0 */
 205 #define AddrPrefixOp0           (ToQword + 1)
 206 /* opcode is a prefix */
 207 #define IsPrefix                (AddrPrefixOp0 + 1)
 208 /* instruction has extension in 8 bit imm */
 209 #define ImmExt                  (IsPrefix + 1)
 210 /* instruction don't need Rex64 prefix.  */
 211 #define NoRex64                 (ImmExt + 1)
 212 /* instruction require Rex64 prefix.  */
 213 #define Rex64                   (NoRex64 + 1)
 214 /* deprecated fp insn, gets a warning */
 215 #define Ugh                     (Rex64 + 1)
 216 #define Drex                    (Ugh + 1)
 217 /* instruction needs DREX with multiple encodings for memory ops */
 218 #define Drexv                   (Drex + 1)
 219 /* special DREX for comparisons */
 220 #define Drexc                   (Drexv + 1)
 221 /* Compatible with old (<= 2.8.1) versions of gcc  */
 222 #define OldGcc                  (Drexc + 1)
 223 /* AT&T mnemonic.  */
 224 #define ATTMnemonic             (OldGcc + 1)
 225 /* AT&T syntax.  */
 226 #define ATTSyntax               (ATTMnemonic + 1)
 227 /* Intel syntax.  */
 228 #define IntelSyntax             (ATTSyntax + 1)
 229 /* The last bitfield in i386_opcode_modifier.  */
 230 #define Opcode_Modifier_Max     IntelSyntax
 231
 232 typedef struct i386_opcode_modifier
 233 {
 234   unsigned int d:1;
 235   unsigned int w:1;
 236   unsigned int modrm:1;
 237   unsigned int shortform:1;
 238   unsigned int jump:1;
 239   unsigned int jumpdword:1;
 240   unsigned int jumpbyte:1;
 241   unsigned int jumpintersegment:1;
 242   unsigned int floatmf:1;
 243   unsigned int floatr:1;
 244   unsigned int floatd:1;
 245   unsigned int size16:1;
 246   unsigned int size32:1;
 247   unsigned int size64:1;
 248   unsigned int ignoresize:1;
 249   unsigned int defaultsize:1;
 250   unsigned int no_bsuf:1;
 251   unsigned int no_wsuf:1;
 252   unsigned int no_lsuf:1;
 253   unsigned int no_ssuf:1;
 254   unsigned int no_qsuf:1;
 255   unsigned int no_ldsuf:1;
 256   unsigned int fwait:1;
 257   unsigned int isstring:1;
 258   unsigned int regkludge:1;
 259   unsigned int firstxmm0:1;
 260   unsigned int byteokintel:1;
 261   unsigned int todword:1;
 262   unsigned int toqword:1;
 263   unsigned int addrprefixop0:1;
 264   unsigned int isprefix:1;
 265   unsigned int immext:1;
 266   unsigned int norex64:1;
 267   unsigned int rex64:1;
 268   unsigned int ugh:1;
 269   unsigned int drex:1;
 270   unsigned int drexv:1;
 271   unsigned int drexc:1;
 272   unsigned int oldgcc:1;
 273   unsigned int attmnemonic:1;
 274   unsigned int attsyntax:1;
 275   unsigned int intelsyntax:1;
 276 } i386_opcode_modifier;
 277
 278 /* Position of operand_type bits.  */
 279
 280 /* 8bit register */
 281 #define Reg8                    0
 282 /* 16bit register */
 283 #define Reg16                   (Reg8 + 1)
 284 /* 32bit register */
 285 #define Reg32                   (Reg16 + 1)
 286 /* 64bit register */
 287 #define Reg64                   (Reg32 + 1)
 288 /* Floating pointer stack register */
 289 #define FloatReg                (Reg64 + 1)
 290 /* MMX register */
 291 #define RegMMX                  (FloatReg + 1)
 292 /* SSE register */
 293 #define RegXMM                  (RegMMX + 1)
 294 /* Control register */
 295 #define Control                 (RegXMM + 1)
 296 /* Debug register */
 297 #define Debug                   (Control + 1)
 298 /* Test register */
 299 #define Test                    (Debug + 1)
 300 /* 2 bit segment register */
 301 #define SReg2                   (Test + 1)
 302 /* 3 bit segment register */
 303 #define SReg3                   (SReg2 + 1)
 304 /* 1 bit immediate */
 305 #define Imm1                    (SReg3 + 1)
 306 /* 8 bit immediate */
 307 #define Imm8                    (Imm1 + 1)
 308 /* 8 bit immediate sign extended */
 309 #define Imm8S                   (Imm8 + 1)
 310 /* 16 bit immediate */
 311 #define Imm16                   (Imm8S + 1)
 312 /* 32 bit immediate */
 313 #define Imm32                   (Imm16 + 1)
 314 /* 32 bit immediate sign extended */
 315 #define Imm32S                  (Imm32 + 1)
 316 /* 64 bit immediate */
 317 #define Imm64                   (Imm32S + 1)
 318 /* 8bit/16bit/32bit displacements are used in different ways,
 319    depending on the instruction.  For jumps, they specify the
 320    size of the PC relative displacement, for instructions with
 321    memory operand, they specify the size of the offset relative
 322    to the base register, and for instructions with memory offset
 323    such as `mov 1234,%al' they specify the size of the offset
 324    relative to the segment base.  */
 325 /* 8 bit displacement */
 326 #define Disp8                   (Imm64 + 1)
 327 /* 16 bit displacement */
 328 #define Disp16                  (Disp8 + 1)
 329 /* 32 bit displacement */
 330 #define Disp32                  (Disp16 + 1)
 331 /* 32 bit signed displacement */
 332 #define Disp32S                 (Disp32 + 1)
 333 /* 64 bit displacement */
 334 #define Disp64                  (Disp32S + 1)
 335 /* Accumulator %al/%ax/%eax/%rax */
 336 #define Acc                     (Disp64 + 1)
 337 /* Floating pointer top stack register %st(0) */
 338 #define FloatAcc                (Acc + 1)
 339 /* Register which can be used for base or index in memory operand.  */
 340 #define BaseIndex               (FloatAcc + 1)
 341 /* Register to hold in/out port addr = dx */
 342 #define InOutPortReg            (BaseIndex + 1)
 343 /* Register to hold shift count = cl */
 344 #define ShiftCount              (InOutPortReg + 1)
 345 /* Absolute address for jump.  */
 346 #define JumpAbsolute            (ShiftCount + 1)
 347 /* String insn operand with fixed es segment */
 348 #define EsSeg                   (JumpAbsolute + 1)
 349 /* RegMem is for instructions with a modrm byte where the register
 350    destination operand should be encoded in the mod and regmem fields.
 351    Normally, it will be encoded in the reg field. We add a RegMem
 352    flag to the destination register operand to indicate that it should
 353    be encoded in the regmem field.  */
 354 #define RegMem                  (EsSeg + 1)
 355 /* Memory.  */
 356 #define Mem                     (RegMem + 1)
 357 /* BYTE memory. */
 358 #define Byte                    (Mem + 1)
 359 /* WORD memory. 2 byte */
 360 #define Word                    (Byte + 1)
 361 /* DWORD memory. 4 byte */
 362 #define Dword                   (Word + 1)
 363 /* FWORD memory. 6 byte */
 364 #define Fword                   (Dword + 1)
 365 /* QWORD memory. 8 byte */
 366 #define Qword                   (Fword + 1)
 367 /* TBYTE memory. 10 byte */
 368 #define Tbyte                   (Qword + 1)
 369 /* XMMWORD memory. */
 370 #define Xmmword                 (Tbyte + 1)
 371 /* Unspecified memory size.  */
 372 #define Unspecified             (Xmmword + 1)
 373 /* Any memory size.  */
 374 #define Anysize                 (Unspecified  + 1)
 375
 376 /* The last bitfield in i386_operand_type.  */
 377 #define OTMax                   Anysize
 378
 379 #define OTNumOfUints \
 380   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 381 #define OTNumOfBits \
 382   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 383
 384 /* If you get a compiler error for zero width of the unused field,
 385    comment it out.  */
 386 #define OTUnused                (OTMax + 1)
 387
 388 typedef union i386_operand_type
 389 {
 390   struct
 391     {
 392       unsigned int reg8:1;
 393       unsigned int reg16:1;
 394       unsigned int reg32:1;
 395       unsigned int reg64:1;
 396       unsigned int floatreg:1;
 397       unsigned int regmmx:1;
 398       unsigned int regxmm:1;
 399       unsigned int control:1;
 400       unsigned int debug:1;
 401       unsigned int test:1;
 402       unsigned int sreg2:1;
 403       unsigned int sreg3:1;
 404       unsigned int imm1:1;
 405       unsigned int imm8:1;
 406       unsigned int imm8s:1;
 407       unsigned int imm16:1;
 408       unsigned int imm32:1;
 409       unsigned int imm32s:1;
 410       unsigned int imm64:1;
 411       unsigned int disp8:1;
 412       unsigned int disp16:1;
 413       unsigned int disp32:1;
 414       unsigned int disp32s:1;
 415       unsigned int disp64:1;
 416       unsigned int acc:1;
 417       unsigned int floatacc:1;
 418       unsigned int baseindex:1;
 419       unsigned int inoutportreg:1;
 420       unsigned int shiftcount:1;
 421       unsigned int jumpabsolute:1;
 422       unsigned int esseg:1;
 423       unsigned int regmem:1;
 424       unsigned int mem:1;
 425       unsigned int byte:1;
 426       unsigned int word:1;
 427       unsigned int dword:1;
 428       unsigned int fword:1;
 429       unsigned int qword:1;
 430       unsigned int tbyte:1;
 431       unsigned int xmmword:1;
 432       unsigned int unspecified:1;
 433       unsigned int anysize:1;
 434 #ifdef OTUnused
 435       unsigned int unused:(OTNumOfBits - OTUnused);
 436 #endif
 437     } bitfield;
 438   unsigned int array[OTNumOfUints];
 439 } i386_operand_type;
 440
 441 typedef struct template
 442 {
 443   /* instruction name sans width suffix ("mov" for movl insns) */
 444   char *name;
 445
 446   /* how many operands */
 447   unsigned int operands;
 448
 449   /* base_opcode is the fundamental opcode byte without optional
 450      prefix(es).  */
 451   unsigned int base_opcode;
 452 #define Opcode_D        0x2 /* Direction bit:
 453                                set if Reg --> Regmem;
 454                                unset if Regmem --> Reg. */
 455 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 456 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 457
 458   /* extension_opcode is the 3 bit extension for group <n> insns.
 459      This field is also used to store the 8-bit opcode suffix for the
 460      AMD 3DNow! instructions.
 461      If this template has no extension opcode (the usual case) use None
 462      Instructions with Drex use this to specify 2 bits for OC */
 463   unsigned int extension_opcode;
 464 #define None 0xffff             /* If no extension_opcode is possible.  */
 465
 466   /* Opcode length.  */
 467   unsigned char opcode_length;
 468
 469   /* cpu feature flags */
 470   i386_cpu_flags cpu_flags;
 471
 472   /* the bits in opcode_modifier are used to generate the final opcode from
 473      the base_opcode.  These bits also are used to detect alternate forms of
 474      the same instruction */
 475   i386_opcode_modifier opcode_modifier;
 476
 477   /* operand_types[i] describes the type of operand i.  This is made
 478      by OR'ing together all of the possible type masks.  (e.g.
 479      'operand_types[i] = Reg|Imm' specifies that operand i can be
 480      either a register or an immediate operand.  */
 481   i386_operand_type operand_types[MAX_OPERANDS];
 482 }
 483 template;
 484
 485 extern const template i386_optab[];
 486
 487 /* these are for register name --> number & type hash lookup */
 488 typedef struct
 489 {
 490   char *reg_name;
 491   i386_operand_type reg_type;
 492   unsigned int reg_flags;
 493 #define RegRex      0x1  /* Extended register.  */
 494 #define RegRex64    0x2  /* Extended 8 bit register.  */
 495   unsigned int reg_num;
 496 #define RegRip  ((unsigned int ) ~0)
 497 #define RegEip  (RegRip - 1)
 498 /* EIZ and RIZ are fake index registers.  */
 499 #define RegEiz  (RegEip - 1)
 500 #define RegRiz  (RegEiz - 1)
 501 }
 502 reg_entry;
 503
 504 /* Entries in i386_regtab.  */
 505 #define REGNAM_AL 1
 506 #define REGNAM_AX 25
 507 #define REGNAM_EAX 41
 508
 509 extern const reg_entry i386_regtab[];
 510 extern const unsigned int i386_regtab_size;
 511
 512 typedef struct
 513 {
 514   char *seg_name;
 515   unsigned int seg_prefix;
 516 }
 517 seg_entry;
 518
 519 extern const seg_entry cs;
 520 extern const seg_entry ds;
 521 extern const seg_entry ss;
 522 extern const seg_entry es;
 523 extern const seg_entry fs;
 524 extern const seg_entry gs;