1 @c Copyright (C) 2002, 2003 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
6 @chapter SuperH SH64 Dependent Features
10 * SH64 Options:: Options
11 * SH64 Syntax:: Syntax
12 * SH64 Directives:: SH64 Machine Directives
13 * SH64 Opcodes:: Opcodes
23 @cindex SH64 ISA options
24 @cindex ISA options, SH64
26 Specify the sh4 or sh4a instruction set.
28 Enable sh-dsp insns, and disable sh3e / sh4 insns.
30 Enable sh2e, sh3e, sh4, and sh4a insn sets.
32 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
33 @item -isa=shmedia | -isa=shcompact
34 Specify the default instruction set. @code{SHmedia} specifies the
35 32-bit opcodes, and @code{SHcompact} specifies the 16-bit opcodes
36 compatible with previous SH families. The default depends on the ABI
37 selected; the default for the 64-bit ABI is SHmedia, and the default for
38 the 32-bit ABI is SHcompact. If neither the ABI nor the ISA is
39 specified, the default is 32-bit SHcompact.
41 Note that the @code{.mode} pseudo-op is not permitted if the ISA is not
42 specified on the command line.
44 @cindex SH64 ABI options
45 @cindex ABI options, SH64
46 @item -abi=32 | -abi=64
47 Specify the default ABI. If the ISA is specified and the ABI is not,
48 the default ABI depends on the ISA, with SHmedia defaulting to 64-bit
49 and SHcompact defaulting to 32-bit.
51 Note that the @code{.abi} pseudo-op is not permitted if the ABI is not
52 specified on the command line. When the ABI is specified on the command
53 line, any @code{.abi} pseudo-ops in the source must match it.
55 @item -shcompact-const-crange
56 Emit code-range descriptors for constants in SHcompact code sections.
59 Disallow SHmedia code in the same section as constants and SHcompact
63 Do not expand MOVI, PT, PTA or PTB instructions.
66 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
69 Support H'00 style hex constants in addition to 0x00 style.
77 * SH64-Chars:: Special Characters
78 * SH64-Regs:: Register Names
79 * SH64-Addressing:: Addressing Modes
83 @subsection Special Characters
85 @cindex line comment character, SH64
86 @cindex SH64 line comment character
87 @samp{!} is the line comment character.
89 @cindex line separator, SH64
90 @cindex statement separator, SH64
91 @cindex SH64 line separator
92 You can use @samp{;} instead of a newline to separate statements.
94 @cindex symbol names, @samp{$} in
95 @cindex @code{$} in symbol names
96 Since @samp{$} has no special meaning, you may use it in symbol names.
99 @subsection Register Names
101 @cindex SH64 registers
102 @cindex registers, SH64
103 You can use the predefined symbols @samp{r0} through @samp{r63} to refer
104 to the SH64 general registers, @samp{cr0} through @code{cr63} for
105 control registers, @samp{tr0} through @samp{tr7} for target address
106 registers, @samp{fr0} through @samp{fr63} for single-precision floating
107 point registers, @samp{dr0} through @samp{dr62} (even numbered registers
108 only) for double-precision floating point registers, @samp{fv0} through
109 @samp{fv60} (multiples of four only) for single-precision floating point
110 vectors, @samp{fp0} through @samp{fp62} (even numbered registers only)
111 for single-precision floating point pairs, @samp{mtrx0} through
112 @samp{mtrx48} (multiples of 16 only) for 4x4 matrices of
113 single-precision floating point registers, @samp{pc} for the program
114 counter, and @samp{fpscr} for the floating point status and control
117 You can also refer to the control registers by the mnemonics @samp{sr},
118 @samp{ssr}, @samp{pssr}, @samp{intevt}, @samp{expevt}, @samp{pexpevt},
119 @samp{tra}, @samp{spc}, @samp{pspc}, @samp{resvec}, @samp{vbr},
120 @samp{tea}, @samp{dcr}, @samp{kcr0}, @samp{kcr1}, @samp{ctc}, and
123 @node SH64-Addressing
124 @subsection Addressing Modes
126 @cindex addressing modes, SH64
127 @cindex SH64 addressing modes
129 SH64 operands consist of either a register or immediate value. The
130 immediate value can be a constant or label reference (or portion of a
131 label reference), as in this example:
136 movi (function >> 16) & 65535,r0
137 shori function & 65535, r0
141 @cindex datalabel, SH64
142 Instruction label references can reference labels in either SHmedia or
143 SHcompact. To differentiate between the two, labels in SHmedia sections
144 will always have the least significant bit set (i.e. they will be odd),
145 which SHcompact labels will have the least significant bit reset
146 (i.e. they will be even). If you need to reference the actual address
147 of a label, you can use the @code{datalabel} modifier, as in this
152 .long datalabel function
155 In that example, the first longword may or may not have the least
156 significant bit set depending on whether the label is an SHmedia label
157 or an SHcompact label. The second longword will be the actual address
158 of the label, regardless of what type of label it is.
160 @node SH64 Directives
161 @section SH64 Machine Directives
163 In addition to the SH directives, the SH64 provides the following
166 @cindex SH64 machine directives
167 @cindex machine directives, SH64
171 @item .mode [shmedia|shcompact]
172 @itemx .isa [shmedia|shcompact]
173 Specify the ISA for the following instructions (the two directives are
174 equivalent). Note that programs such as @code{objdump} rely on symbolic
175 labels to determine when such mode switches occur (by checking the least
176 significant bit of the label's address), so such mode/isa changes should
177 always be followed by a label (in practice, this is true anyway). Note
178 that you cannot use these directives if you didn't specify an ISA on the
182 Specify the ABI for the following instructions. Note that you cannot use
183 this directive unless you specified an ABI on the command line, and the
184 ABIs specified must match.
187 Like .uaword and .ualong, this allows you to specify an intentionally
188 unaligned quadword (64 bit word).
195 @cindex SH64 opcode summary
196 @cindex opcode summary, SH64
197 @cindex mnemonics, SH64
198 @cindex instruction summary, SH64
199 For detailed information on the SH64 machine instruction set, see
200 @cite{SuperH 64 bit RISC Series Architecture Manual} (SuperH, Inc.).
202 @code{@value{AS}} implements all the standard SH64 opcodes. In
203 addition, the following pseudo-opcodes may be expanded into one or more
209 If the value doesn't fit into a standard @code{movi} opcode,
210 @code{@value{AS}} will replace the @code{movi} with a sequence of
211 @code{movi} and @code{shori} opcodes.
214 This expands to a sequence of @code{movi} and @code{shori} opcode,
215 followed by a @code{ptrel} opcode, or to a @code{pta} or @code{ptb}
216 opcode, depending on the label referenced.