1 /* mmix-opc.c -- MMIX opcode table
2 Copyright (C) 2001, 2003 Free Software Foundation, Inc.
3 Written by Hans-Peter Nilsson (hp@bitrange.com)
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version 2,
10 or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "opcode/mmix.h"
25 /* Register-name-table for special registers. */
26 const struct mmix_spec_reg mmix_spec_regs
[] =
28 /* Keep rJ at top; it's the most frequently used one. */
64 /* Opcode-table. In order to cut down on redundant contents, we use helper
67 /* All bits in the opcode-byte are significant. Add "| ..." expressions
70 #define O(m) ((unsigned long) (m) << 24UL), ((~(unsigned long) (m) & 255) << 24)
72 /* Bits 7..1 of the opcode are significant. */
74 #define Z(m) ((unsigned long) (m) << 24), ((~(unsigned long) (m) & 254) << 24)
76 /* For easier overview of the table. */
77 #define N mmix_type_normal
78 #define B mmix_type_branch
79 #define C mmix_type_condbranch
80 #define MB mmix_type_memaccess_byte
81 #define MW mmix_type_memaccess_wyde
82 #define MT mmix_type_memaccess_tetra
83 #define MO mmix_type_memaccess_octa
84 #define M mmix_type_memaccess_block
85 #define J mmix_type_jsr
86 #define P mmix_type_pseudo
88 #define OP(y) XCONCAT2 (mmix_operands_,y)
90 /* Groups of instructions specified here must, if all are matching the
91 same instruction, be consecutive, in order more-specific to
92 less-specific match. */
94 const struct mmix_opcode mmix_opcodes
[] =
96 {"trap", O (0), OP (xyz_opt
), J
},
97 {"fcmp", O (1), OP (regs
), N
},
98 {"flot", Z (8), OP (roundregs_z
), N
},
100 {"fun", O (2), OP (regs
), N
},
101 {"feql", O (3), OP (regs
), N
},
102 {"flotu", Z (10), OP (roundregs_z
), N
},
104 {"fadd", O (4), OP (regs
), N
},
105 {"fix", O (5), OP (roundregs
), N
},
106 {"sflot", Z (12), OP (roundregs_z
), N
},
108 {"fsub", O (6), OP (regs
), N
},
109 {"fixu", O (7), OP (roundregs
), N
},
110 {"sflotu", Z (14), OP (roundregs_z
), N
},
112 {"fmul", O (16), OP (regs
), N
},
113 {"fcmpe", O (17), OP (regs
), N
},
114 {"mul", Z (24), OP (regs_z
), N
},
116 {"fune", O (18), OP (regs
), N
},
117 {"feqle", O (19), OP (regs
), N
},
118 {"mulu", Z (26), OP (regs_z
), N
},
120 {"fdiv", O (20), OP (regs
), N
},
121 {"fsqrt", O (21), OP (roundregs
), N
},
122 {"div", Z (28), OP (regs_z
), N
},
124 {"frem", O (22), OP (regs
), N
},
125 {"fint", O (23), OP (roundregs
), N
},
126 {"divu", Z (30), OP (regs_z
), N
},
128 {"add", Z (0x20), OP (regs_z
), N
},
129 {"2addu", Z (0x28), OP (regs_z
), N
},
131 {"addu", Z (0x22), OP (regs_z
), N
},
132 /* Synonym for ADDU. Put after ADDU, since we don't prefer it for
133 disassembly. It's supposed to be used for addresses, so we make it
134 a memory block reference for purposes of assembly. */
135 {"lda", Z (0x22), OP (regs_z_opt
), M
},
136 {"4addu", Z (0x2a), OP (regs_z
), N
},
138 {"sub", Z (0x24), OP (regs_z
), N
},
139 {"8addu", Z (0x2c), OP (regs_z
), N
},
141 {"subu", Z (0x26), OP (regs_z
), N
},
142 {"16addu", Z (0x2e), OP (regs_z
), N
},
144 {"cmp", Z (0x30), OP (regs_z
), N
},
145 {"sl", Z (0x38), OP (regs_z
), N
},
147 {"cmpu", Z (0x32), OP (regs_z
), N
},
148 {"slu", Z (0x3a), OP (regs_z
), N
},
150 {"neg", Z (0x34), OP (neg
), N
},
151 {"sr", Z (0x3c), OP (regs_z
), N
},
153 {"negu", Z (0x36), OP (neg
), N
},
154 {"sru", Z (0x3e), OP (regs_z
), N
},
156 {"bn", Z (0x40), OP (regaddr
), C
},
157 {"bnn", Z (0x48), OP (regaddr
), C
},
159 {"bz", Z (0x42), OP (regaddr
), C
},
160 {"bnz", Z (0x4a), OP (regaddr
), C
},
162 {"bp", Z (0x44), OP (regaddr
), C
},
163 {"bnp", Z (0x4c), OP (regaddr
), C
},
165 {"bod", Z (0x46), OP (regaddr
), C
},
166 {"bev", Z (0x4e), OP (regaddr
), C
},
168 {"pbn", Z (0x50), OP (regaddr
), C
},
169 {"pbnn", Z (0x58), OP (regaddr
), C
},
171 {"pbz", Z (0x52), OP (regaddr
), C
},
172 {"pbnz", Z (0x5a), OP (regaddr
), C
},
174 {"pbp", Z (0x54), OP (regaddr
), C
},
175 {"pbnp", Z (0x5c), OP (regaddr
), C
},
177 {"pbod", Z (0x56), OP (regaddr
), C
},
178 {"pbev", Z (0x5e), OP (regaddr
), C
},
180 {"csn", Z (0x60), OP (regs_z
), N
},
181 {"csnn", Z (0x68), OP (regs_z
), N
},
183 {"csz", Z (0x62), OP (regs_z
), N
},
184 {"csnz", Z (0x6a), OP (regs_z
), N
},
186 {"csp", Z (0x64), OP (regs_z
), N
},
187 {"csnp", Z (0x6c), OP (regs_z
), N
},
189 {"csod", Z (0x66), OP (regs_z
), N
},
190 {"csev", Z (0x6e), OP (regs_z
), N
},
192 {"zsn", Z (0x70), OP (regs_z
), N
},
193 {"zsnn", Z (0x78), OP (regs_z
), N
},
195 {"zsz", Z (0x72), OP (regs_z
), N
},
196 {"zsnz", Z (0x7a), OP (regs_z
), N
},
198 {"zsp", Z (0x74), OP (regs_z
), N
},
199 {"zsnp", Z (0x7c), OP (regs_z
), N
},
201 {"zsod", Z (0x76), OP (regs_z
), N
},
202 {"zsev", Z (0x7e), OP (regs_z
), N
},
204 {"ldb", Z (0x80), OP (regs_z_opt
), MB
},
205 {"ldt", Z (0x88), OP (regs_z_opt
), MT
},
207 {"ldbu", Z (0x82), OP (regs_z_opt
), MB
},
208 {"ldtu", Z (0x8a), OP (regs_z_opt
), MT
},
210 {"ldw", Z (0x84), OP (regs_z_opt
), MW
},
211 {"ldo", Z (0x8c), OP (regs_z_opt
), MO
},
213 {"ldwu", Z (0x86), OP (regs_z_opt
), MW
},
214 {"ldou", Z (0x8e), OP (regs_z_opt
), MO
},
216 {"ldsf", Z (0x90), OP (regs_z_opt
), MT
},
218 /* This doesn't seem to access memory, just the TLB. */
219 {"ldvts", Z (0x98), OP (regs_z_opt
), M
},
221 {"ldht", Z (0x92), OP (regs_z_opt
), MT
},
223 /* Neither does this per-se. */
224 {"preld", Z (0x9a), OP (x_regs_z
), N
},
226 {"cswap", Z (0x94), OP (regs_z_opt
), MO
},
227 {"prego", Z (0x9c), OP (x_regs_z
), N
},
229 {"ldunc", Z (0x96), OP (regs_z_opt
), MO
},
230 {"go", Z (GO_INSN_BYTE
),
233 {"stb", Z (0xa0), OP (regs_z_opt
), MB
},
234 {"stt", Z (0xa8), OP (regs_z_opt
), MT
},
236 {"stbu", Z (0xa2), OP (regs_z_opt
), MB
},
237 {"sttu", Z (0xaa), OP (regs_z_opt
), MT
},
239 {"stw", Z (0xa4), OP (regs_z_opt
), MW
},
240 {"sto", Z (0xac), OP (regs_z_opt
), MO
},
242 {"stwu", Z (0xa6), OP (regs_z_opt
), MW
},
243 {"stou", Z (0xae), OP (regs_z_opt
), MO
},
245 {"stsf", Z (0xb0), OP (regs_z_opt
), MT
},
246 {"syncd", Z (0xb8), OP (x_regs_z
), M
},
248 {"stht", Z (0xb2), OP (regs_z_opt
), MT
},
249 {"prest", Z (0xba), OP (x_regs_z
), M
},
251 {"stco", Z (0xb4), OP (x_regs_z
), MO
},
252 {"syncid", Z (0xbc), OP (x_regs_z
), M
},
254 {"stunc", Z (0xb6), OP (regs_z_opt
), MO
},
255 {"pushgo", Z (PUSHGO_INSN_BYTE
),
258 /* Synonym for OR with a zero Z. */
260 | 0xff, OP (set
), N
},
262 {"or", Z (0xc0), OP (regs_z
), N
},
263 {"and", Z (0xc8), OP (regs_z
), N
},
265 {"orn", Z (0xc2), OP (regs_z
), N
},
266 {"andn", Z (0xca), OP (regs_z
), N
},
268 {"nor", Z (0xc4), OP (regs_z
), N
},
269 {"nand", Z (0xcc), OP (regs_z
), N
},
271 {"xor", Z (0xc6), OP (regs_z
), N
},
272 {"nxor", Z (0xce), OP (regs_z
), N
},
274 {"bdif", Z (0xd0), OP (regs_z
), N
},
275 {"mux", Z (0xd8), OP (regs_z
), N
},
277 {"wdif", Z (0xd2), OP (regs_z
), N
},
278 {"sadd", Z (0xda), OP (regs_z
), N
},
280 {"tdif", Z (0xd4), OP (regs_z
), N
},
281 {"mor", Z (0xdc), OP (regs_z
), N
},
283 {"odif", Z (0xd6), OP (regs_z
), N
},
284 {"mxor", Z (0xde), OP (regs_z
), N
},
286 {"seth", O (0xe0), OP (reg_yz
), N
},
287 {"setmh", O (0xe1), OP (reg_yz
), N
},
288 {"orh", O (0xe8), OP (reg_yz
), N
},
289 {"ormh", O (0xe9), OP (reg_yz
), N
},
291 {"setml", O (0xe2), OP (reg_yz
), N
},
292 {"setl", O (SETL_INSN_BYTE
),
294 {"orml", O (0xea), OP (reg_yz
), N
},
295 {"orl", O (0xeb), OP (reg_yz
), N
},
297 {"inch", O (INCH_INSN_BYTE
),
299 {"incmh", O (INCMH_INSN_BYTE
),
301 {"andnh", O (0xec), OP (reg_yz
), N
},
302 {"andnmh", O (0xed), OP (reg_yz
), N
},
304 {"incml", O (INCML_INSN_BYTE
),
306 {"incl", O (0xe7), OP (reg_yz
), N
},
307 {"andnml", O (0xee), OP (reg_yz
), N
},
308 {"andnl", O (0xef), OP (reg_yz
), N
},
310 {"jmp", Z (0xf0), OP (jmp
), B
},
311 {"pop", O (0xf8), OP (pop
), B
},
313 | 0xffff00, OP (resume
), B
},
315 {"pushj", Z (0xf2), OP (pushj
), J
},
317 | 0xffff, OP (save
), M
},
319 | 0xffff00, OP (unsave
), M
},
321 {"geta", Z (0xf4), OP (regaddr
), N
},
322 {"sync", O (0xfc), OP (sync
), N
},
323 {"swym", O (SWYM_INSN_BYTE
),
326 {"put", Z (0xf6) | 0xff00, OP (put
), N
},
327 {"get", O (0xfe) | 0xffe0, OP (get
), N
},
328 {"trip", O (0xff), OP (xyz_opt
), J
},
330 /* We have mmixal pseudos in the ordinary instruction table so we can
331 avoid the "set" vs. ".set" ambiguity that would be the effect if we
332 had pseudos handled "normally" and defined NO_PSEUDO_DOT.
334 Note that IS and GREG are handled fully by md_start_line_hook, so
336 {"loc", ~0, ~0, OP (loc
), P
},
337 {"prefix", ~0, ~0, OP (prefix
), P
},
338 {"byte", ~0, ~0, OP (byte
), P
},
339 {"wyde", ~0, ~0, OP (wyde
), P
},
340 {"tetra", ~0, ~0, OP (tetra
), P
},
341 {"octa", ~0, ~0, OP (octa
), P
},
342 {"local", ~0, ~0, OP (local
), P
},
343 {"bspec", ~0, ~0, OP (bspec
), P
},
344 {"espec", ~0, ~0, OP (espec
), P
},
346 {NULL
, ~0, ~0, OP (none
), N
}
