1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu
.core
== arm_arch_none
.core
248 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
253 static int meabi_flags
= EABI_DEFAULT
;
255 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
258 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
263 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS
* GOT_symbol
;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode
= 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER
= 0x00,
286 IMPLICIT_IT_MODE_ARM
= 0x01,
287 IMPLICIT_IT_MODE_THUMB
= 0x02,
288 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
290 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax
= FALSE
;
330 enum neon_el_type type
;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN
/* The IT insn has been parsed. */
357 unsigned long instruction
;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype
;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type
;
379 enum it_instruction_type it_insn_type
;
385 struct neon_type_el vectype
;
386 unsigned present
: 1; /* Operand present. */
387 unsigned isreg
: 1; /* Operand was a register. */
388 unsigned immisreg
: 1; /* .imm field is a second register. */
389 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
399 unsigned writeback
: 1; /* Operand has trailing ! */
400 unsigned preind
: 1; /* Preindexed address. */
401 unsigned postind
: 1; /* Postindexed address. */
402 unsigned negative
: 1; /* Index register was negated. */
403 unsigned shifted
: 1; /* Shift applied to operation. */
404 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst
;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const
[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name
;
444 #define COND_ALWAYS 0xE
448 const char * template_name
;
452 struct asm_barrier_opt
454 const char * template_name
;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc
;
475 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
476 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
481 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined
;
492 struct neon_type_el eltype
;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin
;
533 struct neon_typed_alias
* neon
;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs
[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name
;
576 /* Parameters to instruction. */
577 unsigned int operands
[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag
: 4;
582 /* Basic instruction code. */
583 unsigned int avalue
: 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set
* avariant
;
590 const arm_feature_set
* tvariant
;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode
) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode
) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
728 static struct hash_control
* arm_ops_hsh
;
729 static struct hash_control
* arm_cond_hsh
;
730 static struct hash_control
* arm_shift_hsh
;
731 static struct hash_control
* arm_psr_hsh
;
732 static struct hash_control
* arm_v7m_psr_hsh
;
733 static struct hash_control
* arm_reg_hsh
;
734 static struct hash_control
* arm_reloc_hsh
;
735 static struct hash_control
* arm_barrier_opt_hsh
;
737 /* Stuff needed to resolve the label ambiguity
746 symbolS
* last_label_seen
;
747 static int label_is_thumb_function_name
= FALSE
;
749 /* Literal pool structure. Held on a per-section
750 and per-sub-section basis. */
752 #define MAX_LITERAL_POOL_SIZE 1024
753 typedef struct literal_pool
755 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
756 unsigned int next_free_entry
;
761 struct literal_pool
* next
;
764 /* Pointer to a linked list of literal pools. */
765 literal_pool
* list_of_pools
= NULL
;
768 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
770 static struct current_it now_it
;
774 now_it_compatible (int cond
)
776 return (cond
& ~1) == (now_it
.cc
& ~1);
780 conditional_insn (void)
782 return inst
.cond
!= COND_ALWAYS
;
785 static int in_it_block (void);
787 static int handle_it_state (void);
789 static void force_automatic_it_block_close (void);
791 static void it_fsm_post_encode (void);
793 #define set_it_insn_type(type) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_nonvoid(type, failret) \
805 inst.it_insn_type = type; \
806 if (handle_it_state () == FAIL) \
811 #define set_it_insn_type_last() \
814 if (inst.cond == COND_ALWAYS) \
815 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
817 set_it_insn_type (INSIDE_IT_LAST_INSN); \
823 /* This array holds the chars that always start a comment. If the
824 pre-processor is disabled, these aren't very useful. */
825 const char comment_chars
[] = "@";
827 /* This array holds the chars that only start a comment at the beginning of
828 a line. If the line seems to have the form '# 123 filename'
829 .line and .file directives will appear in the pre-processed output. */
830 /* Note that input_file.c hand checks for '#' at the beginning of the
831 first line of the input file. This is because the compiler outputs
832 #NO_APP at the beginning of its output. */
833 /* Also note that comments like this one will always work. */
834 const char line_comment_chars
[] = "#";
836 const char line_separator_chars
[] = ";";
838 /* Chars that can be used to separate mant
839 from exp in floating point numbers. */
840 const char EXP_CHARS
[] = "eE";
842 /* Chars that mean this number is a floating point constant. */
846 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
848 /* Prefix characters that indicate the start of an immediate
850 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
852 /* Separator character handling. */
854 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
857 skip_past_char (char ** str
, char c
)
868 #define skip_past_comma(str) skip_past_char (str, ',')
870 /* Arithmetic expressions (possibly involving symbols). */
872 /* Return TRUE if anything in the expression is a bignum. */
875 walk_no_bignums (symbolS
* sp
)
877 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
880 if (symbol_get_value_expression (sp
)->X_add_symbol
)
882 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
883 || (symbol_get_value_expression (sp
)->X_op_symbol
884 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
890 static int in_my_get_expression
= 0;
892 /* Third argument to my_get_expression. */
893 #define GE_NO_PREFIX 0
894 #define GE_IMM_PREFIX 1
895 #define GE_OPT_PREFIX 2
896 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
897 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
898 #define GE_OPT_PREFIX_BIG 3
901 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
906 /* In unified syntax, all prefixes are optional. */
908 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
913 case GE_NO_PREFIX
: break;
915 if (!is_immediate_prefix (**str
))
917 inst
.error
= _("immediate expression requires a # prefix");
923 case GE_OPT_PREFIX_BIG
:
924 if (is_immediate_prefix (**str
))
930 memset (ep
, 0, sizeof (expressionS
));
932 save_in
= input_line_pointer
;
933 input_line_pointer
= *str
;
934 in_my_get_expression
= 1;
935 seg
= expression (ep
);
936 in_my_get_expression
= 0;
938 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
940 /* We found a bad or missing expression in md_operand(). */
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
943 if (inst
.error
== NULL
)
944 inst
.error
= (ep
->X_op
== O_absent
945 ? _("missing expression") :_("bad expression"));
950 if (seg
!= absolute_section
951 && seg
!= text_section
952 && seg
!= data_section
953 && seg
!= bss_section
954 && seg
!= undefined_section
)
956 inst
.error
= _("bad segment");
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
965 /* Get rid of any bignums now, so that we don't generate an error for which
966 we can't establish a line number later on. Big numbers are never valid
967 in instructions, which is where this routine is always called. */
968 if (prefix_mode
!= GE_OPT_PREFIX_BIG
969 && (ep
->X_op
== O_big
971 && (walk_no_bignums (ep
->X_add_symbol
)
973 && walk_no_bignums (ep
->X_op_symbol
))))))
975 inst
.error
= _("invalid constant");
976 *str
= input_line_pointer
;
977 input_line_pointer
= save_in
;
981 *str
= input_line_pointer
;
982 input_line_pointer
= save_in
;
986 /* Turn a string in input_line_pointer into a floating point constant
987 of type TYPE, and store the appropriate bytes in *LITP. The number
988 of LITTLENUMS emitted is stored in *SIZEP. An error message is
989 returned, or NULL on OK.
991 Note that fp constants aren't represent in the normal way on the ARM.
992 In big endian mode, things are as expected. However, in little endian
993 mode fp constants are big-endian word-wise, and little-endian byte-wise
994 within the words. For example, (double) 1.1 in big endian mode is
995 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
996 the byte sequence 99 99 f1 3f 9a 99 99 99.
998 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1001 md_atof (int type
, char * litP
, int * sizeP
)
1004 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1036 return _("Unrecognized or unsupported floating point constant");
1039 t
= atof_ieee (input_line_pointer
, type
, words
);
1041 input_line_pointer
= t
;
1042 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1044 if (target_big_endian
)
1046 for (i
= 0; i
< prec
; i
++)
1048 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1049 litP
+= sizeof (LITTLENUM_TYPE
);
1054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1055 for (i
= prec
- 1; i
>= 0; i
--)
1057 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1058 litP
+= sizeof (LITTLENUM_TYPE
);
1061 /* For a 4 byte float the order of elements in `words' is 1 0.
1062 For an 8 byte float the order is 1 0 3 2. */
1063 for (i
= 0; i
< prec
; i
+= 2)
1065 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1066 sizeof (LITTLENUM_TYPE
));
1067 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1068 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1069 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1076 /* We handle all bad expressions here, so that we can report the faulty
1077 instruction in the error message. */
1079 md_operand (expressionS
* exp
)
1081 if (in_my_get_expression
)
1082 exp
->X_op
= O_illegal
;
1085 /* Immediate values. */
1087 /* Generic immediate-value read function for use in directives.
1088 Accepts anything that 'expression' can fold to a constant.
1089 *val receives the number. */
1092 immediate_for_directive (int *val
)
1095 exp
.X_op
= O_illegal
;
1097 if (is_immediate_prefix (*input_line_pointer
))
1099 input_line_pointer
++;
1103 if (exp
.X_op
!= O_constant
)
1105 as_bad (_("expected #constant"));
1106 ignore_rest_of_line ();
1109 *val
= exp
.X_add_number
;
1114 /* Register parsing. */
1116 /* Generic register parser. CCP points to what should be the
1117 beginning of a register name. If it is indeed a valid register
1118 name, advance CCP over it and return the reg_entry structure;
1119 otherwise return NULL. Does not issue diagnostics. */
1121 static struct reg_entry
*
1122 arm_reg_parse_multi (char **ccp
)
1126 struct reg_entry
*reg
;
1128 #ifdef REGISTER_PREFIX
1129 if (*start
!= REGISTER_PREFIX
)
1133 #ifdef OPTIONAL_REGISTER_PREFIX
1134 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1139 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1144 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1146 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1156 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1157 enum arm_reg_type type
)
1159 /* Alternative syntaxes are accepted for a few register classes. */
1166 /* Generic coprocessor register names are allowed for these. */
1167 if (reg
&& reg
->type
== REG_TYPE_CN
)
1172 /* For backward compatibility, a bare number is valid here. */
1174 unsigned long processor
= strtoul (start
, ccp
, 10);
1175 if (*ccp
!= start
&& processor
<= 15)
1179 case REG_TYPE_MMXWC
:
1180 /* WC includes WCG. ??? I'm not sure this is true for all
1181 instructions that take WC registers. */
1182 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1193 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1194 return value is the register number or FAIL. */
1197 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1200 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1203 /* Do not allow a scalar (reg+index) to parse as a register. */
1204 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1207 if (reg
&& reg
->type
== type
)
1210 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1217 /* Parse a Neon type specifier. *STR should point at the leading '.'
1218 character. Does no verification at this stage that the type fits the opcode
1225 Can all be legally parsed by this function.
1227 Fills in neon_type struct pointer with parsed information, and updates STR
1228 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1229 type, FAIL if not. */
1232 parse_neon_type (struct neon_type
*type
, char **str
)
1239 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1241 enum neon_el_type thistype
= NT_untyped
;
1242 unsigned thissize
= -1u;
1249 /* Just a size without an explicit type. */
1253 switch (TOLOWER (*ptr
))
1255 case 'i': thistype
= NT_integer
; break;
1256 case 'f': thistype
= NT_float
; break;
1257 case 'p': thistype
= NT_poly
; break;
1258 case 's': thistype
= NT_signed
; break;
1259 case 'u': thistype
= NT_unsigned
; break;
1261 thistype
= NT_float
;
1266 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1272 /* .f is an abbreviation for .f32. */
1273 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1278 thissize
= strtoul (ptr
, &ptr
, 10);
1280 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1283 as_bad (_("bad size %d in type specifier"), thissize
);
1291 type
->el
[type
->elems
].type
= thistype
;
1292 type
->el
[type
->elems
].size
= thissize
;
1297 /* Empty/missing type is not a successful parse. */
1298 if (type
->elems
== 0)
1306 /* Errors may be set multiple times during parsing or bit encoding
1307 (particularly in the Neon bits), but usually the earliest error which is set
1308 will be the most meaningful. Avoid overwriting it with later (cascading)
1309 errors by calling this function. */
1312 first_error (const char *err
)
1318 /* Parse a single type, e.g. ".s32", leading period included. */
1320 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1323 struct neon_type optype
;
1327 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1329 if (optype
.elems
== 1)
1330 *vectype
= optype
.el
[0];
1333 first_error (_("only one type should be specified for operand"));
1339 first_error (_("vector type expected"));
1351 /* Special meanings for indices (which have a range of 0-7), which will fit into
1354 #define NEON_ALL_LANES 15
1355 #define NEON_INTERLEAVE_LANES 14
1357 /* Parse either a register or a scalar, with an optional type. Return the
1358 register number, and optionally fill in the actual type of the register
1359 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1360 type/index information in *TYPEINFO. */
1363 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1364 enum arm_reg_type
*rtype
,
1365 struct neon_typed_alias
*typeinfo
)
1368 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1369 struct neon_typed_alias atype
;
1370 struct neon_type_el parsetype
;
1374 atype
.eltype
.type
= NT_invtype
;
1375 atype
.eltype
.size
= -1;
1377 /* Try alternate syntax for some types of register. Note these are mutually
1378 exclusive with the Neon syntax extensions. */
1381 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1389 /* Undo polymorphism when a set of register types may be accepted. */
1390 if ((type
== REG_TYPE_NDQ
1391 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1392 || (type
== REG_TYPE_VFSD
1393 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1394 || (type
== REG_TYPE_NSDQ
1395 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1396 || reg
->type
== REG_TYPE_NQ
))
1397 || (type
== REG_TYPE_MMXWC
1398 && (reg
->type
== REG_TYPE_MMXWCG
)))
1399 type
= (enum arm_reg_type
) reg
->type
;
1401 if (type
!= reg
->type
)
1407 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1409 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1411 first_error (_("can't redefine type for operand"));
1414 atype
.defined
|= NTA_HASTYPE
;
1415 atype
.eltype
= parsetype
;
1418 if (skip_past_char (&str
, '[') == SUCCESS
)
1420 if (type
!= REG_TYPE_VFD
)
1422 first_error (_("only D registers may be indexed"));
1426 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1428 first_error (_("can't change index for operand"));
1432 atype
.defined
|= NTA_HASINDEX
;
1434 if (skip_past_char (&str
, ']') == SUCCESS
)
1435 atype
.index
= NEON_ALL_LANES
;
1440 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1442 if (exp
.X_op
!= O_constant
)
1444 first_error (_("constant expression required"));
1448 if (skip_past_char (&str
, ']') == FAIL
)
1451 atype
.index
= exp
.X_add_number
;
1466 /* Like arm_reg_parse, but allow allow the following extra features:
1467 - If RTYPE is non-zero, return the (possibly restricted) type of the
1468 register (e.g. Neon double or quad reg when either has been requested).
1469 - If this is a Neon vector type with additional type information, fill
1470 in the struct pointed to by VECTYPE (if non-NULL).
1471 This function will fault on encountering a scalar. */
1474 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1475 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1477 struct neon_typed_alias atype
;
1479 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1484 /* Do not allow regname(... to parse as a register. */
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1491 first_error (_("register operand expected, but got scalar"));
1496 *vectype
= atype
.eltype
;
1503 #define NEON_SCALAR_REG(X) ((X) >> 4)
1504 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1506 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1507 have enough information to be able to do a good job bounds-checking. So, we
1508 just do easy checks here, and do further checks later. */
1511 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1515 struct neon_typed_alias atype
;
1517 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1519 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1522 if (atype
.index
== NEON_ALL_LANES
)
1524 first_error (_("scalar must have an index"));
1527 else if (atype
.index
>= 64 / elsize
)
1529 first_error (_("scalar index out of range"));
1534 *type
= atype
.eltype
;
1538 return reg
* 16 + atype
.index
;
1541 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1544 parse_reg_list (char ** strp
)
1546 char * str
= * strp
;
1550 /* We come back here if we get ranges concatenated by '+' or '|'. */
1565 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1567 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1577 first_error (_("bad range in register list"));
1581 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1583 if (range
& (1 << i
))
1585 (_("Warning: duplicated register (r%d) in register list"),
1593 if (range
& (1 << reg
))
1594 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1596 else if (reg
<= cur_reg
)
1597 as_tsktsk (_("Warning: register range not in ascending order"));
1602 while (skip_past_comma (&str
) != FAIL
1603 || (in_range
= 1, *str
++ == '-'));
1608 first_error (_("missing `}'"));
1616 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1619 if (exp
.X_op
== O_constant
)
1621 if (exp
.X_add_number
1622 != (exp
.X_add_number
& 0x0000ffff))
1624 inst
.error
= _("invalid register mask");
1628 if ((range
& exp
.X_add_number
) != 0)
1630 int regno
= range
& exp
.X_add_number
;
1633 regno
= (1 << regno
) - 1;
1635 (_("Warning: duplicated register (r%d) in register list"),
1639 range
|= exp
.X_add_number
;
1643 if (inst
.reloc
.type
!= 0)
1645 inst
.error
= _("expression too complex");
1649 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1650 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1651 inst
.reloc
.pc_rel
= 0;
1655 if (*str
== '|' || *str
== '+')
1661 while (another_range
);
1667 /* Types of registers in a list. */
1676 /* Parse a VFP register list. If the string is invalid return FAIL.
1677 Otherwise return the number of registers, and set PBASE to the first
1678 register. Parses registers of type ETYPE.
1679 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1680 - Q registers can be used to specify pairs of D registers
1681 - { } can be omitted from around a singleton register list
1682 FIXME: This is not implemented, as it would require backtracking in
1685 This could be done (the meaning isn't really ambiguous), but doesn't
1686 fit in well with the current parsing framework.
1687 - 32 D registers may be used (also true for VFPv3).
1688 FIXME: Types are ignored in these register lists, which is probably a
1692 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1697 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1701 unsigned long mask
= 0;
1706 inst
.error
= _("expecting {");
1715 regtype
= REG_TYPE_VFS
;
1720 regtype
= REG_TYPE_VFD
;
1723 case REGLIST_NEON_D
:
1724 regtype
= REG_TYPE_NDQ
;
1728 if (etype
!= REGLIST_VFP_S
)
1730 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1731 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1735 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1738 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1745 base_reg
= max_regs
;
1749 int setmask
= 1, addregs
= 1;
1751 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1753 if (new_base
== FAIL
)
1755 first_error (_(reg_expected_msgs
[regtype
]));
1759 if (new_base
>= max_regs
)
1761 first_error (_("register out of range in list"));
1765 /* Note: a value of 2 * n is returned for the register Q<n>. */
1766 if (regtype
== REG_TYPE_NQ
)
1772 if (new_base
< base_reg
)
1773 base_reg
= new_base
;
1775 if (mask
& (setmask
<< new_base
))
1777 first_error (_("invalid register list"));
1781 if ((mask
>> new_base
) != 0 && ! warned
)
1783 as_tsktsk (_("register list not in ascending order"));
1787 mask
|= setmask
<< new_base
;
1790 if (*str
== '-') /* We have the start of a range expression */
1796 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1799 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1803 if (high_range
>= max_regs
)
1805 first_error (_("register out of range in list"));
1809 if (regtype
== REG_TYPE_NQ
)
1810 high_range
= high_range
+ 1;
1812 if (high_range
<= new_base
)
1814 inst
.error
= _("register range not in ascending order");
1818 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1820 if (mask
& (setmask
<< new_base
))
1822 inst
.error
= _("invalid register list");
1826 mask
|= setmask
<< new_base
;
1831 while (skip_past_comma (&str
) != FAIL
);
1835 /* Sanity check -- should have raised a parse error above. */
1836 if (count
== 0 || count
> max_regs
)
1841 /* Final test -- the registers must be consecutive. */
1843 for (i
= 0; i
< count
; i
++)
1845 if ((mask
& (1u << i
)) == 0)
1847 inst
.error
= _("non-contiguous register range");
1857 /* True if two alias types are the same. */
1860 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1868 if (a
->defined
!= b
->defined
)
1871 if ((a
->defined
& NTA_HASTYPE
) != 0
1872 && (a
->eltype
.type
!= b
->eltype
.type
1873 || a
->eltype
.size
!= b
->eltype
.size
))
1876 if ((a
->defined
& NTA_HASINDEX
) != 0
1877 && (a
->index
!= b
->index
))
1883 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1884 The base register is put in *PBASE.
1885 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1887 The register stride (minus one) is put in bit 4 of the return value.
1888 Bits [6:5] encode the list length (minus one).
1889 The type of the list elements is put in *ELTYPE, if non-NULL. */
1891 #define NEON_LANE(X) ((X) & 0xf)
1892 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1893 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1896 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1897 struct neon_type_el
*eltype
)
1904 int leading_brace
= 0;
1905 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1906 const char *const incr_error
= _("register stride must be 1 or 2");
1907 const char *const type_error
= _("mismatched element/structure types in list");
1908 struct neon_typed_alias firsttype
;
1910 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1915 struct neon_typed_alias atype
;
1916 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1920 first_error (_(reg_expected_msgs
[rtype
]));
1927 if (rtype
== REG_TYPE_NQ
)
1933 else if (reg_incr
== -1)
1935 reg_incr
= getreg
- base_reg
;
1936 if (reg_incr
< 1 || reg_incr
> 2)
1938 first_error (_(incr_error
));
1942 else if (getreg
!= base_reg
+ reg_incr
* count
)
1944 first_error (_(incr_error
));
1948 if (! neon_alias_types_same (&atype
, &firsttype
))
1950 first_error (_(type_error
));
1954 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1958 struct neon_typed_alias htype
;
1959 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1961 lane
= NEON_INTERLEAVE_LANES
;
1962 else if (lane
!= NEON_INTERLEAVE_LANES
)
1964 first_error (_(type_error
));
1969 else if (reg_incr
!= 1)
1971 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1975 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1978 first_error (_(reg_expected_msgs
[rtype
]));
1981 if (! neon_alias_types_same (&htype
, &firsttype
))
1983 first_error (_(type_error
));
1986 count
+= hireg
+ dregs
- getreg
;
1990 /* If we're using Q registers, we can't use [] or [n] syntax. */
1991 if (rtype
== REG_TYPE_NQ
)
1997 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2001 else if (lane
!= atype
.index
)
2003 first_error (_(type_error
));
2007 else if (lane
== -1)
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2018 /* No lane set by [x]. We must be interleaving structures. */
2020 lane
= NEON_INTERLEAVE_LANES
;
2023 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2024 || (count
> 1 && reg_incr
== -1))
2026 first_error (_("error parsing element/structure list"));
2030 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2032 first_error (_("expected }"));
2040 *eltype
= firsttype
.eltype
;
2045 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2048 /* Parse an explicit relocation suffix on an expression. This is
2049 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2050 arm_reloc_hsh contains no entries, so this function can only
2051 succeed if there is no () after the word. Returns -1 on error,
2052 BFD_RELOC_UNUSED if there wasn't any suffix. */
2054 parse_reloc (char **str
)
2056 struct reloc_entry
*r
;
2060 return BFD_RELOC_UNUSED
;
2065 while (*q
&& *q
!= ')' && *q
!= ',')
2070 if ((r
= (struct reloc_entry
*)
2071 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2078 /* Directives: register aliases. */
2080 static struct reg_entry
*
2081 insert_reg_alias (char *str
, unsigned number
, int type
)
2083 struct reg_entry
*new_reg
;
2086 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2088 if (new_reg
->builtin
)
2089 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2091 /* Only warn about a redefinition if it's not defined as the
2093 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2094 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2099 name
= xstrdup (str
);
2100 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2102 new_reg
->name
= name
;
2103 new_reg
->number
= number
;
2104 new_reg
->type
= type
;
2105 new_reg
->builtin
= FALSE
;
2106 new_reg
->neon
= NULL
;
2108 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2115 insert_neon_reg_alias (char *str
, int number
, int type
,
2116 struct neon_typed_alias
*atype
)
2118 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2122 first_error (_("attempt to redefine typed alias"));
2128 reg
->neon
= (struct neon_typed_alias
*)
2129 xmalloc (sizeof (struct neon_typed_alias
));
2130 *reg
->neon
= *atype
;
2134 /* Look for the .req directive. This is of the form:
2136 new_register_name .req existing_register_name
2138 If we find one, or if it looks sufficiently like one that we want to
2139 handle any error here, return TRUE. Otherwise return FALSE. */
2142 create_register_alias (char * newname
, char *p
)
2144 struct reg_entry
*old
;
2145 char *oldname
, *nbuf
;
2148 /* The input scrubber ensures that whitespace after the mnemonic is
2149 collapsed to single spaces. */
2151 if (strncmp (oldname
, " .req ", 6) != 0)
2155 if (*oldname
== '\0')
2158 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2161 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2165 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2166 the desired alias name, and p points to its end. If not, then
2167 the desired alias name is in the global original_case_string. */
2168 #ifdef TC_CASE_SENSITIVE
2171 newname
= original_case_string
;
2172 nlen
= strlen (newname
);
2175 nbuf
= (char *) alloca (nlen
+ 1);
2176 memcpy (nbuf
, newname
, nlen
);
2179 /* Create aliases under the new name as stated; an all-lowercase
2180 version of the new name; and an all-uppercase version of the new
2182 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2184 for (p
= nbuf
; *p
; p
++)
2187 if (strncmp (nbuf
, newname
, nlen
))
2189 /* If this attempt to create an additional alias fails, do not bother
2190 trying to create the all-lower case alias. We will fail and issue
2191 a second, duplicate error message. This situation arises when the
2192 programmer does something like:
2195 The second .req creates the "Foo" alias but then fails to create
2196 the artificial FOO alias because it has already been created by the
2198 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2202 for (p
= nbuf
; *p
; p
++)
2205 if (strncmp (nbuf
, newname
, nlen
))
2206 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2212 /* Create a Neon typed/indexed register alias using directives, e.g.:
2217 These typed registers can be used instead of the types specified after the
2218 Neon mnemonic, so long as all operands given have types. Types can also be
2219 specified directly, e.g.:
2220 vadd d0.s32, d1.s32, d2.s32 */
2223 create_neon_reg_alias (char *newname
, char *p
)
2225 enum arm_reg_type basetype
;
2226 struct reg_entry
*basereg
;
2227 struct reg_entry mybasereg
;
2228 struct neon_type ntype
;
2229 struct neon_typed_alias typeinfo
;
2230 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2233 typeinfo
.defined
= 0;
2234 typeinfo
.eltype
.type
= NT_invtype
;
2235 typeinfo
.eltype
.size
= -1;
2236 typeinfo
.index
= -1;
2240 if (strncmp (p
, " .dn ", 5) == 0)
2241 basetype
= REG_TYPE_VFD
;
2242 else if (strncmp (p
, " .qn ", 5) == 0)
2243 basetype
= REG_TYPE_NQ
;
2252 basereg
= arm_reg_parse_multi (&p
);
2254 if (basereg
&& basereg
->type
!= basetype
)
2256 as_bad (_("bad type for register"));
2260 if (basereg
== NULL
)
2263 /* Try parsing as an integer. */
2264 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2265 if (exp
.X_op
!= O_constant
)
2267 as_bad (_("expression must be constant"));
2270 basereg
= &mybasereg
;
2271 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2277 typeinfo
= *basereg
->neon
;
2279 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2281 /* We got a type. */
2282 if (typeinfo
.defined
& NTA_HASTYPE
)
2284 as_bad (_("can't redefine the type of a register alias"));
2288 typeinfo
.defined
|= NTA_HASTYPE
;
2289 if (ntype
.elems
!= 1)
2291 as_bad (_("you must specify a single type only"));
2294 typeinfo
.eltype
= ntype
.el
[0];
2297 if (skip_past_char (&p
, '[') == SUCCESS
)
2300 /* We got a scalar index. */
2302 if (typeinfo
.defined
& NTA_HASINDEX
)
2304 as_bad (_("can't redefine the index of a scalar alias"));
2308 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2310 if (exp
.X_op
!= O_constant
)
2312 as_bad (_("scalar index must be constant"));
2316 typeinfo
.defined
|= NTA_HASINDEX
;
2317 typeinfo
.index
= exp
.X_add_number
;
2319 if (skip_past_char (&p
, ']') == FAIL
)
2321 as_bad (_("expecting ]"));
2326 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2327 the desired alias name, and p points to its end. If not, then
2328 the desired alias name is in the global original_case_string. */
2329 #ifdef TC_CASE_SENSITIVE
2330 namelen
= nameend
- newname
;
2332 newname
= original_case_string
;
2333 namelen
= strlen (newname
);
2336 namebuf
= (char *) alloca (namelen
+ 1);
2337 strncpy (namebuf
, newname
, namelen
);
2338 namebuf
[namelen
] = '\0';
2340 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2341 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2343 /* Insert name in all uppercase. */
2344 for (p
= namebuf
; *p
; p
++)
2347 if (strncmp (namebuf
, newname
, namelen
))
2348 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2349 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2351 /* Insert name in all lowercase. */
2352 for (p
= namebuf
; *p
; p
++)
2355 if (strncmp (namebuf
, newname
, namelen
))
2356 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2357 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2362 /* Should never be called, as .req goes between the alias and the
2363 register name, not at the beginning of the line. */
2366 s_req (int a ATTRIBUTE_UNUSED
)
2368 as_bad (_("invalid syntax for .req directive"));
2372 s_dn (int a ATTRIBUTE_UNUSED
)
2374 as_bad (_("invalid syntax for .dn directive"));
2378 s_qn (int a ATTRIBUTE_UNUSED
)
2380 as_bad (_("invalid syntax for .qn directive"));
2383 /* The .unreq directive deletes an alias which was previously defined
2384 by .req. For example:
2390 s_unreq (int a ATTRIBUTE_UNUSED
)
2395 name
= input_line_pointer
;
2397 while (*input_line_pointer
!= 0
2398 && *input_line_pointer
!= ' '
2399 && *input_line_pointer
!= '\n')
2400 ++input_line_pointer
;
2402 saved_char
= *input_line_pointer
;
2403 *input_line_pointer
= 0;
2406 as_bad (_("invalid syntax for .unreq directive"));
2409 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2413 as_bad (_("unknown register alias '%s'"), name
);
2414 else if (reg
->builtin
)
2415 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2422 hash_delete (arm_reg_hsh
, name
, FALSE
);
2423 free ((char *) reg
->name
);
2428 /* Also locate the all upper case and all lower case versions.
2429 Do not complain if we cannot find one or the other as it
2430 was probably deleted above. */
2432 nbuf
= strdup (name
);
2433 for (p
= nbuf
; *p
; p
++)
2435 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2438 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2439 free ((char *) reg
->name
);
2445 for (p
= nbuf
; *p
; p
++)
2447 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2450 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2451 free ((char *) reg
->name
);
2461 *input_line_pointer
= saved_char
;
2462 demand_empty_rest_of_line ();
2465 /* Directives: Instruction set selection. */
2468 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2469 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2470 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2471 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2473 /* Create a new mapping symbol for the transition to STATE. */
2476 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2479 const char * symname
;
2486 type
= BSF_NO_FLAGS
;
2490 type
= BSF_NO_FLAGS
;
2494 type
= BSF_NO_FLAGS
;
2500 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2501 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2506 THUMB_SET_FUNC (symbolP
, 0);
2507 ARM_SET_THUMB (symbolP
, 0);
2508 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2512 THUMB_SET_FUNC (symbolP
, 1);
2513 ARM_SET_THUMB (symbolP
, 1);
2514 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2522 /* Save the mapping symbols for future reference. Also check that
2523 we do not place two mapping symbols at the same offset within a
2524 frag. We'll handle overlap between frags in
2525 check_mapping_symbols.
2527 If .fill or other data filling directive generates zero sized data,
2528 the mapping symbol for the following code will have the same value
2529 as the one generated for the data filling directive. In this case,
2530 we replace the old symbol with the new one at the same address. */
2533 if (frag
->tc_frag_data
.first_map
!= NULL
)
2535 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2536 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2538 frag
->tc_frag_data
.first_map
= symbolP
;
2540 if (frag
->tc_frag_data
.last_map
!= NULL
)
2542 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2543 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2544 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2546 frag
->tc_frag_data
.last_map
= symbolP
;
2549 /* We must sometimes convert a region marked as code to data during
2550 code alignment, if an odd number of bytes have to be padded. The
2551 code mapping symbol is pushed to an aligned address. */
2554 insert_data_mapping_symbol (enum mstate state
,
2555 valueT value
, fragS
*frag
, offsetT bytes
)
2557 /* If there was already a mapping symbol, remove it. */
2558 if (frag
->tc_frag_data
.last_map
!= NULL
2559 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2561 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2565 know (frag
->tc_frag_data
.first_map
== symp
);
2566 frag
->tc_frag_data
.first_map
= NULL
;
2568 frag
->tc_frag_data
.last_map
= NULL
;
2569 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2572 make_mapping_symbol (MAP_DATA
, value
, frag
);
2573 make_mapping_symbol (state
, value
+ bytes
, frag
);
2576 static void mapping_state_2 (enum mstate state
, int max_chars
);
2578 /* Set the mapping state to STATE. Only call this when about to
2579 emit some STATE bytes to the file. */
2582 mapping_state (enum mstate state
)
2584 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2586 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2588 if (mapstate
== state
)
2589 /* The mapping symbol has already been emitted.
2590 There is nothing else to do. */
2592 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2593 /* This case will be evaluated later in the next else. */
2595 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2596 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2598 /* Only add the symbol if the offset is > 0:
2599 if we're at the first frag, check it's size > 0;
2600 if we're not at the first frag, then for sure
2601 the offset is > 0. */
2602 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2603 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2606 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2609 mapping_state_2 (state
, 0);
2613 /* Same as mapping_state, but MAX_CHARS bytes have already been
2614 allocated. Put the mapping symbol that far back. */
2617 mapping_state_2 (enum mstate state
, int max_chars
)
2619 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2621 if (!SEG_NORMAL (now_seg
))
2624 if (mapstate
== state
)
2625 /* The mapping symbol has already been emitted.
2626 There is nothing else to do. */
2629 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2630 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2633 #define mapping_state(x) ((void)0)
2634 #define mapping_state_2(x, y) ((void)0)
2637 /* Find the real, Thumb encoded start of a Thumb function. */
2641 find_real_start (symbolS
* symbolP
)
2644 const char * name
= S_GET_NAME (symbolP
);
2645 symbolS
* new_target
;
2647 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2648 #define STUB_NAME ".real_start_of"
2653 /* The compiler may generate BL instructions to local labels because
2654 it needs to perform a branch to a far away location. These labels
2655 do not have a corresponding ".real_start_of" label. We check
2656 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2657 the ".real_start_of" convention for nonlocal branches. */
2658 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2661 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2662 new_target
= symbol_find (real_start
);
2664 if (new_target
== NULL
)
2666 as_warn (_("Failed to find real start of function: %s\n"), name
);
2667 new_target
= symbolP
;
2675 opcode_select (int width
)
2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2683 as_bad (_("selected processor does not support THUMB opcodes"));
2686 /* No need to force the alignment, since we will have been
2687 coming from ARM mode, which is word-aligned. */
2688 record_alignment (now_seg
, 1);
2695 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2696 as_bad (_("selected processor does not support ARM opcodes"));
2701 frag_align (2, 0, 0);
2703 record_alignment (now_seg
, 1);
2708 as_bad (_("invalid instruction size selected (%d)"), width
);
2713 s_arm (int ignore ATTRIBUTE_UNUSED
)
2716 demand_empty_rest_of_line ();
2720 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2723 demand_empty_rest_of_line ();
2727 s_code (int unused ATTRIBUTE_UNUSED
)
2731 temp
= get_absolute_expression ();
2736 opcode_select (temp
);
2740 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2745 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2747 /* If we are not already in thumb mode go into it, EVEN if
2748 the target processor does not support thumb instructions.
2749 This is used by gcc/config/arm/lib1funcs.asm for example
2750 to compile interworking support functions even if the
2751 target processor should not support interworking. */
2755 record_alignment (now_seg
, 1);
2758 demand_empty_rest_of_line ();
2762 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2766 /* The following label is the name/address of the start of a Thumb function.
2767 We need to know this for the interworking support. */
2768 label_is_thumb_function_name
= TRUE
;
2771 /* Perform a .set directive, but also mark the alias as
2772 being a thumb function. */
2775 s_thumb_set (int equiv
)
2777 /* XXX the following is a duplicate of the code for s_set() in read.c
2778 We cannot just call that code as we need to get at the symbol that
2785 /* Especial apologies for the random logic:
2786 This just grew, and could be parsed much more simply!
2788 name
= input_line_pointer
;
2789 delim
= get_symbol_end ();
2790 end_name
= input_line_pointer
;
2793 if (*input_line_pointer
!= ',')
2796 as_bad (_("expected comma after name \"%s\""), name
);
2798 ignore_rest_of_line ();
2802 input_line_pointer
++;
2805 if (name
[0] == '.' && name
[1] == '\0')
2807 /* XXX - this should not happen to .thumb_set. */
2811 if ((symbolP
= symbol_find (name
)) == NULL
2812 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2815 /* When doing symbol listings, play games with dummy fragments living
2816 outside the normal fragment chain to record the file and line info
2818 if (listing
& LISTING_SYMBOLS
)
2820 extern struct list_info_struct
* listing_tail
;
2821 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2823 memset (dummy_frag
, 0, sizeof (fragS
));
2824 dummy_frag
->fr_type
= rs_fill
;
2825 dummy_frag
->line
= listing_tail
;
2826 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2827 dummy_frag
->fr_symbol
= symbolP
;
2831 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2834 /* "set" symbols are local unless otherwise specified. */
2835 SF_SET_LOCAL (symbolP
);
2836 #endif /* OBJ_COFF */
2837 } /* Make a new symbol. */
2839 symbol_table_insert (symbolP
);
2844 && S_IS_DEFINED (symbolP
)
2845 && S_GET_SEGMENT (symbolP
) != reg_section
)
2846 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2848 pseudo_set (symbolP
);
2850 demand_empty_rest_of_line ();
2852 /* XXX Now we come to the Thumb specific bit of code. */
2854 THUMB_SET_FUNC (symbolP
, 1);
2855 ARM_SET_THUMB (symbolP
, 1);
2856 #if defined OBJ_ELF || defined OBJ_COFF
2857 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2861 /* Directives: Mode selection. */
2863 /* .syntax [unified|divided] - choose the new unified syntax
2864 (same for Arm and Thumb encoding, modulo slight differences in what
2865 can be represented) or the old divergent syntax for each mode. */
2867 s_syntax (int unused ATTRIBUTE_UNUSED
)
2871 name
= input_line_pointer
;
2872 delim
= get_symbol_end ();
2874 if (!strcasecmp (name
, "unified"))
2875 unified_syntax
= TRUE
;
2876 else if (!strcasecmp (name
, "divided"))
2877 unified_syntax
= FALSE
;
2880 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2883 *input_line_pointer
= delim
;
2884 demand_empty_rest_of_line ();
2887 /* Directives: sectioning and alignment. */
2889 /* Same as s_align_ptwo but align 0 => align 2. */
2892 s_align (int unused ATTRIBUTE_UNUSED
)
2897 long max_alignment
= 15;
2899 temp
= get_absolute_expression ();
2900 if (temp
> max_alignment
)
2901 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2904 as_bad (_("alignment negative. 0 assumed."));
2908 if (*input_line_pointer
== ',')
2910 input_line_pointer
++;
2911 temp_fill
= get_absolute_expression ();
2923 /* Only make a frag if we HAVE to. */
2924 if (temp
&& !need_pass_2
)
2926 if (!fill_p
&& subseg_text_p (now_seg
))
2927 frag_align_code (temp
, 0);
2929 frag_align (temp
, (int) temp_fill
, 0);
2931 demand_empty_rest_of_line ();
2933 record_alignment (now_seg
, temp
);
2937 s_bss (int ignore ATTRIBUTE_UNUSED
)
2939 /* We don't support putting frags in the BSS segment, we fake it by
2940 marking in_bss, then looking at s_skip for clues. */
2941 subseg_set (bss_section
, 0);
2942 demand_empty_rest_of_line ();
2944 #ifdef md_elf_section_change_hook
2945 md_elf_section_change_hook ();
2950 s_even (int ignore ATTRIBUTE_UNUSED
)
2952 /* Never make frag if expect extra pass. */
2954 frag_align (1, 0, 0);
2956 record_alignment (now_seg
, 1);
2958 demand_empty_rest_of_line ();
2961 /* Directives: Literal pools. */
2963 static literal_pool
*
2964 find_literal_pool (void)
2966 literal_pool
* pool
;
2968 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2970 if (pool
->section
== now_seg
2971 && pool
->sub_section
== now_subseg
)
2978 static literal_pool
*
2979 find_or_make_literal_pool (void)
2981 /* Next literal pool ID number. */
2982 static unsigned int latest_pool_num
= 1;
2983 literal_pool
* pool
;
2985 pool
= find_literal_pool ();
2989 /* Create a new pool. */
2990 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2994 pool
->next_free_entry
= 0;
2995 pool
->section
= now_seg
;
2996 pool
->sub_section
= now_subseg
;
2997 pool
->next
= list_of_pools
;
2998 pool
->symbol
= NULL
;
3000 /* Add it to the list. */
3001 list_of_pools
= pool
;
3004 /* New pools, and emptied pools, will have a NULL symbol. */
3005 if (pool
->symbol
== NULL
)
3007 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3008 (valueT
) 0, &zero_address_frag
);
3009 pool
->id
= latest_pool_num
++;
3016 /* Add the literal in the global 'inst'
3017 structure to the relevant literal pool. */
3020 add_to_lit_pool (void)
3022 literal_pool
* pool
;
3025 pool
= find_or_make_literal_pool ();
3027 /* Check if this literal value is already in the pool. */
3028 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3030 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3031 && (inst
.reloc
.exp
.X_op
== O_constant
)
3032 && (pool
->literals
[entry
].X_add_number
3033 == inst
.reloc
.exp
.X_add_number
)
3034 && (pool
->literals
[entry
].X_unsigned
3035 == inst
.reloc
.exp
.X_unsigned
))
3038 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3039 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3040 && (pool
->literals
[entry
].X_add_number
3041 == inst
.reloc
.exp
.X_add_number
)
3042 && (pool
->literals
[entry
].X_add_symbol
3043 == inst
.reloc
.exp
.X_add_symbol
)
3044 && (pool
->literals
[entry
].X_op_symbol
3045 == inst
.reloc
.exp
.X_op_symbol
))
3049 /* Do we need to create a new entry? */
3050 if (entry
== pool
->next_free_entry
)
3052 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3054 inst
.error
= _("literal pool overflow");
3058 pool
->literals
[entry
] = inst
.reloc
.exp
;
3059 pool
->next_free_entry
+= 1;
3062 inst
.reloc
.exp
.X_op
= O_symbol
;
3063 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3064 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3069 /* Can't use symbol_new here, so have to create a symbol and then at
3070 a later date assign it a value. Thats what these functions do. */
3073 symbol_locate (symbolS
* symbolP
,
3074 const char * name
, /* It is copied, the caller can modify. */
3075 segT segment
, /* Segment identifier (SEG_<something>). */
3076 valueT valu
, /* Symbol value. */
3077 fragS
* frag
) /* Associated fragment. */
3079 unsigned int name_length
;
3080 char * preserved_copy_of_name
;
3082 name_length
= strlen (name
) + 1; /* +1 for \0. */
3083 obstack_grow (¬es
, name
, name_length
);
3084 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3086 #ifdef tc_canonicalize_symbol_name
3087 preserved_copy_of_name
=
3088 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3091 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3093 S_SET_SEGMENT (symbolP
, segment
);
3094 S_SET_VALUE (symbolP
, valu
);
3095 symbol_clear_list_pointers (symbolP
);
3097 symbol_set_frag (symbolP
, frag
);
3099 /* Link to end of symbol chain. */
3101 extern int symbol_table_frozen
;
3103 if (symbol_table_frozen
)
3107 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3109 obj_symbol_new_hook (symbolP
);
3111 #ifdef tc_symbol_new_hook
3112 tc_symbol_new_hook (symbolP
);
3116 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3117 #endif /* DEBUG_SYMS */
3122 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3125 literal_pool
* pool
;
3128 pool
= find_literal_pool ();
3130 || pool
->symbol
== NULL
3131 || pool
->next_free_entry
== 0)
3134 mapping_state (MAP_DATA
);
3136 /* Align pool as you have word accesses.
3137 Only make a frag if we have to. */
3139 frag_align (2, 0, 0);
3141 record_alignment (now_seg
, 2);
3143 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3145 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3146 (valueT
) frag_now_fix (), frag_now
);
3147 symbol_table_insert (pool
->symbol
);
3149 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3151 #if defined OBJ_COFF || defined OBJ_ELF
3152 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3155 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3156 /* First output the expression in the instruction to the pool. */
3157 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3159 /* Mark the pool as empty. */
3160 pool
->next_free_entry
= 0;
3161 pool
->symbol
= NULL
;
3165 /* Forward declarations for functions below, in the MD interface
3167 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3168 static valueT
create_unwind_entry (int);
3169 static void start_unwind_section (const segT
, int);
3170 static void add_unwind_opcode (valueT
, int);
3171 static void flush_pending_unwind (void);
3173 /* Directives: Data. */
3176 s_arm_elf_cons (int nbytes
)
3180 #ifdef md_flush_pending_output
3181 md_flush_pending_output ();
3184 if (is_it_end_of_statement ())
3186 demand_empty_rest_of_line ();
3190 #ifdef md_cons_align
3191 md_cons_align (nbytes
);
3194 mapping_state (MAP_DATA
);
3198 char *base
= input_line_pointer
;
3202 if (exp
.X_op
!= O_symbol
)
3203 emit_expr (&exp
, (unsigned int) nbytes
);
3206 char *before_reloc
= input_line_pointer
;
3207 reloc
= parse_reloc (&input_line_pointer
);
3210 as_bad (_("unrecognized relocation suffix"));
3211 ignore_rest_of_line ();
3214 else if (reloc
== BFD_RELOC_UNUSED
)
3215 emit_expr (&exp
, (unsigned int) nbytes
);
3218 reloc_howto_type
*howto
= (reloc_howto_type
*)
3219 bfd_reloc_type_lookup (stdoutput
,
3220 (bfd_reloc_code_real_type
) reloc
);
3221 int size
= bfd_get_reloc_size (howto
);
3223 if (reloc
== BFD_RELOC_ARM_PLT32
)
3225 as_bad (_("(plt) is only valid on branch targets"));
3226 reloc
= BFD_RELOC_UNUSED
;
3231 as_bad (_("%s relocations do not fit in %d bytes"),
3232 howto
->name
, nbytes
);
3235 /* We've parsed an expression stopping at O_symbol.
3236 But there may be more expression left now that we
3237 have parsed the relocation marker. Parse it again.
3238 XXX Surely there is a cleaner way to do this. */
3239 char *p
= input_line_pointer
;
3241 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3242 memcpy (save_buf
, base
, input_line_pointer
- base
);
3243 memmove (base
+ (input_line_pointer
- before_reloc
),
3244 base
, before_reloc
- base
);
3246 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3248 memcpy (base
, save_buf
, p
- base
);
3250 offset
= nbytes
- size
;
3251 p
= frag_more ((int) nbytes
);
3252 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3253 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3258 while (*input_line_pointer
++ == ',');
3260 /* Put terminator back into stream. */
3261 input_line_pointer
--;
3262 demand_empty_rest_of_line ();
3265 /* Emit an expression containing a 32-bit thumb instruction.
3266 Implementation based on put_thumb32_insn. */
3269 emit_thumb32_expr (expressionS
* exp
)
3271 expressionS exp_high
= *exp
;
3273 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3274 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3275 exp
->X_add_number
&= 0xffff;
3276 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3279 /* Guess the instruction size based on the opcode. */
3282 thumb_insn_size (int opcode
)
3284 if ((unsigned int) opcode
< 0xe800u
)
3286 else if ((unsigned int) opcode
>= 0xe8000000u
)
3293 emit_insn (expressionS
*exp
, int nbytes
)
3297 if (exp
->X_op
== O_constant
)
3302 size
= thumb_insn_size (exp
->X_add_number
);
3306 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3308 as_bad (_(".inst.n operand too big. "\
3309 "Use .inst.w instead"));
3314 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3315 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3317 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3319 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3320 emit_thumb32_expr (exp
);
3322 emit_expr (exp
, (unsigned int) size
);
3324 it_fsm_post_encode ();
3328 as_bad (_("cannot determine Thumb instruction size. " \
3329 "Use .inst.n/.inst.w instead"));
3332 as_bad (_("constant expression required"));
3337 /* Like s_arm_elf_cons but do not use md_cons_align and
3338 set the mapping state to MAP_ARM/MAP_THUMB. */
3341 s_arm_elf_inst (int nbytes
)
3343 if (is_it_end_of_statement ())
3345 demand_empty_rest_of_line ();
3349 /* Calling mapping_state () here will not change ARM/THUMB,
3350 but will ensure not to be in DATA state. */
3353 mapping_state (MAP_THUMB
);
3358 as_bad (_("width suffixes are invalid in ARM mode"));
3359 ignore_rest_of_line ();
3365 mapping_state (MAP_ARM
);
3374 if (! emit_insn (& exp
, nbytes
))
3376 ignore_rest_of_line ();
3380 while (*input_line_pointer
++ == ',');
3382 /* Put terminator back into stream. */
3383 input_line_pointer
--;
3384 demand_empty_rest_of_line ();
3387 /* Parse a .rel31 directive. */
3390 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3397 if (*input_line_pointer
== '1')
3398 highbit
= 0x80000000;
3399 else if (*input_line_pointer
!= '0')
3400 as_bad (_("expected 0 or 1"));
3402 input_line_pointer
++;
3403 if (*input_line_pointer
!= ',')
3404 as_bad (_("missing comma"));
3405 input_line_pointer
++;
3407 #ifdef md_flush_pending_output
3408 md_flush_pending_output ();
3411 #ifdef md_cons_align
3415 mapping_state (MAP_DATA
);
3420 md_number_to_chars (p
, highbit
, 4);
3421 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3422 BFD_RELOC_ARM_PREL31
);
3424 demand_empty_rest_of_line ();
3427 /* Directives: AEABI stack-unwind tables. */
3429 /* Parse an unwind_fnstart directive. Simply records the current location. */
3432 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3434 demand_empty_rest_of_line ();
3435 if (unwind
.proc_start
)
3437 as_bad (_("duplicate .fnstart directive"));
3441 /* Mark the start of the function. */
3442 unwind
.proc_start
= expr_build_dot ();
3444 /* Reset the rest of the unwind info. */
3445 unwind
.opcode_count
= 0;
3446 unwind
.table_entry
= NULL
;
3447 unwind
.personality_routine
= NULL
;
3448 unwind
.personality_index
= -1;
3449 unwind
.frame_size
= 0;
3450 unwind
.fp_offset
= 0;
3451 unwind
.fp_reg
= REG_SP
;
3453 unwind
.sp_restored
= 0;
3457 /* Parse a handlerdata directive. Creates the exception handling table entry
3458 for the function. */
3461 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3463 demand_empty_rest_of_line ();
3464 if (!unwind
.proc_start
)
3465 as_bad (MISSING_FNSTART
);
3467 if (unwind
.table_entry
)
3468 as_bad (_("duplicate .handlerdata directive"));
3470 create_unwind_entry (1);
3473 /* Parse an unwind_fnend directive. Generates the index table entry. */
3476 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3481 unsigned int marked_pr_dependency
;
3483 demand_empty_rest_of_line ();
3485 if (!unwind
.proc_start
)
3487 as_bad (_(".fnend directive without .fnstart"));
3491 /* Add eh table entry. */
3492 if (unwind
.table_entry
== NULL
)
3493 val
= create_unwind_entry (0);
3497 /* Add index table entry. This is two words. */
3498 start_unwind_section (unwind
.saved_seg
, 1);
3499 frag_align (2, 0, 0);
3500 record_alignment (now_seg
, 2);
3502 ptr
= frag_more (8);
3503 where
= frag_now_fix () - 8;
3505 /* Self relative offset of the function start. */
3506 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3507 BFD_RELOC_ARM_PREL31
);
3509 /* Indicate dependency on EHABI-defined personality routines to the
3510 linker, if it hasn't been done already. */
3511 marked_pr_dependency
3512 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3513 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3514 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3516 static const char *const name
[] =
3518 "__aeabi_unwind_cpp_pr0",
3519 "__aeabi_unwind_cpp_pr1",
3520 "__aeabi_unwind_cpp_pr2"
3522 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3523 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3524 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3525 |= 1 << unwind
.personality_index
;
3529 /* Inline exception table entry. */
3530 md_number_to_chars (ptr
+ 4, val
, 4);
3532 /* Self relative offset of the table entry. */
3533 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3534 BFD_RELOC_ARM_PREL31
);
3536 /* Restore the original section. */
3537 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3539 unwind
.proc_start
= NULL
;
3543 /* Parse an unwind_cantunwind directive. */
3546 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3548 demand_empty_rest_of_line ();
3549 if (!unwind
.proc_start
)
3550 as_bad (MISSING_FNSTART
);
3552 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3553 as_bad (_("personality routine specified for cantunwind frame"));
3555 unwind
.personality_index
= -2;
3559 /* Parse a personalityindex directive. */
3562 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("duplicate .personalityindex directive"));
3574 if (exp
.X_op
!= O_constant
3575 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3577 as_bad (_("bad personality routine number"));
3578 ignore_rest_of_line ();
3582 unwind
.personality_index
= exp
.X_add_number
;
3584 demand_empty_rest_of_line ();
3588 /* Parse a personality directive. */
3591 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3595 if (!unwind
.proc_start
)
3596 as_bad (MISSING_FNSTART
);
3598 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3599 as_bad (_("duplicate .personality directive"));
3601 name
= input_line_pointer
;
3602 c
= get_symbol_end ();
3603 p
= input_line_pointer
;
3604 unwind
.personality_routine
= symbol_find_or_make (name
);
3606 demand_empty_rest_of_line ();
3610 /* Parse a directive saving core registers. */
3613 s_arm_unwind_save_core (void)
3619 range
= parse_reg_list (&input_line_pointer
);
3622 as_bad (_("expected register list"));
3623 ignore_rest_of_line ();
3627 demand_empty_rest_of_line ();
3629 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3630 into .unwind_save {..., sp...}. We aren't bothered about the value of
3631 ip because it is clobbered by calls. */
3632 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3633 && (range
& 0x3000) == 0x1000)
3635 unwind
.opcode_count
--;
3636 unwind
.sp_restored
= 0;
3637 range
= (range
| 0x2000) & ~0x1000;
3638 unwind
.pending_offset
= 0;
3644 /* See if we can use the short opcodes. These pop a block of up to 8
3645 registers starting with r4, plus maybe r14. */
3646 for (n
= 0; n
< 8; n
++)
3648 /* Break at the first non-saved register. */
3649 if ((range
& (1 << (n
+ 4))) == 0)
3652 /* See if there are any other bits set. */
3653 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3655 /* Use the long form. */
3656 op
= 0x8000 | ((range
>> 4) & 0xfff);
3657 add_unwind_opcode (op
, 2);
3661 /* Use the short form. */
3663 op
= 0xa8; /* Pop r14. */
3665 op
= 0xa0; /* Do not pop r14. */
3667 add_unwind_opcode (op
, 1);
3674 op
= 0xb100 | (range
& 0xf);
3675 add_unwind_opcode (op
, 2);
3678 /* Record the number of bytes pushed. */
3679 for (n
= 0; n
< 16; n
++)
3681 if (range
& (1 << n
))
3682 unwind
.frame_size
+= 4;
3687 /* Parse a directive saving FPA registers. */
3690 s_arm_unwind_save_fpa (int reg
)
3696 /* Get Number of registers to transfer. */
3697 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3700 exp
.X_op
= O_illegal
;
3702 if (exp
.X_op
!= O_constant
)
3704 as_bad (_("expected , <constant>"));
3705 ignore_rest_of_line ();
3709 num_regs
= exp
.X_add_number
;
3711 if (num_regs
< 1 || num_regs
> 4)
3713 as_bad (_("number of registers must be in the range [1:4]"));
3714 ignore_rest_of_line ();
3718 demand_empty_rest_of_line ();
3723 op
= 0xb4 | (num_regs
- 1);
3724 add_unwind_opcode (op
, 1);
3729 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3730 add_unwind_opcode (op
, 2);
3732 unwind
.frame_size
+= num_regs
* 12;
3736 /* Parse a directive saving VFP registers for ARMv6 and above. */
3739 s_arm_unwind_save_vfp_armv6 (void)
3744 int num_vfpv3_regs
= 0;
3745 int num_regs_below_16
;
3747 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3750 as_bad (_("expected register list"));
3751 ignore_rest_of_line ();
3755 demand_empty_rest_of_line ();
3757 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3758 than FSTMX/FLDMX-style ones). */
3760 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3762 num_vfpv3_regs
= count
;
3763 else if (start
+ count
> 16)
3764 num_vfpv3_regs
= start
+ count
- 16;
3766 if (num_vfpv3_regs
> 0)
3768 int start_offset
= start
> 16 ? start
- 16 : 0;
3769 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3770 add_unwind_opcode (op
, 2);
3773 /* Generate opcode for registers numbered in the range 0 .. 15. */
3774 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3775 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3776 if (num_regs_below_16
> 0)
3778 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3779 add_unwind_opcode (op
, 2);
3782 unwind
.frame_size
+= count
* 8;
3786 /* Parse a directive saving VFP registers for pre-ARMv6. */
3789 s_arm_unwind_save_vfp (void)
3795 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3798 as_bad (_("expected register list"));
3799 ignore_rest_of_line ();
3803 demand_empty_rest_of_line ();
3808 op
= 0xb8 | (count
- 1);
3809 add_unwind_opcode (op
, 1);
3814 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3815 add_unwind_opcode (op
, 2);
3817 unwind
.frame_size
+= count
* 8 + 4;
3821 /* Parse a directive saving iWMMXt data registers. */
3824 s_arm_unwind_save_mmxwr (void)
3832 if (*input_line_pointer
== '{')
3833 input_line_pointer
++;
3837 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3841 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3846 as_tsktsk (_("register list not in ascending order"));
3849 if (*input_line_pointer
== '-')
3851 input_line_pointer
++;
3852 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3855 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3858 else if (reg
>= hi_reg
)
3860 as_bad (_("bad register range"));
3863 for (; reg
< hi_reg
; reg
++)
3867 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3869 if (*input_line_pointer
== '}')
3870 input_line_pointer
++;
3872 demand_empty_rest_of_line ();
3874 /* Generate any deferred opcodes because we're going to be looking at
3876 flush_pending_unwind ();
3878 for (i
= 0; i
< 16; i
++)
3880 if (mask
& (1 << i
))
3881 unwind
.frame_size
+= 8;
3884 /* Attempt to combine with a previous opcode. We do this because gcc
3885 likes to output separate unwind directives for a single block of
3887 if (unwind
.opcode_count
> 0)
3889 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3890 if ((i
& 0xf8) == 0xc0)
3893 /* Only merge if the blocks are contiguous. */
3896 if ((mask
& 0xfe00) == (1 << 9))
3898 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3899 unwind
.opcode_count
--;
3902 else if (i
== 6 && unwind
.opcode_count
>= 2)
3904 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3908 op
= 0xffff << (reg
- 1);
3910 && ((mask
& op
) == (1u << (reg
- 1))))
3912 op
= (1 << (reg
+ i
+ 1)) - 1;
3913 op
&= ~((1 << reg
) - 1);
3915 unwind
.opcode_count
-= 2;
3922 /* We want to generate opcodes in the order the registers have been
3923 saved, ie. descending order. */
3924 for (reg
= 15; reg
>= -1; reg
--)
3926 /* Save registers in blocks. */
3928 || !(mask
& (1 << reg
)))
3930 /* We found an unsaved reg. Generate opcodes to save the
3937 op
= 0xc0 | (hi_reg
- 10);
3938 add_unwind_opcode (op
, 1);
3943 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3944 add_unwind_opcode (op
, 2);
3953 ignore_rest_of_line ();
3957 s_arm_unwind_save_mmxwcg (void)
3964 if (*input_line_pointer
== '{')
3965 input_line_pointer
++;
3969 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3973 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3979 as_tsktsk (_("register list not in ascending order"));
3982 if (*input_line_pointer
== '-')
3984 input_line_pointer
++;
3985 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3988 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3991 else if (reg
>= hi_reg
)
3993 as_bad (_("bad register range"));
3996 for (; reg
< hi_reg
; reg
++)
4000 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4002 if (*input_line_pointer
== '}')
4003 input_line_pointer
++;
4005 demand_empty_rest_of_line ();
4007 /* Generate any deferred opcodes because we're going to be looking at
4009 flush_pending_unwind ();
4011 for (reg
= 0; reg
< 16; reg
++)
4013 if (mask
& (1 << reg
))
4014 unwind
.frame_size
+= 4;
4017 add_unwind_opcode (op
, 2);
4020 ignore_rest_of_line ();
4024 /* Parse an unwind_save directive.
4025 If the argument is non-zero, this is a .vsave directive. */
4028 s_arm_unwind_save (int arch_v6
)
4031 struct reg_entry
*reg
;
4032 bfd_boolean had_brace
= FALSE
;
4034 if (!unwind
.proc_start
)
4035 as_bad (MISSING_FNSTART
);
4037 /* Figure out what sort of save we have. */
4038 peek
= input_line_pointer
;
4046 reg
= arm_reg_parse_multi (&peek
);
4050 as_bad (_("register expected"));
4051 ignore_rest_of_line ();
4060 as_bad (_("FPA .unwind_save does not take a register list"));
4061 ignore_rest_of_line ();
4064 input_line_pointer
= peek
;
4065 s_arm_unwind_save_fpa (reg
->number
);
4068 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4071 s_arm_unwind_save_vfp_armv6 ();
4073 s_arm_unwind_save_vfp ();
4075 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4076 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4079 as_bad (_(".unwind_save does not support this kind of register"));
4080 ignore_rest_of_line ();
4085 /* Parse an unwind_movsp directive. */
4088 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4094 if (!unwind
.proc_start
)
4095 as_bad (MISSING_FNSTART
);
4097 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4100 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4101 ignore_rest_of_line ();
4105 /* Optional constant. */
4106 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4108 if (immediate_for_directive (&offset
) == FAIL
)
4114 demand_empty_rest_of_line ();
4116 if (reg
== REG_SP
|| reg
== REG_PC
)
4118 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4122 if (unwind
.fp_reg
!= REG_SP
)
4123 as_bad (_("unexpected .unwind_movsp directive"));
4125 /* Generate opcode to restore the value. */
4127 add_unwind_opcode (op
, 1);
4129 /* Record the information for later. */
4130 unwind
.fp_reg
= reg
;
4131 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4132 unwind
.sp_restored
= 1;
4135 /* Parse an unwind_pad directive. */
4138 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4142 if (!unwind
.proc_start
)
4143 as_bad (MISSING_FNSTART
);
4145 if (immediate_for_directive (&offset
) == FAIL
)
4150 as_bad (_("stack increment must be multiple of 4"));
4151 ignore_rest_of_line ();
4155 /* Don't generate any opcodes, just record the details for later. */
4156 unwind
.frame_size
+= offset
;
4157 unwind
.pending_offset
+= offset
;
4159 demand_empty_rest_of_line ();
4162 /* Parse an unwind_setfp directive. */
4165 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4171 if (!unwind
.proc_start
)
4172 as_bad (MISSING_FNSTART
);
4174 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4175 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4178 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4180 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4182 as_bad (_("expected <reg>, <reg>"));
4183 ignore_rest_of_line ();
4187 /* Optional constant. */
4188 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4190 if (immediate_for_directive (&offset
) == FAIL
)
4196 demand_empty_rest_of_line ();
4198 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4200 as_bad (_("register must be either sp or set by a previous"
4201 "unwind_movsp directive"));
4205 /* Don't generate any opcodes, just record the information for later. */
4206 unwind
.fp_reg
= fp_reg
;
4208 if (sp_reg
== REG_SP
)
4209 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4211 unwind
.fp_offset
-= offset
;
4214 /* Parse an unwind_raw directive. */
4217 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4220 /* This is an arbitrary limit. */
4221 unsigned char op
[16];
4224 if (!unwind
.proc_start
)
4225 as_bad (MISSING_FNSTART
);
4228 if (exp
.X_op
== O_constant
4229 && skip_past_comma (&input_line_pointer
) != FAIL
)
4231 unwind
.frame_size
+= exp
.X_add_number
;
4235 exp
.X_op
= O_illegal
;
4237 if (exp
.X_op
!= O_constant
)
4239 as_bad (_("expected <offset>, <opcode>"));
4240 ignore_rest_of_line ();
4246 /* Parse the opcode. */
4251 as_bad (_("unwind opcode too long"));
4252 ignore_rest_of_line ();
4254 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4256 as_bad (_("invalid unwind opcode"));
4257 ignore_rest_of_line ();
4260 op
[count
++] = exp
.X_add_number
;
4262 /* Parse the next byte. */
4263 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4269 /* Add the opcode bytes in reverse order. */
4271 add_unwind_opcode (op
[count
], 1);
4273 demand_empty_rest_of_line ();
4277 /* Parse a .eabi_attribute directive. */
4280 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4282 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4284 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4285 attributes_set_explicitly
[tag
] = 1;
4288 /* Emit a tls fix for the symbol. */
4291 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4295 #ifdef md_flush_pending_output
4296 md_flush_pending_output ();
4299 #ifdef md_cons_align
4303 /* Since we're just labelling the code, there's no need to define a
4306 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4307 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4308 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4309 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4311 #endif /* OBJ_ELF */
4313 static void s_arm_arch (int);
4314 static void s_arm_object_arch (int);
4315 static void s_arm_cpu (int);
4316 static void s_arm_fpu (int);
4317 static void s_arm_arch_extension (int);
4322 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4329 if (exp
.X_op
== O_symbol
)
4330 exp
.X_op
= O_secrel
;
4332 emit_expr (&exp
, 4);
4334 while (*input_line_pointer
++ == ',');
4336 input_line_pointer
--;
4337 demand_empty_rest_of_line ();
4341 /* This table describes all the machine specific pseudo-ops the assembler
4342 has to support. The fields are:
4343 pseudo-op name without dot
4344 function to call to execute this pseudo-op
4345 Integer arg to pass to the function. */
4347 const pseudo_typeS md_pseudo_table
[] =
4349 /* Never called because '.req' does not start a line. */
4350 { "req", s_req
, 0 },
4351 /* Following two are likewise never called. */
4354 { "unreq", s_unreq
, 0 },
4355 { "bss", s_bss
, 0 },
4356 { "align", s_align
, 0 },
4357 { "arm", s_arm
, 0 },
4358 { "thumb", s_thumb
, 0 },
4359 { "code", s_code
, 0 },
4360 { "force_thumb", s_force_thumb
, 0 },
4361 { "thumb_func", s_thumb_func
, 0 },
4362 { "thumb_set", s_thumb_set
, 0 },
4363 { "even", s_even
, 0 },
4364 { "ltorg", s_ltorg
, 0 },
4365 { "pool", s_ltorg
, 0 },
4366 { "syntax", s_syntax
, 0 },
4367 { "cpu", s_arm_cpu
, 0 },
4368 { "arch", s_arm_arch
, 0 },
4369 { "object_arch", s_arm_object_arch
, 0 },
4370 { "fpu", s_arm_fpu
, 0 },
4371 { "arch_extension", s_arm_arch_extension
, 0 },
4373 { "word", s_arm_elf_cons
, 4 },
4374 { "long", s_arm_elf_cons
, 4 },
4375 { "inst.n", s_arm_elf_inst
, 2 },
4376 { "inst.w", s_arm_elf_inst
, 4 },
4377 { "inst", s_arm_elf_inst
, 0 },
4378 { "rel31", s_arm_rel31
, 0 },
4379 { "fnstart", s_arm_unwind_fnstart
, 0 },
4380 { "fnend", s_arm_unwind_fnend
, 0 },
4381 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4382 { "personality", s_arm_unwind_personality
, 0 },
4383 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4384 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4385 { "save", s_arm_unwind_save
, 0 },
4386 { "vsave", s_arm_unwind_save
, 1 },
4387 { "movsp", s_arm_unwind_movsp
, 0 },
4388 { "pad", s_arm_unwind_pad
, 0 },
4389 { "setfp", s_arm_unwind_setfp
, 0 },
4390 { "unwind_raw", s_arm_unwind_raw
, 0 },
4391 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4392 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4396 /* These are used for dwarf. */
4400 /* These are used for dwarf2. */
4401 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4402 { "loc", dwarf2_directive_loc
, 0 },
4403 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4405 { "extend", float_cons
, 'x' },
4406 { "ldouble", float_cons
, 'x' },
4407 { "packed", float_cons
, 'p' },
4409 {"secrel32", pe_directive_secrel
, 0},
4414 /* Parser functions used exclusively in instruction operands. */
4416 /* Generic immediate-value read function for use in insn parsing.
4417 STR points to the beginning of the immediate (the leading #);
4418 VAL receives the value; if the value is outside [MIN, MAX]
4419 issue an error. PREFIX_OPT is true if the immediate prefix is
4423 parse_immediate (char **str
, int *val
, int min
, int max
,
4424 bfd_boolean prefix_opt
)
4427 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4428 if (exp
.X_op
!= O_constant
)
4430 inst
.error
= _("constant expression required");
4434 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4436 inst
.error
= _("immediate value out of range");
4440 *val
= exp
.X_add_number
;
4444 /* Less-generic immediate-value read function with the possibility of loading a
4445 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4446 instructions. Puts the result directly in inst.operands[i]. */
4449 parse_big_immediate (char **str
, int i
)
4454 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4456 if (exp
.X_op
== O_constant
)
4458 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4459 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4460 O_constant. We have to be careful not to break compilation for
4461 32-bit X_add_number, though. */
4462 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4464 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4465 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4466 inst
.operands
[i
].regisimm
= 1;
4469 else if (exp
.X_op
== O_big
4470 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4472 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4474 /* Bignums have their least significant bits in
4475 generic_bignum[0]. Make sure we put 32 bits in imm and
4476 32 bits in reg, in a (hopefully) portable way. */
4477 gas_assert (parts
!= 0);
4479 /* Make sure that the number is not too big.
4480 PR 11972: Bignums can now be sign-extended to the
4481 size of a .octa so check that the out of range bits
4482 are all zero or all one. */
4483 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4485 LITTLENUM_TYPE m
= -1;
4487 if (generic_bignum
[parts
* 2] != 0
4488 && generic_bignum
[parts
* 2] != m
)
4491 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4492 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4496 inst
.operands
[i
].imm
= 0;
4497 for (j
= 0; j
< parts
; j
++, idx
++)
4498 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4499 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4500 inst
.operands
[i
].reg
= 0;
4501 for (j
= 0; j
< parts
; j
++, idx
++)
4502 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4503 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4504 inst
.operands
[i
].regisimm
= 1;
4514 /* Returns the pseudo-register number of an FPA immediate constant,
4515 or FAIL if there isn't a valid constant here. */
4518 parse_fpa_immediate (char ** str
)
4520 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4526 /* First try and match exact strings, this is to guarantee
4527 that some formats will work even for cross assembly. */
4529 for (i
= 0; fp_const
[i
]; i
++)
4531 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4535 *str
+= strlen (fp_const
[i
]);
4536 if (is_end_of_line
[(unsigned char) **str
])
4542 /* Just because we didn't get a match doesn't mean that the constant
4543 isn't valid, just that it is in a format that we don't
4544 automatically recognize. Try parsing it with the standard
4545 expression routines. */
4547 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4549 /* Look for a raw floating point number. */
4550 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4551 && is_end_of_line
[(unsigned char) *save_in
])
4553 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4555 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4557 if (words
[j
] != fp_values
[i
][j
])
4561 if (j
== MAX_LITTLENUMS
)
4569 /* Try and parse a more complex expression, this will probably fail
4570 unless the code uses a floating point prefix (eg "0f"). */
4571 save_in
= input_line_pointer
;
4572 input_line_pointer
= *str
;
4573 if (expression (&exp
) == absolute_section
4574 && exp
.X_op
== O_big
4575 && exp
.X_add_number
< 0)
4577 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4579 if (gen_to_words (words
, 5, (long) 15) == 0)
4581 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4583 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4585 if (words
[j
] != fp_values
[i
][j
])
4589 if (j
== MAX_LITTLENUMS
)
4591 *str
= input_line_pointer
;
4592 input_line_pointer
= save_in
;
4599 *str
= input_line_pointer
;
4600 input_line_pointer
= save_in
;
4601 inst
.error
= _("invalid FPA immediate expression");
4605 /* Returns 1 if a number has "quarter-precision" float format
4606 0baBbbbbbc defgh000 00000000 00000000. */
4609 is_quarter_float (unsigned imm
)
4611 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4612 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4615 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4616 0baBbbbbbc defgh000 00000000 00000000.
4617 The zero and minus-zero cases need special handling, since they can't be
4618 encoded in the "quarter-precision" float format, but can nonetheless be
4619 loaded as integer constants. */
4622 parse_qfloat_immediate (char **ccp
, int *immed
)
4626 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4627 int found_fpchar
= 0;
4629 skip_past_char (&str
, '#');
4631 /* We must not accidentally parse an integer as a floating-point number. Make
4632 sure that the value we parse is not an integer by checking for special
4633 characters '.' or 'e'.
4634 FIXME: This is a horrible hack, but doing better is tricky because type
4635 information isn't in a very usable state at parse time. */
4637 skip_whitespace (fpnum
);
4639 if (strncmp (fpnum
, "0x", 2) == 0)
4643 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4644 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4654 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4656 unsigned fpword
= 0;
4659 /* Our FP word must be 32 bits (single-precision FP). */
4660 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4662 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4666 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4679 /* Shift operands. */
4682 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4685 struct asm_shift_name
4688 enum shift_kind kind
;
4691 /* Third argument to parse_shift. */
4692 enum parse_shift_mode
4694 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4695 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4696 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4697 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4698 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4701 /* Parse a <shift> specifier on an ARM data processing instruction.
4702 This has three forms:
4704 (LSL|LSR|ASL|ASR|ROR) Rs
4705 (LSL|LSR|ASL|ASR|ROR) #imm
4708 Note that ASL is assimilated to LSL in the instruction encoding, and
4709 RRX to ROR #0 (which cannot be written as such). */
4712 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4714 const struct asm_shift_name
*shift_name
;
4715 enum shift_kind shift
;
4720 for (p
= *str
; ISALPHA (*p
); p
++)
4725 inst
.error
= _("shift expression expected");
4729 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4732 if (shift_name
== NULL
)
4734 inst
.error
= _("shift expression expected");
4738 shift
= shift_name
->kind
;
4742 case NO_SHIFT_RESTRICT
:
4743 case SHIFT_IMMEDIATE
: break;
4745 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4746 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4748 inst
.error
= _("'LSL' or 'ASR' required");
4753 case SHIFT_LSL_IMMEDIATE
:
4754 if (shift
!= SHIFT_LSL
)
4756 inst
.error
= _("'LSL' required");
4761 case SHIFT_ASR_IMMEDIATE
:
4762 if (shift
!= SHIFT_ASR
)
4764 inst
.error
= _("'ASR' required");
4772 if (shift
!= SHIFT_RRX
)
4774 /* Whitespace can appear here if the next thing is a bare digit. */
4775 skip_whitespace (p
);
4777 if (mode
== NO_SHIFT_RESTRICT
4778 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4780 inst
.operands
[i
].imm
= reg
;
4781 inst
.operands
[i
].immisreg
= 1;
4783 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4786 inst
.operands
[i
].shift_kind
= shift
;
4787 inst
.operands
[i
].shifted
= 1;
4792 /* Parse a <shifter_operand> for an ARM data processing instruction:
4795 #<immediate>, <rotate>
4799 where <shift> is defined by parse_shift above, and <rotate> is a
4800 multiple of 2 between 0 and 30. Validation of immediate operands
4801 is deferred to md_apply_fix. */
4804 parse_shifter_operand (char **str
, int i
)
4809 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4811 inst
.operands
[i
].reg
= value
;
4812 inst
.operands
[i
].isreg
= 1;
4814 /* parse_shift will override this if appropriate */
4815 inst
.reloc
.exp
.X_op
= O_constant
;
4816 inst
.reloc
.exp
.X_add_number
= 0;
4818 if (skip_past_comma (str
) == FAIL
)
4821 /* Shift operation on register. */
4822 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4825 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4828 if (skip_past_comma (str
) == SUCCESS
)
4830 /* #x, y -- ie explicit rotation by Y. */
4831 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4834 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4836 inst
.error
= _("constant expression expected");
4840 value
= exp
.X_add_number
;
4841 if (value
< 0 || value
> 30 || value
% 2 != 0)
4843 inst
.error
= _("invalid rotation");
4846 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4848 inst
.error
= _("invalid constant");
4852 /* Convert to decoded value. md_apply_fix will put it back. */
4853 inst
.reloc
.exp
.X_add_number
4854 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4855 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4858 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4859 inst
.reloc
.pc_rel
= 0;
4863 /* Group relocation information. Each entry in the table contains the
4864 textual name of the relocation as may appear in assembler source
4865 and must end with a colon.
4866 Along with this textual name are the relocation codes to be used if
4867 the corresponding instruction is an ALU instruction (ADD or SUB only),
4868 an LDR, an LDRS, or an LDC. */
4870 struct group_reloc_table_entry
4881 /* Varieties of non-ALU group relocation. */
4888 static struct group_reloc_table_entry group_reloc_table
[] =
4889 { /* Program counter relative: */
4891 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4896 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4897 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4898 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4899 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4901 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4906 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4907 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4908 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4909 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4911 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4912 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4913 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4914 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4915 /* Section base relative */
4917 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4922 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4923 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4924 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4925 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4927 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4932 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4933 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4934 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4935 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4937 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4938 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4939 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4940 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4942 /* Given the address of a pointer pointing to the textual name of a group
4943 relocation as may appear in assembler source, attempt to find its details
4944 in group_reloc_table. The pointer will be updated to the character after
4945 the trailing colon. On failure, FAIL will be returned; SUCCESS
4946 otherwise. On success, *entry will be updated to point at the relevant
4947 group_reloc_table entry. */
4950 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4953 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4955 int length
= strlen (group_reloc_table
[i
].name
);
4957 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4958 && (*str
)[length
] == ':')
4960 *out
= &group_reloc_table
[i
];
4961 *str
+= (length
+ 1);
4969 /* Parse a <shifter_operand> for an ARM data processing instruction
4970 (as for parse_shifter_operand) where group relocations are allowed:
4973 #<immediate>, <rotate>
4974 #:<group_reloc>:<expression>
4978 where <group_reloc> is one of the strings defined in group_reloc_table.
4979 The hashes are optional.
4981 Everything else is as for parse_shifter_operand. */
4983 static parse_operand_result
4984 parse_shifter_operand_group_reloc (char **str
, int i
)
4986 /* Determine if we have the sequence of characters #: or just :
4987 coming next. If we do, then we check for a group relocation.
4988 If we don't, punt the whole lot to parse_shifter_operand. */
4990 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4991 || (*str
)[0] == ':')
4993 struct group_reloc_table_entry
*entry
;
4995 if ((*str
)[0] == '#')
5000 /* Try to parse a group relocation. Anything else is an error. */
5001 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5003 inst
.error
= _("unknown group relocation");
5004 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5007 /* We now have the group relocation table entry corresponding to
5008 the name in the assembler source. Next, we parse the expression. */
5009 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5010 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5012 /* Record the relocation type (always the ALU variant here). */
5013 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5014 gas_assert (inst
.reloc
.type
!= 0);
5016 return PARSE_OPERAND_SUCCESS
;
5019 return parse_shifter_operand (str
, i
) == SUCCESS
5020 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5022 /* Never reached. */
5025 /* Parse a Neon alignment expression. Information is written to
5026 inst.operands[i]. We assume the initial ':' has been skipped.
5028 align .imm = align << 8, .immisalign=1, .preind=0 */
5029 static parse_operand_result
5030 parse_neon_alignment (char **str
, int i
)
5035 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5037 if (exp
.X_op
!= O_constant
)
5039 inst
.error
= _("alignment must be constant");
5040 return PARSE_OPERAND_FAIL
;
5043 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5044 inst
.operands
[i
].immisalign
= 1;
5045 /* Alignments are not pre-indexes. */
5046 inst
.operands
[i
].preind
= 0;
5049 return PARSE_OPERAND_SUCCESS
;
5052 /* Parse all forms of an ARM address expression. Information is written
5053 to inst.operands[i] and/or inst.reloc.
5055 Preindexed addressing (.preind=1):
5057 [Rn, #offset] .reg=Rn .reloc.exp=offset
5058 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5059 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5060 .shift_kind=shift .reloc.exp=shift_imm
5062 These three may have a trailing ! which causes .writeback to be set also.
5064 Postindexed addressing (.postind=1, .writeback=1):
5066 [Rn], #offset .reg=Rn .reloc.exp=offset
5067 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5068 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5069 .shift_kind=shift .reloc.exp=shift_imm
5071 Unindexed addressing (.preind=0, .postind=0):
5073 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5077 [Rn]{!} shorthand for [Rn,#0]{!}
5078 =immediate .isreg=0 .reloc.exp=immediate
5079 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5081 It is the caller's responsibility to check for addressing modes not
5082 supported by the instruction, and to set inst.reloc.type. */
5084 static parse_operand_result
5085 parse_address_main (char **str
, int i
, int group_relocations
,
5086 group_reloc_type group_type
)
5091 if (skip_past_char (&p
, '[') == FAIL
)
5093 if (skip_past_char (&p
, '=') == FAIL
)
5095 /* Bare address - translate to PC-relative offset. */
5096 inst
.reloc
.pc_rel
= 1;
5097 inst
.operands
[i
].reg
= REG_PC
;
5098 inst
.operands
[i
].isreg
= 1;
5099 inst
.operands
[i
].preind
= 1;
5101 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5103 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5104 return PARSE_OPERAND_FAIL
;
5107 return PARSE_OPERAND_SUCCESS
;
5110 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5112 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5113 return PARSE_OPERAND_FAIL
;
5115 inst
.operands
[i
].reg
= reg
;
5116 inst
.operands
[i
].isreg
= 1;
5118 if (skip_past_comma (&p
) == SUCCESS
)
5120 inst
.operands
[i
].preind
= 1;
5123 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5125 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5127 inst
.operands
[i
].imm
= reg
;
5128 inst
.operands
[i
].immisreg
= 1;
5130 if (skip_past_comma (&p
) == SUCCESS
)
5131 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5132 return PARSE_OPERAND_FAIL
;
5134 else if (skip_past_char (&p
, ':') == SUCCESS
)
5136 /* FIXME: '@' should be used here, but it's filtered out by generic
5137 code before we get to see it here. This may be subject to
5139 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5141 if (result
!= PARSE_OPERAND_SUCCESS
)
5146 if (inst
.operands
[i
].negative
)
5148 inst
.operands
[i
].negative
= 0;
5152 if (group_relocations
5153 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5155 struct group_reloc_table_entry
*entry
;
5157 /* Skip over the #: or : sequence. */
5163 /* Try to parse a group relocation. Anything else is an
5165 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5167 inst
.error
= _("unknown group relocation");
5168 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5171 /* We now have the group relocation table entry corresponding to
5172 the name in the assembler source. Next, we parse the
5174 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5175 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5177 /* Record the relocation type. */
5181 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5185 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5189 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5196 if (inst
.reloc
.type
== 0)
5198 inst
.error
= _("this group relocation is not allowed on this instruction");
5199 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5205 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5206 return PARSE_OPERAND_FAIL
;
5207 /* If the offset is 0, find out if it's a +0 or -0. */
5208 if (inst
.reloc
.exp
.X_op
== O_constant
5209 && inst
.reloc
.exp
.X_add_number
== 0)
5211 skip_whitespace (q
);
5215 skip_whitespace (q
);
5218 inst
.operands
[i
].negative
= 1;
5223 else if (skip_past_char (&p
, ':') == SUCCESS
)
5225 /* FIXME: '@' should be used here, but it's filtered out by generic code
5226 before we get to see it here. This may be subject to change. */
5227 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5229 if (result
!= PARSE_OPERAND_SUCCESS
)
5233 if (skip_past_char (&p
, ']') == FAIL
)
5235 inst
.error
= _("']' expected");
5236 return PARSE_OPERAND_FAIL
;
5239 if (skip_past_char (&p
, '!') == SUCCESS
)
5240 inst
.operands
[i
].writeback
= 1;
5242 else if (skip_past_comma (&p
) == SUCCESS
)
5244 if (skip_past_char (&p
, '{') == SUCCESS
)
5246 /* [Rn], {expr} - unindexed, with option */
5247 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5248 0, 255, TRUE
) == FAIL
)
5249 return PARSE_OPERAND_FAIL
;
5251 if (skip_past_char (&p
, '}') == FAIL
)
5253 inst
.error
= _("'}' expected at end of 'option' field");
5254 return PARSE_OPERAND_FAIL
;
5256 if (inst
.operands
[i
].preind
)
5258 inst
.error
= _("cannot combine index with option");
5259 return PARSE_OPERAND_FAIL
;
5262 return PARSE_OPERAND_SUCCESS
;
5266 inst
.operands
[i
].postind
= 1;
5267 inst
.operands
[i
].writeback
= 1;
5269 if (inst
.operands
[i
].preind
)
5271 inst
.error
= _("cannot combine pre- and post-indexing");
5272 return PARSE_OPERAND_FAIL
;
5276 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5278 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5280 /* We might be using the immediate for alignment already. If we
5281 are, OR the register number into the low-order bits. */
5282 if (inst
.operands
[i
].immisalign
)
5283 inst
.operands
[i
].imm
|= reg
;
5285 inst
.operands
[i
].imm
= reg
;
5286 inst
.operands
[i
].immisreg
= 1;
5288 if (skip_past_comma (&p
) == SUCCESS
)
5289 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5290 return PARSE_OPERAND_FAIL
;
5295 if (inst
.operands
[i
].negative
)
5297 inst
.operands
[i
].negative
= 0;
5300 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5301 return PARSE_OPERAND_FAIL
;
5302 /* If the offset is 0, find out if it's a +0 or -0. */
5303 if (inst
.reloc
.exp
.X_op
== O_constant
5304 && inst
.reloc
.exp
.X_add_number
== 0)
5306 skip_whitespace (q
);
5310 skip_whitespace (q
);
5313 inst
.operands
[i
].negative
= 1;
5319 /* If at this point neither .preind nor .postind is set, we have a
5320 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5321 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5323 inst
.operands
[i
].preind
= 1;
5324 inst
.reloc
.exp
.X_op
= O_constant
;
5325 inst
.reloc
.exp
.X_add_number
= 0;
5328 return PARSE_OPERAND_SUCCESS
;
5332 parse_address (char **str
, int i
)
5334 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5338 static parse_operand_result
5339 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5341 return parse_address_main (str
, i
, 1, type
);
5344 /* Parse an operand for a MOVW or MOVT instruction. */
5346 parse_half (char **str
)
5351 skip_past_char (&p
, '#');
5352 if (strncasecmp (p
, ":lower16:", 9) == 0)
5353 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5354 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5355 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5357 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5360 skip_whitespace (p
);
5363 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5366 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5368 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5370 inst
.error
= _("constant expression expected");
5373 if (inst
.reloc
.exp
.X_add_number
< 0
5374 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5376 inst
.error
= _("immediate value out of range");
5384 /* Miscellaneous. */
5386 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5387 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5389 parse_psr (char **str
, bfd_boolean lhs
)
5392 unsigned long psr_field
;
5393 const struct asm_psr
*psr
;
5395 bfd_boolean is_apsr
= FALSE
;
5396 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5398 /* PR gas/12698: If the user has specified -march=all then m_profile will
5399 be TRUE, but we want to ignore it in this case as we are building for any
5400 CPU type, including non-m variants. */
5401 if (selected_cpu
.core
== arm_arch_any
.core
)
5404 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5405 feature for ease of use and backwards compatibility. */
5407 if (strncasecmp (p
, "SPSR", 4) == 0)
5410 goto unsupported_psr
;
5412 psr_field
= SPSR_BIT
;
5414 else if (strncasecmp (p
, "CPSR", 4) == 0)
5417 goto unsupported_psr
;
5421 else if (strncasecmp (p
, "APSR", 4) == 0)
5423 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5424 and ARMv7-R architecture CPUs. */
5433 while (ISALNUM (*p
) || *p
== '_');
5435 if (strncasecmp (start
, "iapsr", 5) == 0
5436 || strncasecmp (start
, "eapsr", 5) == 0
5437 || strncasecmp (start
, "xpsr", 4) == 0
5438 || strncasecmp (start
, "psr", 3) == 0)
5439 p
= start
+ strcspn (start
, "rR") + 1;
5441 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5447 /* If APSR is being written, a bitfield may be specified. Note that
5448 APSR itself is handled above. */
5449 if (psr
->field
<= 3)
5451 psr_field
= psr
->field
;
5457 /* M-profile MSR instructions have the mask field set to "10", except
5458 *PSR variants which modify APSR, which may use a different mask (and
5459 have been handled already). Do that by setting the PSR_f field
5461 return psr
->field
| (lhs
? PSR_f
: 0);
5464 goto unsupported_psr
;
5470 /* A suffix follows. */
5476 while (ISALNUM (*p
) || *p
== '_');
5480 /* APSR uses a notation for bits, rather than fields. */
5481 unsigned int nzcvq_bits
= 0;
5482 unsigned int g_bit
= 0;
5485 for (bit
= start
; bit
!= p
; bit
++)
5487 switch (TOLOWER (*bit
))
5490 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5494 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5498 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5502 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5506 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5510 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5514 inst
.error
= _("unexpected bit specified after APSR");
5519 if (nzcvq_bits
== 0x1f)
5524 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5526 inst
.error
= _("selected processor does not "
5527 "support DSP extension");
5534 if ((nzcvq_bits
& 0x20) != 0
5535 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5536 || (g_bit
& 0x2) != 0)
5538 inst
.error
= _("bad bitmask specified after APSR");
5544 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5549 psr_field
|= psr
->field
;
5555 goto error
; /* Garbage after "[CS]PSR". */
5557 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5558 is deprecated, but allow it anyway. */
5562 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5565 else if (!m_profile
)
5566 /* These bits are never right for M-profile devices: don't set them
5567 (only code paths which read/write APSR reach here). */
5568 psr_field
|= (PSR_c
| PSR_f
);
5574 inst
.error
= _("selected processor does not support requested special "
5575 "purpose register");
5579 inst
.error
= _("flag for {c}psr instruction expected");
5583 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5584 value suitable for splatting into the AIF field of the instruction. */
5587 parse_cps_flags (char **str
)
5596 case '\0': case ',':
5599 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5600 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5601 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5604 inst
.error
= _("unrecognized CPS flag");
5609 if (saw_a_flag
== 0)
5611 inst
.error
= _("missing CPS flags");
5619 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5620 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5623 parse_endian_specifier (char **str
)
5628 if (strncasecmp (s
, "BE", 2))
5630 else if (strncasecmp (s
, "LE", 2))
5634 inst
.error
= _("valid endian specifiers are be or le");
5638 if (ISALNUM (s
[2]) || s
[2] == '_')
5640 inst
.error
= _("valid endian specifiers are be or le");
5645 return little_endian
;
5648 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5649 value suitable for poking into the rotate field of an sxt or sxta
5650 instruction, or FAIL on error. */
5653 parse_ror (char **str
)
5658 if (strncasecmp (s
, "ROR", 3) == 0)
5662 inst
.error
= _("missing rotation field after comma");
5666 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5671 case 0: *str
= s
; return 0x0;
5672 case 8: *str
= s
; return 0x1;
5673 case 16: *str
= s
; return 0x2;
5674 case 24: *str
= s
; return 0x3;
5677 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5682 /* Parse a conditional code (from conds[] below). The value returned is in the
5683 range 0 .. 14, or FAIL. */
5685 parse_cond (char **str
)
5688 const struct asm_cond
*c
;
5690 /* Condition codes are always 2 characters, so matching up to
5691 3 characters is sufficient. */
5696 while (ISALPHA (*q
) && n
< 3)
5698 cond
[n
] = TOLOWER (*q
);
5703 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5706 inst
.error
= _("condition required");
5714 /* Parse an option for a barrier instruction. Returns the encoding for the
5717 parse_barrier (char **str
)
5720 const struct asm_barrier_opt
*o
;
5723 while (ISALPHA (*q
))
5726 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5735 /* Parse the operands of a table branch instruction. Similar to a memory
5738 parse_tb (char **str
)
5743 if (skip_past_char (&p
, '[') == FAIL
)
5745 inst
.error
= _("'[' expected");
5749 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5751 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5754 inst
.operands
[0].reg
= reg
;
5756 if (skip_past_comma (&p
) == FAIL
)
5758 inst
.error
= _("',' expected");
5762 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5764 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5767 inst
.operands
[0].imm
= reg
;
5769 if (skip_past_comma (&p
) == SUCCESS
)
5771 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5773 if (inst
.reloc
.exp
.X_add_number
!= 1)
5775 inst
.error
= _("invalid shift");
5778 inst
.operands
[0].shifted
= 1;
5781 if (skip_past_char (&p
, ']') == FAIL
)
5783 inst
.error
= _("']' expected");
5790 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5791 information on the types the operands can take and how they are encoded.
5792 Up to four operands may be read; this function handles setting the
5793 ".present" field for each read operand itself.
5794 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5795 else returns FAIL. */
5798 parse_neon_mov (char **str
, int *which_operand
)
5800 int i
= *which_operand
, val
;
5801 enum arm_reg_type rtype
;
5803 struct neon_type_el optype
;
5805 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5807 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5808 inst
.operands
[i
].reg
= val
;
5809 inst
.operands
[i
].isscalar
= 1;
5810 inst
.operands
[i
].vectype
= optype
;
5811 inst
.operands
[i
++].present
= 1;
5813 if (skip_past_comma (&ptr
) == FAIL
)
5816 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5819 inst
.operands
[i
].reg
= val
;
5820 inst
.operands
[i
].isreg
= 1;
5821 inst
.operands
[i
].present
= 1;
5823 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5826 /* Cases 0, 1, 2, 3, 5 (D only). */
5827 if (skip_past_comma (&ptr
) == FAIL
)
5830 inst
.operands
[i
].reg
= val
;
5831 inst
.operands
[i
].isreg
= 1;
5832 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5833 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5834 inst
.operands
[i
].isvec
= 1;
5835 inst
.operands
[i
].vectype
= optype
;
5836 inst
.operands
[i
++].present
= 1;
5838 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5840 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5841 Case 13: VMOV <Sd>, <Rm> */
5842 inst
.operands
[i
].reg
= val
;
5843 inst
.operands
[i
].isreg
= 1;
5844 inst
.operands
[i
].present
= 1;
5846 if (rtype
== REG_TYPE_NQ
)
5848 first_error (_("can't use Neon quad register here"));
5851 else if (rtype
!= REG_TYPE_VFS
)
5854 if (skip_past_comma (&ptr
) == FAIL
)
5856 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5858 inst
.operands
[i
].reg
= val
;
5859 inst
.operands
[i
].isreg
= 1;
5860 inst
.operands
[i
].present
= 1;
5863 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5866 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5867 Case 1: VMOV<c><q> <Dd>, <Dm>
5868 Case 8: VMOV.F32 <Sd>, <Sm>
5869 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5871 inst
.operands
[i
].reg
= val
;
5872 inst
.operands
[i
].isreg
= 1;
5873 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5874 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5875 inst
.operands
[i
].isvec
= 1;
5876 inst
.operands
[i
].vectype
= optype
;
5877 inst
.operands
[i
].present
= 1;
5879 if (skip_past_comma (&ptr
) == SUCCESS
)
5884 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5887 inst
.operands
[i
].reg
= val
;
5888 inst
.operands
[i
].isreg
= 1;
5889 inst
.operands
[i
++].present
= 1;
5891 if (skip_past_comma (&ptr
) == FAIL
)
5894 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5897 inst
.operands
[i
].reg
= val
;
5898 inst
.operands
[i
].isreg
= 1;
5899 inst
.operands
[i
++].present
= 1;
5902 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5903 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5904 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5905 Case 10: VMOV.F32 <Sd>, #<imm>
5906 Case 11: VMOV.F64 <Dd>, #<imm> */
5907 inst
.operands
[i
].immisfloat
= 1;
5908 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5909 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5910 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5914 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5918 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5921 inst
.operands
[i
].reg
= val
;
5922 inst
.operands
[i
].isreg
= 1;
5923 inst
.operands
[i
++].present
= 1;
5925 if (skip_past_comma (&ptr
) == FAIL
)
5928 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5930 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5931 inst
.operands
[i
].reg
= val
;
5932 inst
.operands
[i
].isscalar
= 1;
5933 inst
.operands
[i
].present
= 1;
5934 inst
.operands
[i
].vectype
= optype
;
5936 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5938 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5939 inst
.operands
[i
].reg
= val
;
5940 inst
.operands
[i
].isreg
= 1;
5941 inst
.operands
[i
++].present
= 1;
5943 if (skip_past_comma (&ptr
) == FAIL
)
5946 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5949 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5953 inst
.operands
[i
].reg
= val
;
5954 inst
.operands
[i
].isreg
= 1;
5955 inst
.operands
[i
].isvec
= 1;
5956 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5957 inst
.operands
[i
].vectype
= optype
;
5958 inst
.operands
[i
].present
= 1;
5960 if (rtype
== REG_TYPE_VFS
)
5964 if (skip_past_comma (&ptr
) == FAIL
)
5966 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5969 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5972 inst
.operands
[i
].reg
= val
;
5973 inst
.operands
[i
].isreg
= 1;
5974 inst
.operands
[i
].isvec
= 1;
5975 inst
.operands
[i
].issingle
= 1;
5976 inst
.operands
[i
].vectype
= optype
;
5977 inst
.operands
[i
].present
= 1;
5980 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5984 inst
.operands
[i
].reg
= val
;
5985 inst
.operands
[i
].isreg
= 1;
5986 inst
.operands
[i
].isvec
= 1;
5987 inst
.operands
[i
].issingle
= 1;
5988 inst
.operands
[i
].vectype
= optype
;
5989 inst
.operands
[i
++].present
= 1;
5994 first_error (_("parse error"));
5998 /* Successfully parsed the operands. Update args. */
6004 first_error (_("expected comma"));
6008 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6012 /* Use this macro when the operand constraints are different
6013 for ARM and THUMB (e.g. ldrd). */
6014 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6015 ((arm_operand) | ((thumb_operand) << 16))
6017 /* Matcher codes for parse_operands. */
6018 enum operand_parse_code
6020 OP_stop
, /* end of line */
6022 OP_RR
, /* ARM register */
6023 OP_RRnpc
, /* ARM register, not r15 */
6024 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6025 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6026 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6027 optional trailing ! */
6028 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6029 OP_RCP
, /* Coprocessor number */
6030 OP_RCN
, /* Coprocessor register */
6031 OP_RF
, /* FPA register */
6032 OP_RVS
, /* VFP single precision register */
6033 OP_RVD
, /* VFP double precision register (0..15) */
6034 OP_RND
, /* Neon double precision register (0..31) */
6035 OP_RNQ
, /* Neon quad precision register */
6036 OP_RVSD
, /* VFP single or double precision register */
6037 OP_RNDQ
, /* Neon double or quad precision register */
6038 OP_RNSDQ
, /* Neon single, double or quad precision register */
6039 OP_RNSC
, /* Neon scalar D[X] */
6040 OP_RVC
, /* VFP control register */
6041 OP_RMF
, /* Maverick F register */
6042 OP_RMD
, /* Maverick D register */
6043 OP_RMFX
, /* Maverick FX register */
6044 OP_RMDX
, /* Maverick DX register */
6045 OP_RMAX
, /* Maverick AX register */
6046 OP_RMDS
, /* Maverick DSPSC register */
6047 OP_RIWR
, /* iWMMXt wR register */
6048 OP_RIWC
, /* iWMMXt wC register */
6049 OP_RIWG
, /* iWMMXt wCG register */
6050 OP_RXA
, /* XScale accumulator register */
6052 OP_REGLST
, /* ARM register list */
6053 OP_VRSLST
, /* VFP single-precision register list */
6054 OP_VRDLST
, /* VFP double-precision register list */
6055 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6056 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6057 OP_NSTRLST
, /* Neon element/structure list */
6059 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6060 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6061 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6062 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6063 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6064 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6065 OP_VMOV
, /* Neon VMOV operands. */
6066 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6067 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6068 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6070 OP_I0
, /* immediate zero */
6071 OP_I7
, /* immediate value 0 .. 7 */
6072 OP_I15
, /* 0 .. 15 */
6073 OP_I16
, /* 1 .. 16 */
6074 OP_I16z
, /* 0 .. 16 */
6075 OP_I31
, /* 0 .. 31 */
6076 OP_I31w
, /* 0 .. 31, optional trailing ! */
6077 OP_I32
, /* 1 .. 32 */
6078 OP_I32z
, /* 0 .. 32 */
6079 OP_I63
, /* 0 .. 63 */
6080 OP_I63s
, /* -64 .. 63 */
6081 OP_I64
, /* 1 .. 64 */
6082 OP_I64z
, /* 0 .. 64 */
6083 OP_I255
, /* 0 .. 255 */
6085 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6086 OP_I7b
, /* 0 .. 7 */
6087 OP_I15b
, /* 0 .. 15 */
6088 OP_I31b
, /* 0 .. 31 */
6090 OP_SH
, /* shifter operand */
6091 OP_SHG
, /* shifter operand with possible group relocation */
6092 OP_ADDR
, /* Memory address expression (any mode) */
6093 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6094 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6095 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6096 OP_EXP
, /* arbitrary expression */
6097 OP_EXPi
, /* same, with optional immediate prefix */
6098 OP_EXPr
, /* same, with optional relocation suffix */
6099 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6101 OP_CPSF
, /* CPS flags */
6102 OP_ENDI
, /* Endianness specifier */
6103 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6104 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6105 OP_COND
, /* conditional code */
6106 OP_TB
, /* Table branch. */
6108 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6110 OP_RRnpc_I0
, /* ARM register or literal 0 */
6111 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6112 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6113 OP_RF_IF
, /* FPA register or immediate */
6114 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6115 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6117 /* Optional operands. */
6118 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6119 OP_oI31b
, /* 0 .. 31 */
6120 OP_oI32b
, /* 1 .. 32 */
6121 OP_oIffffb
, /* 0 .. 65535 */
6122 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6124 OP_oRR
, /* ARM register */
6125 OP_oRRnpc
, /* ARM register, not the PC */
6126 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6127 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6128 OP_oRND
, /* Optional Neon double precision register */
6129 OP_oRNQ
, /* Optional Neon quad precision register */
6130 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6131 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6132 OP_oSHll
, /* LSL immediate */
6133 OP_oSHar
, /* ASR immediate */
6134 OP_oSHllar
, /* LSL or ASR immediate */
6135 OP_oROR
, /* ROR 0/8/16/24 */
6136 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6138 /* Some pre-defined mixed (ARM/THUMB) operands. */
6139 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6140 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6141 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6143 OP_FIRST_OPTIONAL
= OP_oI7b
6146 /* Generic instruction operand parser. This does no encoding and no
6147 semantic validation; it merely squirrels values away in the inst
6148 structure. Returns SUCCESS or FAIL depending on whether the
6149 specified grammar matched. */
6151 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6153 unsigned const int *upat
= pattern
;
6154 char *backtrack_pos
= 0;
6155 const char *backtrack_error
= 0;
6156 int i
, val
, backtrack_index
= 0;
6157 enum arm_reg_type rtype
;
6158 parse_operand_result result
;
6159 unsigned int op_parse_code
;
6161 #define po_char_or_fail(chr) \
6164 if (skip_past_char (&str, chr) == FAIL) \
6169 #define po_reg_or_fail(regtype) \
6172 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6173 & inst.operands[i].vectype); \
6176 first_error (_(reg_expected_msgs[regtype])); \
6179 inst.operands[i].reg = val; \
6180 inst.operands[i].isreg = 1; \
6181 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6182 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6183 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6184 || rtype == REG_TYPE_VFD \
6185 || rtype == REG_TYPE_NQ); \
6189 #define po_reg_or_goto(regtype, label) \
6192 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6193 & inst.operands[i].vectype); \
6197 inst.operands[i].reg = val; \
6198 inst.operands[i].isreg = 1; \
6199 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6200 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6201 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6202 || rtype == REG_TYPE_VFD \
6203 || rtype == REG_TYPE_NQ); \
6207 #define po_imm_or_fail(min, max, popt) \
6210 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6212 inst.operands[i].imm = val; \
6216 #define po_scalar_or_goto(elsz, label) \
6219 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6222 inst.operands[i].reg = val; \
6223 inst.operands[i].isscalar = 1; \
6227 #define po_misc_or_fail(expr) \
6235 #define po_misc_or_fail_no_backtrack(expr) \
6239 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6240 backtrack_pos = 0; \
6241 if (result != PARSE_OPERAND_SUCCESS) \
6246 #define po_barrier_or_imm(str) \
6249 val = parse_barrier (&str); \
6252 if (ISALPHA (*str)) \
6259 if ((inst.instruction & 0xf0) == 0x60 \
6262 /* ISB can only take SY as an option. */ \
6263 inst.error = _("invalid barrier type"); \
6270 skip_whitespace (str
);
6272 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6274 op_parse_code
= upat
[i
];
6275 if (op_parse_code
>= 1<<16)
6276 op_parse_code
= thumb
? (op_parse_code
>> 16)
6277 : (op_parse_code
& ((1<<16)-1));
6279 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6281 /* Remember where we are in case we need to backtrack. */
6282 gas_assert (!backtrack_pos
);
6283 backtrack_pos
= str
;
6284 backtrack_error
= inst
.error
;
6285 backtrack_index
= i
;
6288 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6289 po_char_or_fail (',');
6291 switch (op_parse_code
)
6299 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6300 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6301 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6302 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6303 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6304 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6306 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6308 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6310 /* Also accept generic coprocessor regs for unknown registers. */
6312 po_reg_or_fail (REG_TYPE_CN
);
6314 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6315 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6316 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6317 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6318 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6319 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6320 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6321 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6322 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6323 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6325 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6327 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6328 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6330 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6332 /* Neon scalar. Using an element size of 8 means that some invalid
6333 scalars are accepted here, so deal with those in later code. */
6334 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6338 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6341 po_imm_or_fail (0, 0, TRUE
);
6346 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6351 po_scalar_or_goto (8, try_rr
);
6354 po_reg_or_fail (REG_TYPE_RN
);
6360 po_scalar_or_goto (8, try_nsdq
);
6363 po_reg_or_fail (REG_TYPE_NSDQ
);
6369 po_scalar_or_goto (8, try_ndq
);
6372 po_reg_or_fail (REG_TYPE_NDQ
);
6378 po_scalar_or_goto (8, try_vfd
);
6381 po_reg_or_fail (REG_TYPE_VFD
);
6386 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6387 not careful then bad things might happen. */
6388 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6393 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6396 /* There's a possibility of getting a 64-bit immediate here, so
6397 we need special handling. */
6398 if (parse_big_immediate (&str
, i
) == FAIL
)
6400 inst
.error
= _("immediate value is out of range");
6408 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6411 po_imm_or_fail (0, 63, TRUE
);
6416 po_char_or_fail ('[');
6417 po_reg_or_fail (REG_TYPE_RN
);
6418 po_char_or_fail (']');
6424 po_reg_or_fail (REG_TYPE_RN
);
6425 if (skip_past_char (&str
, '!') == SUCCESS
)
6426 inst
.operands
[i
].writeback
= 1;
6430 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6431 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6432 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6433 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6434 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6435 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6436 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6437 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6438 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6439 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6440 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6441 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6443 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6445 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6446 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6448 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6449 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6450 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6452 /* Immediate variants */
6454 po_char_or_fail ('{');
6455 po_imm_or_fail (0, 255, TRUE
);
6456 po_char_or_fail ('}');
6460 /* The expression parser chokes on a trailing !, so we have
6461 to find it first and zap it. */
6464 while (*s
&& *s
!= ',')
6469 inst
.operands
[i
].writeback
= 1;
6471 po_imm_or_fail (0, 31, TRUE
);
6479 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6484 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6489 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6491 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6493 val
= parse_reloc (&str
);
6496 inst
.error
= _("unrecognized relocation suffix");
6499 else if (val
!= BFD_RELOC_UNUSED
)
6501 inst
.operands
[i
].imm
= val
;
6502 inst
.operands
[i
].hasreloc
= 1;
6507 /* Operand for MOVW or MOVT. */
6509 po_misc_or_fail (parse_half (&str
));
6512 /* Register or expression. */
6513 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6514 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6516 /* Register or immediate. */
6517 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6518 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6520 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6522 if (!is_immediate_prefix (*str
))
6525 val
= parse_fpa_immediate (&str
);
6528 /* FPA immediates are encoded as registers 8-15.
6529 parse_fpa_immediate has already applied the offset. */
6530 inst
.operands
[i
].reg
= val
;
6531 inst
.operands
[i
].isreg
= 1;
6534 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6535 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6537 /* Two kinds of register. */
6540 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6542 || (rege
->type
!= REG_TYPE_MMXWR
6543 && rege
->type
!= REG_TYPE_MMXWC
6544 && rege
->type
!= REG_TYPE_MMXWCG
))
6546 inst
.error
= _("iWMMXt data or control register expected");
6549 inst
.operands
[i
].reg
= rege
->number
;
6550 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6556 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6558 || (rege
->type
!= REG_TYPE_MMXWC
6559 && rege
->type
!= REG_TYPE_MMXWCG
))
6561 inst
.error
= _("iWMMXt control register expected");
6564 inst
.operands
[i
].reg
= rege
->number
;
6565 inst
.operands
[i
].isreg
= 1;
6570 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6571 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6572 case OP_oROR
: val
= parse_ror (&str
); break;
6573 case OP_COND
: val
= parse_cond (&str
); break;
6574 case OP_oBARRIER_I15
:
6575 po_barrier_or_imm (str
); break;
6577 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6583 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6584 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6586 inst
.error
= _("Banked registers are not available with this "
6592 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6596 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6599 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6601 if (strncasecmp (str
, "APSR_", 5) == 0)
6608 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6609 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6610 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6611 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6612 default: found
= 16;
6616 inst
.operands
[i
].isvec
= 1;
6617 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6618 inst
.operands
[i
].reg
= REG_PC
;
6625 po_misc_or_fail (parse_tb (&str
));
6628 /* Register lists. */
6630 val
= parse_reg_list (&str
);
6633 inst
.operands
[1].writeback
= 1;
6639 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6643 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6647 /* Allow Q registers too. */
6648 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6653 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6655 inst
.operands
[i
].issingle
= 1;
6660 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6665 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6666 &inst
.operands
[i
].vectype
);
6669 /* Addressing modes */
6671 po_misc_or_fail (parse_address (&str
, i
));
6675 po_misc_or_fail_no_backtrack (
6676 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6680 po_misc_or_fail_no_backtrack (
6681 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6685 po_misc_or_fail_no_backtrack (
6686 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6690 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6694 po_misc_or_fail_no_backtrack (
6695 parse_shifter_operand_group_reloc (&str
, i
));
6699 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6703 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6707 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6711 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6714 /* Various value-based sanity checks and shared operations. We
6715 do not signal immediate failures for the register constraints;
6716 this allows a syntax error to take precedence. */
6717 switch (op_parse_code
)
6725 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6726 inst
.error
= BAD_PC
;
6731 if (inst
.operands
[i
].isreg
)
6733 if (inst
.operands
[i
].reg
== REG_PC
)
6734 inst
.error
= BAD_PC
;
6735 else if (inst
.operands
[i
].reg
== REG_SP
)
6736 inst
.error
= BAD_SP
;
6741 if (inst
.operands
[i
].isreg
6742 && inst
.operands
[i
].reg
== REG_PC
6743 && (inst
.operands
[i
].writeback
|| thumb
))
6744 inst
.error
= BAD_PC
;
6753 case OP_oBARRIER_I15
:
6762 inst
.operands
[i
].imm
= val
;
6769 /* If we get here, this operand was successfully parsed. */
6770 inst
.operands
[i
].present
= 1;
6774 inst
.error
= BAD_ARGS
;
6779 /* The parse routine should already have set inst.error, but set a
6780 default here just in case. */
6782 inst
.error
= _("syntax error");
6786 /* Do not backtrack over a trailing optional argument that
6787 absorbed some text. We will only fail again, with the
6788 'garbage following instruction' error message, which is
6789 probably less helpful than the current one. */
6790 if (backtrack_index
== i
&& backtrack_pos
!= str
6791 && upat
[i
+1] == OP_stop
)
6794 inst
.error
= _("syntax error");
6798 /* Try again, skipping the optional argument at backtrack_pos. */
6799 str
= backtrack_pos
;
6800 inst
.error
= backtrack_error
;
6801 inst
.operands
[backtrack_index
].present
= 0;
6802 i
= backtrack_index
;
6806 /* Check that we have parsed all the arguments. */
6807 if (*str
!= '\0' && !inst
.error
)
6808 inst
.error
= _("garbage following instruction");
6810 return inst
.error
? FAIL
: SUCCESS
;
6813 #undef po_char_or_fail
6814 #undef po_reg_or_fail
6815 #undef po_reg_or_goto
6816 #undef po_imm_or_fail
6817 #undef po_scalar_or_fail
6818 #undef po_barrier_or_imm
6820 /* Shorthand macro for instruction encoding functions issuing errors. */
6821 #define constraint(expr, err) \
6832 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6833 instructions are unpredictable if these registers are used. This
6834 is the BadReg predicate in ARM's Thumb-2 documentation. */
6835 #define reject_bad_reg(reg) \
6837 if (reg == REG_SP || reg == REG_PC) \
6839 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6844 /* If REG is R13 (the stack pointer), warn that its use is
6846 #define warn_deprecated_sp(reg) \
6848 if (warn_on_deprecated && reg == REG_SP) \
6849 as_warn (_("use of r13 is deprecated")); \
6852 /* Functions for operand encoding. ARM, then Thumb. */
6854 #define rotate_left(v, n) (v << n | v >> (32 - n))
6856 /* If VAL can be encoded in the immediate field of an ARM instruction,
6857 return the encoded form. Otherwise, return FAIL. */
6860 encode_arm_immediate (unsigned int val
)
6864 for (i
= 0; i
< 32; i
+= 2)
6865 if ((a
= rotate_left (val
, i
)) <= 0xff)
6866 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6871 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6872 return the encoded form. Otherwise, return FAIL. */
6874 encode_thumb32_immediate (unsigned int val
)
6881 for (i
= 1; i
<= 24; i
++)
6884 if ((val
& ~(0xff << i
)) == 0)
6885 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6889 if (val
== ((a
<< 16) | a
))
6891 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6895 if (val
== ((a
<< 16) | a
))
6896 return 0x200 | (a
>> 8);
6900 /* Encode a VFP SP or DP register number into inst.instruction. */
6903 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6905 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6908 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6911 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6914 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6919 first_error (_("D register out of range for selected VFP version"));
6927 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6931 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6935 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6939 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6943 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6947 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6955 /* Encode a <shift> in an ARM-format instruction. The immediate,
6956 if any, is handled by md_apply_fix. */
6958 encode_arm_shift (int i
)
6960 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6961 inst
.instruction
|= SHIFT_ROR
<< 5;
6964 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6965 if (inst
.operands
[i
].immisreg
)
6967 inst
.instruction
|= SHIFT_BY_REG
;
6968 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6971 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6976 encode_arm_shifter_operand (int i
)
6978 if (inst
.operands
[i
].isreg
)
6980 inst
.instruction
|= inst
.operands
[i
].reg
;
6981 encode_arm_shift (i
);
6984 inst
.instruction
|= INST_IMMEDIATE
;
6987 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6989 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6991 gas_assert (inst
.operands
[i
].isreg
);
6992 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6994 if (inst
.operands
[i
].preind
)
6998 inst
.error
= _("instruction does not accept preindexed addressing");
7001 inst
.instruction
|= PRE_INDEX
;
7002 if (inst
.operands
[i
].writeback
)
7003 inst
.instruction
|= WRITE_BACK
;
7006 else if (inst
.operands
[i
].postind
)
7008 gas_assert (inst
.operands
[i
].writeback
);
7010 inst
.instruction
|= WRITE_BACK
;
7012 else /* unindexed - only for coprocessor */
7014 inst
.error
= _("instruction does not accept unindexed addressing");
7018 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7019 && (((inst
.instruction
& 0x000f0000) >> 16)
7020 == ((inst
.instruction
& 0x0000f000) >> 12)))
7021 as_warn ((inst
.instruction
& LOAD_BIT
)
7022 ? _("destination register same as write-back base")
7023 : _("source register same as write-back base"));
7026 /* inst.operands[i] was set up by parse_address. Encode it into an
7027 ARM-format mode 2 load or store instruction. If is_t is true,
7028 reject forms that cannot be used with a T instruction (i.e. not
7031 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7033 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7035 encode_arm_addr_mode_common (i
, is_t
);
7037 if (inst
.operands
[i
].immisreg
)
7039 constraint ((inst
.operands
[i
].imm
== REG_PC
7040 || (is_pc
&& inst
.operands
[i
].writeback
)),
7042 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7043 inst
.instruction
|= inst
.operands
[i
].imm
;
7044 if (!inst
.operands
[i
].negative
)
7045 inst
.instruction
|= INDEX_UP
;
7046 if (inst
.operands
[i
].shifted
)
7048 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7049 inst
.instruction
|= SHIFT_ROR
<< 5;
7052 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7053 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7057 else /* immediate offset in inst.reloc */
7059 if (is_pc
&& !inst
.reloc
.pc_rel
)
7061 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7063 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7064 cannot use PC in addressing.
7065 PC cannot be used in writeback addressing, either. */
7066 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7069 /* Use of PC in str is deprecated for ARMv7. */
7070 if (warn_on_deprecated
7072 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7073 as_warn (_("use of PC in this instruction is deprecated"));
7076 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7078 /* Prefer + for zero encoded value. */
7079 if (!inst
.operands
[i
].negative
)
7080 inst
.instruction
|= INDEX_UP
;
7081 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7086 /* inst.operands[i] was set up by parse_address. Encode it into an
7087 ARM-format mode 3 load or store instruction. Reject forms that
7088 cannot be used with such instructions. If is_t is true, reject
7089 forms that cannot be used with a T instruction (i.e. not
7092 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7094 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7096 inst
.error
= _("instruction does not accept scaled register index");
7100 encode_arm_addr_mode_common (i
, is_t
);
7102 if (inst
.operands
[i
].immisreg
)
7104 constraint ((inst
.operands
[i
].imm
== REG_PC
7105 || inst
.operands
[i
].reg
== REG_PC
),
7107 inst
.instruction
|= inst
.operands
[i
].imm
;
7108 if (!inst
.operands
[i
].negative
)
7109 inst
.instruction
|= INDEX_UP
;
7111 else /* immediate offset in inst.reloc */
7113 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7114 && inst
.operands
[i
].writeback
),
7116 inst
.instruction
|= HWOFFSET_IMM
;
7117 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7119 /* Prefer + for zero encoded value. */
7120 if (!inst
.operands
[i
].negative
)
7121 inst
.instruction
|= INDEX_UP
;
7123 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7128 /* inst.operands[i] was set up by parse_address. Encode it into an
7129 ARM-format instruction. Reject all forms which cannot be encoded
7130 into a coprocessor load/store instruction. If wb_ok is false,
7131 reject use of writeback; if unind_ok is false, reject use of
7132 unindexed addressing. If reloc_override is not 0, use it instead
7133 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7134 (in which case it is preserved). */
7137 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7139 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7141 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7143 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7145 gas_assert (!inst
.operands
[i
].writeback
);
7148 inst
.error
= _("instruction does not support unindexed addressing");
7151 inst
.instruction
|= inst
.operands
[i
].imm
;
7152 inst
.instruction
|= INDEX_UP
;
7156 if (inst
.operands
[i
].preind
)
7157 inst
.instruction
|= PRE_INDEX
;
7159 if (inst
.operands
[i
].writeback
)
7161 if (inst
.operands
[i
].reg
== REG_PC
)
7163 inst
.error
= _("pc may not be used with write-back");
7168 inst
.error
= _("instruction does not support writeback");
7171 inst
.instruction
|= WRITE_BACK
;
7175 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7176 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7177 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7178 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7181 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7183 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7186 /* Prefer + for zero encoded value. */
7187 if (!inst
.operands
[i
].negative
)
7188 inst
.instruction
|= INDEX_UP
;
7193 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7194 Determine whether it can be performed with a move instruction; if
7195 it can, convert inst.instruction to that move instruction and
7196 return TRUE; if it can't, convert inst.instruction to a literal-pool
7197 load and return FALSE. If this is not a valid thing to do in the
7198 current context, set inst.error and return TRUE.
7200 inst.operands[i] describes the destination register. */
7203 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7208 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7212 if ((inst
.instruction
& tbit
) == 0)
7214 inst
.error
= _("invalid pseudo operation");
7217 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7219 inst
.error
= _("constant expression expected");
7222 if (inst
.reloc
.exp
.X_op
== O_constant
)
7226 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7228 /* This can be done with a mov(1) instruction. */
7229 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7230 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7236 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7239 /* This can be done with a mov instruction. */
7240 inst
.instruction
&= LITERAL_MASK
;
7241 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7242 inst
.instruction
|= value
& 0xfff;
7246 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7249 /* This can be done with a mvn instruction. */
7250 inst
.instruction
&= LITERAL_MASK
;
7251 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7252 inst
.instruction
|= value
& 0xfff;
7258 if (add_to_lit_pool () == FAIL
)
7260 inst
.error
= _("literal pool insertion failed");
7263 inst
.operands
[1].reg
= REG_PC
;
7264 inst
.operands
[1].isreg
= 1;
7265 inst
.operands
[1].preind
= 1;
7266 inst
.reloc
.pc_rel
= 1;
7267 inst
.reloc
.type
= (thumb_p
7268 ? BFD_RELOC_ARM_THUMB_OFFSET
7270 ? BFD_RELOC_ARM_HWLITERAL
7271 : BFD_RELOC_ARM_LITERAL
));
7275 /* Functions for instruction encoding, sorted by sub-architecture.
7276 First some generics; their names are taken from the conventional
7277 bit positions for register arguments in ARM format instructions. */
7287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7293 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7294 inst
.instruction
|= inst
.operands
[1].reg
;
7300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7301 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7307 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7308 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7314 unsigned Rn
= inst
.operands
[2].reg
;
7315 /* Enforce restrictions on SWP instruction. */
7316 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7318 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7319 _("Rn must not overlap other operands"));
7321 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7322 if (warn_on_deprecated
7323 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7324 as_warn (_("swp{b} use is deprecated for this architecture"));
7327 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7328 inst
.instruction
|= inst
.operands
[1].reg
;
7329 inst
.instruction
|= Rn
<< 16;
7335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7337 inst
.instruction
|= inst
.operands
[2].reg
;
7343 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7344 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7345 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7346 || inst
.reloc
.exp
.X_add_number
!= 0),
7348 inst
.instruction
|= inst
.operands
[0].reg
;
7349 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7350 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7356 inst
.instruction
|= inst
.operands
[0].imm
;
7362 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7363 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7366 /* ARM instructions, in alphabetical order by function name (except
7367 that wrapper functions appear immediately after the function they
7370 /* This is a pseudo-op of the form "adr rd, label" to be converted
7371 into a relative address of the form "add rd, pc, #label-.-8". */
7376 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7378 /* Frag hacking will turn this into a sub instruction if the offset turns
7379 out to be negative. */
7380 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7381 inst
.reloc
.pc_rel
= 1;
7382 inst
.reloc
.exp
.X_add_number
-= 8;
7385 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7386 into a relative address of the form:
7387 add rd, pc, #low(label-.-8)"
7388 add rd, rd, #high(label-.-8)" */
7393 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7395 /* Frag hacking will turn this into a sub instruction if the offset turns
7396 out to be negative. */
7397 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7398 inst
.reloc
.pc_rel
= 1;
7399 inst
.size
= INSN_SIZE
* 2;
7400 inst
.reloc
.exp
.X_add_number
-= 8;
7406 if (!inst
.operands
[1].present
)
7407 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7408 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7409 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7410 encode_arm_shifter_operand (2);
7416 if (inst
.operands
[0].present
)
7418 constraint ((inst
.instruction
& 0xf0) != 0x40
7419 && inst
.operands
[0].imm
> 0xf
7420 && inst
.operands
[0].imm
< 0x0,
7421 _("bad barrier type"));
7422 inst
.instruction
|= inst
.operands
[0].imm
;
7425 inst
.instruction
|= 0xf;
7431 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7432 constraint (msb
> 32, _("bit-field extends past end of register"));
7433 /* The instruction encoding stores the LSB and MSB,
7434 not the LSB and width. */
7435 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7436 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7437 inst
.instruction
|= (msb
- 1) << 16;
7445 /* #0 in second position is alternative syntax for bfc, which is
7446 the same instruction but with REG_PC in the Rm field. */
7447 if (!inst
.operands
[1].isreg
)
7448 inst
.operands
[1].reg
= REG_PC
;
7450 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7451 constraint (msb
> 32, _("bit-field extends past end of register"));
7452 /* The instruction encoding stores the LSB and MSB,
7453 not the LSB and width. */
7454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7455 inst
.instruction
|= inst
.operands
[1].reg
;
7456 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7457 inst
.instruction
|= (msb
- 1) << 16;
7463 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7464 _("bit-field extends past end of register"));
7465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7466 inst
.instruction
|= inst
.operands
[1].reg
;
7467 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7468 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7471 /* ARM V5 breakpoint instruction (argument parse)
7472 BKPT <16 bit unsigned immediate>
7473 Instruction is not conditional.
7474 The bit pattern given in insns[] has the COND_ALWAYS condition,
7475 and it is an error if the caller tried to override that. */
7480 /* Top 12 of 16 bits to bits 19:8. */
7481 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7483 /* Bottom 4 of 16 bits to bits 3:0. */
7484 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7488 encode_branch (int default_reloc
)
7490 if (inst
.operands
[0].hasreloc
)
7492 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7493 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7494 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7495 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7496 ? BFD_RELOC_ARM_PLT32
7497 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7500 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7501 inst
.reloc
.pc_rel
= 1;
7508 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7509 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7512 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7519 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7521 if (inst
.cond
== COND_ALWAYS
)
7522 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7524 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7528 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7531 /* ARM V5 branch-link-exchange instruction (argument parse)
7532 BLX <target_addr> ie BLX(1)
7533 BLX{<condition>} <Rm> ie BLX(2)
7534 Unfortunately, there are two different opcodes for this mnemonic.
7535 So, the insns[].value is not used, and the code here zaps values
7536 into inst.instruction.
7537 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7542 if (inst
.operands
[0].isreg
)
7544 /* Arg is a register; the opcode provided by insns[] is correct.
7545 It is not illegal to do "blx pc", just useless. */
7546 if (inst
.operands
[0].reg
== REG_PC
)
7547 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7549 inst
.instruction
|= inst
.operands
[0].reg
;
7553 /* Arg is an address; this instruction cannot be executed
7554 conditionally, and the opcode must be adjusted.
7555 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7556 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7557 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7558 inst
.instruction
= 0xfa000000;
7559 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7566 bfd_boolean want_reloc
;
7568 if (inst
.operands
[0].reg
== REG_PC
)
7569 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7571 inst
.instruction
|= inst
.operands
[0].reg
;
7572 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7573 it is for ARMv4t or earlier. */
7574 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7575 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7579 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7584 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7588 /* ARM v5TEJ. Jump to Jazelle code. */
7593 if (inst
.operands
[0].reg
== REG_PC
)
7594 as_tsktsk (_("use of r15 in bxj is not really useful"));
7596 inst
.instruction
|= inst
.operands
[0].reg
;
7599 /* Co-processor data operation:
7600 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7601 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7605 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7606 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7607 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7608 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7609 inst
.instruction
|= inst
.operands
[4].reg
;
7610 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7616 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7617 encode_arm_shifter_operand (1);
7620 /* Transfer between coprocessor and ARM registers.
7621 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7626 No special properties. */
7633 Rd
= inst
.operands
[2].reg
;
7636 if (inst
.instruction
== 0xee000010
7637 || inst
.instruction
== 0xfe000010)
7639 reject_bad_reg (Rd
);
7642 constraint (Rd
== REG_SP
, BAD_SP
);
7647 if (inst
.instruction
== 0xe000010)
7648 constraint (Rd
== REG_PC
, BAD_PC
);
7652 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7653 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7654 inst
.instruction
|= Rd
<< 12;
7655 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7656 inst
.instruction
|= inst
.operands
[4].reg
;
7657 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7660 /* Transfer between coprocessor register and pair of ARM registers.
7661 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7666 Two XScale instructions are special cases of these:
7668 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7669 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7671 Result unpredictable if Rd or Rn is R15. */
7678 Rd
= inst
.operands
[2].reg
;
7679 Rn
= inst
.operands
[3].reg
;
7683 reject_bad_reg (Rd
);
7684 reject_bad_reg (Rn
);
7688 constraint (Rd
== REG_PC
, BAD_PC
);
7689 constraint (Rn
== REG_PC
, BAD_PC
);
7692 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7693 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7694 inst
.instruction
|= Rd
<< 12;
7695 inst
.instruction
|= Rn
<< 16;
7696 inst
.instruction
|= inst
.operands
[4].reg
;
7702 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7703 if (inst
.operands
[1].present
)
7705 inst
.instruction
|= CPSI_MMOD
;
7706 inst
.instruction
|= inst
.operands
[1].imm
;
7713 inst
.instruction
|= inst
.operands
[0].imm
;
7719 unsigned Rd
, Rn
, Rm
;
7721 Rd
= inst
.operands
[0].reg
;
7722 Rn
= (inst
.operands
[1].present
7723 ? inst
.operands
[1].reg
: Rd
);
7724 Rm
= inst
.operands
[2].reg
;
7726 constraint ((Rd
== REG_PC
), BAD_PC
);
7727 constraint ((Rn
== REG_PC
), BAD_PC
);
7728 constraint ((Rm
== REG_PC
), BAD_PC
);
7730 inst
.instruction
|= Rd
<< 16;
7731 inst
.instruction
|= Rn
<< 0;
7732 inst
.instruction
|= Rm
<< 8;
7738 /* There is no IT instruction in ARM mode. We
7739 process it to do the validation as if in
7740 thumb mode, just in case the code gets
7741 assembled for thumb using the unified syntax. */
7746 set_it_insn_type (IT_INSN
);
7747 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7748 now_it
.cc
= inst
.operands
[0].imm
;
7755 int base_reg
= inst
.operands
[0].reg
;
7756 int range
= inst
.operands
[1].imm
;
7758 inst
.instruction
|= base_reg
<< 16;
7759 inst
.instruction
|= range
;
7761 if (inst
.operands
[1].writeback
)
7762 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7764 if (inst
.operands
[0].writeback
)
7766 inst
.instruction
|= WRITE_BACK
;
7767 /* Check for unpredictable uses of writeback. */
7768 if (inst
.instruction
& LOAD_BIT
)
7770 /* Not allowed in LDM type 2. */
7771 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7772 && ((range
& (1 << REG_PC
)) == 0))
7773 as_warn (_("writeback of base register is UNPREDICTABLE"));
7774 /* Only allowed if base reg not in list for other types. */
7775 else if (range
& (1 << base_reg
))
7776 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7780 /* Not allowed for type 2. */
7781 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7782 as_warn (_("writeback of base register is UNPREDICTABLE"));
7783 /* Only allowed if base reg not in list, or first in list. */
7784 else if ((range
& (1 << base_reg
))
7785 && (range
& ((1 << base_reg
) - 1)))
7786 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7791 /* ARMv5TE load-consecutive (argument parse)
7800 constraint (inst
.operands
[0].reg
% 2 != 0,
7801 _("first transfer register must be even"));
7802 constraint (inst
.operands
[1].present
7803 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7804 _("can only transfer two consecutive registers"));
7805 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7806 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7808 if (!inst
.operands
[1].present
)
7809 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7811 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7812 register and the first register written; we have to diagnose
7813 overlap between the base and the second register written here. */
7815 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7816 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7817 as_warn (_("base register written back, and overlaps "
7818 "second transfer register"));
7820 if (!(inst
.instruction
& V4_STR_BIT
))
7822 /* For an index-register load, the index register must not overlap the
7823 destination (even if not write-back). */
7824 if (inst
.operands
[2].immisreg
7825 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7826 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7827 as_warn (_("index register overlaps transfer register"));
7829 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7830 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7836 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7837 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7838 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7839 || inst
.operands
[1].negative
7840 /* This can arise if the programmer has written
7842 or if they have mistakenly used a register name as the last
7845 It is very difficult to distinguish between these two cases
7846 because "rX" might actually be a label. ie the register
7847 name has been occluded by a symbol of the same name. So we
7848 just generate a general 'bad addressing mode' type error
7849 message and leave it up to the programmer to discover the
7850 true cause and fix their mistake. */
7851 || (inst
.operands
[1].reg
== REG_PC
),
7854 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7855 || inst
.reloc
.exp
.X_add_number
!= 0,
7856 _("offset must be zero in ARM encoding"));
7858 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7860 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7861 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7862 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7868 constraint (inst
.operands
[0].reg
% 2 != 0,
7869 _("even register required"));
7870 constraint (inst
.operands
[1].present
7871 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7872 _("can only load two consecutive registers"));
7873 /* If op 1 were present and equal to PC, this function wouldn't
7874 have been called in the first place. */
7875 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7877 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7878 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7884 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7885 if (!inst
.operands
[1].isreg
)
7886 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7888 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7894 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7896 if (inst
.operands
[1].preind
)
7898 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7899 || inst
.reloc
.exp
.X_add_number
!= 0,
7900 _("this instruction requires a post-indexed address"));
7902 inst
.operands
[1].preind
= 0;
7903 inst
.operands
[1].postind
= 1;
7904 inst
.operands
[1].writeback
= 1;
7906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7907 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7910 /* Halfword and signed-byte load/store operations. */
7915 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7917 if (!inst
.operands
[1].isreg
)
7918 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7920 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7926 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7928 if (inst
.operands
[1].preind
)
7930 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7931 || inst
.reloc
.exp
.X_add_number
!= 0,
7932 _("this instruction requires a post-indexed address"));
7934 inst
.operands
[1].preind
= 0;
7935 inst
.operands
[1].postind
= 1;
7936 inst
.operands
[1].writeback
= 1;
7938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7939 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7942 /* Co-processor register load/store.
7943 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7947 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7948 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7949 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7955 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7956 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7957 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7958 && !(inst
.instruction
& 0x00400000))
7959 as_tsktsk (_("Rd and Rm should be different in mla"));
7961 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7962 inst
.instruction
|= inst
.operands
[1].reg
;
7963 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7964 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7971 encode_arm_shifter_operand (1);
7974 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7981 top
= (inst
.instruction
& 0x00400000) != 0;
7982 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7983 _(":lower16: not allowed this instruction"));
7984 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7985 _(":upper16: not allowed instruction"));
7986 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7987 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7989 imm
= inst
.reloc
.exp
.X_add_number
;
7990 /* The value is in two pieces: 0:11, 16:19. */
7991 inst
.instruction
|= (imm
& 0x00000fff);
7992 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7996 static void do_vfp_nsyn_opcode (const char *);
7999 do_vfp_nsyn_mrs (void)
8001 if (inst
.operands
[0].isvec
)
8003 if (inst
.operands
[1].reg
!= 1)
8004 first_error (_("operand 1 must be FPSCR"));
8005 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8006 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8007 do_vfp_nsyn_opcode ("fmstat");
8009 else if (inst
.operands
[1].isvec
)
8010 do_vfp_nsyn_opcode ("fmrx");
8018 do_vfp_nsyn_msr (void)
8020 if (inst
.operands
[0].isvec
)
8021 do_vfp_nsyn_opcode ("fmxr");
8031 unsigned Rt
= inst
.operands
[0].reg
;
8033 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
8035 inst
.error
= BAD_SP
;
8039 /* APSR_ sets isvec. All other refs to PC are illegal. */
8040 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
8042 inst
.error
= BAD_PC
;
8046 if (inst
.operands
[1].reg
!= 1)
8047 first_error (_("operand 1 must be FPSCR"));
8049 inst
.instruction
|= (Rt
<< 12);
8055 unsigned Rt
= inst
.operands
[1].reg
;
8058 reject_bad_reg (Rt
);
8059 else if (Rt
== REG_PC
)
8061 inst
.error
= BAD_PC
;
8065 if (inst
.operands
[0].reg
!= 1)
8066 first_error (_("operand 0 must be FPSCR"));
8068 inst
.instruction
|= (Rt
<< 12);
8076 if (do_vfp_nsyn_mrs () == SUCCESS
)
8079 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8082 if (inst
.operands
[1].isreg
)
8084 br
= inst
.operands
[1].reg
;
8085 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8086 as_bad (_("bad register for mrs"));
8090 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8091 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8093 _("'APSR', 'CPSR' or 'SPSR' expected"));
8094 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8097 inst
.instruction
|= br
;
8100 /* Two possible forms:
8101 "{C|S}PSR_<field>, Rm",
8102 "{C|S}PSR_f, #expression". */
8107 if (do_vfp_nsyn_msr () == SUCCESS
)
8110 inst
.instruction
|= inst
.operands
[0].imm
;
8111 if (inst
.operands
[1].isreg
)
8112 inst
.instruction
|= inst
.operands
[1].reg
;
8115 inst
.instruction
|= INST_IMMEDIATE
;
8116 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8117 inst
.reloc
.pc_rel
= 0;
8124 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8126 if (!inst
.operands
[2].present
)
8127 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8128 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8129 inst
.instruction
|= inst
.operands
[1].reg
;
8130 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8132 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8133 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8134 as_tsktsk (_("Rd and Rm should be different in mul"));
8137 /* Long Multiply Parser
8138 UMULL RdLo, RdHi, Rm, Rs
8139 SMULL RdLo, RdHi, Rm, Rs
8140 UMLAL RdLo, RdHi, Rm, Rs
8141 SMLAL RdLo, RdHi, Rm, Rs. */
8146 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8147 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8148 inst
.instruction
|= inst
.operands
[2].reg
;
8149 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8151 /* rdhi and rdlo must be different. */
8152 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8153 as_tsktsk (_("rdhi and rdlo must be different"));
8155 /* rdhi, rdlo and rm must all be different before armv6. */
8156 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8157 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8158 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8159 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8165 if (inst
.operands
[0].present
8166 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8168 /* Architectural NOP hints are CPSR sets with no bits selected. */
8169 inst
.instruction
&= 0xf0000000;
8170 inst
.instruction
|= 0x0320f000;
8171 if (inst
.operands
[0].present
)
8172 inst
.instruction
|= inst
.operands
[0].imm
;
8176 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8177 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8178 Condition defaults to COND_ALWAYS.
8179 Error if Rd, Rn or Rm are R15. */
8184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8185 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8186 inst
.instruction
|= inst
.operands
[2].reg
;
8187 if (inst
.operands
[3].present
)
8188 encode_arm_shift (3);
8191 /* ARM V6 PKHTB (Argument Parse). */
8196 if (!inst
.operands
[3].present
)
8198 /* If the shift specifier is omitted, turn the instruction
8199 into pkhbt rd, rm, rn. */
8200 inst
.instruction
&= 0xfff00010;
8201 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8202 inst
.instruction
|= inst
.operands
[1].reg
;
8203 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8207 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8208 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8209 inst
.instruction
|= inst
.operands
[2].reg
;
8210 encode_arm_shift (3);
8214 /* ARMv5TE: Preload-Cache
8215 MP Extensions: Preload for write
8219 Syntactically, like LDR with B=1, W=0, L=1. */
8224 constraint (!inst
.operands
[0].isreg
,
8225 _("'[' expected after PLD mnemonic"));
8226 constraint (inst
.operands
[0].postind
,
8227 _("post-indexed expression used in preload instruction"));
8228 constraint (inst
.operands
[0].writeback
,
8229 _("writeback used in preload instruction"));
8230 constraint (!inst
.operands
[0].preind
,
8231 _("unindexed addressing used in preload instruction"));
8232 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8235 /* ARMv7: PLI <addr_mode> */
8239 constraint (!inst
.operands
[0].isreg
,
8240 _("'[' expected after PLI mnemonic"));
8241 constraint (inst
.operands
[0].postind
,
8242 _("post-indexed expression used in preload instruction"));
8243 constraint (inst
.operands
[0].writeback
,
8244 _("writeback used in preload instruction"));
8245 constraint (!inst
.operands
[0].preind
,
8246 _("unindexed addressing used in preload instruction"));
8247 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8248 inst
.instruction
&= ~PRE_INDEX
;
8254 inst
.operands
[1] = inst
.operands
[0];
8255 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8256 inst
.operands
[0].isreg
= 1;
8257 inst
.operands
[0].writeback
= 1;
8258 inst
.operands
[0].reg
= REG_SP
;
8262 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8263 word at the specified address and the following word
8265 Unconditionally executed.
8266 Error if Rn is R15. */
8271 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8272 if (inst
.operands
[0].writeback
)
8273 inst
.instruction
|= WRITE_BACK
;
8276 /* ARM V6 ssat (argument parse). */
8281 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8282 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8283 inst
.instruction
|= inst
.operands
[2].reg
;
8285 if (inst
.operands
[3].present
)
8286 encode_arm_shift (3);
8289 /* ARM V6 usat (argument parse). */
8294 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8295 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8296 inst
.instruction
|= inst
.operands
[2].reg
;
8298 if (inst
.operands
[3].present
)
8299 encode_arm_shift (3);
8302 /* ARM V6 ssat16 (argument parse). */
8307 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8308 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8309 inst
.instruction
|= inst
.operands
[2].reg
;
8315 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8316 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8317 inst
.instruction
|= inst
.operands
[2].reg
;
8320 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8321 preserving the other bits.
8323 setend <endian_specifier>, where <endian_specifier> is either
8329 if (inst
.operands
[0].imm
)
8330 inst
.instruction
|= 0x200;
8336 unsigned int Rm
= (inst
.operands
[1].present
8337 ? inst
.operands
[1].reg
8338 : inst
.operands
[0].reg
);
8340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8341 inst
.instruction
|= Rm
;
8342 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8344 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8345 inst
.instruction
|= SHIFT_BY_REG
;
8346 /* PR 12854: Error on extraneous shifts. */
8347 constraint (inst
.operands
[2].shifted
,
8348 _("extraneous shift as part of operand to shift insn"));
8351 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8357 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8358 inst
.reloc
.pc_rel
= 0;
8364 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8365 inst
.reloc
.pc_rel
= 0;
8371 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8372 inst
.reloc
.pc_rel
= 0;
8375 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8376 SMLAxy{cond} Rd,Rm,Rs,Rn
8377 SMLAWy{cond} Rd,Rm,Rs,Rn
8378 Error if any register is R15. */
8383 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8384 inst
.instruction
|= inst
.operands
[1].reg
;
8385 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8386 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8389 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8390 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8391 Error if any register is R15.
8392 Warning if Rdlo == Rdhi. */
8397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8398 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8399 inst
.instruction
|= inst
.operands
[2].reg
;
8400 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8402 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8403 as_tsktsk (_("rdhi and rdlo must be different"));
8406 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8407 SMULxy{cond} Rd,Rm,Rs
8408 Error if any register is R15. */
8413 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8414 inst
.instruction
|= inst
.operands
[1].reg
;
8415 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8418 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8419 the same for both ARM and Thumb-2. */
8426 if (inst
.operands
[0].present
)
8428 reg
= inst
.operands
[0].reg
;
8429 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8434 inst
.instruction
|= reg
<< 16;
8435 inst
.instruction
|= inst
.operands
[1].imm
;
8436 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8437 inst
.instruction
|= WRITE_BACK
;
8440 /* ARM V6 strex (argument parse). */
8445 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8446 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8447 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8448 || inst
.operands
[2].negative
8449 /* See comment in do_ldrex(). */
8450 || (inst
.operands
[2].reg
== REG_PC
),
8453 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8454 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8456 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8457 || inst
.reloc
.exp
.X_add_number
!= 0,
8458 _("offset must be zero in ARM encoding"));
8460 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8461 inst
.instruction
|= inst
.operands
[1].reg
;
8462 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8463 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8469 constraint (inst
.operands
[1].reg
% 2 != 0,
8470 _("even register required"));
8471 constraint (inst
.operands
[2].present
8472 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8473 _("can only store two consecutive registers"));
8474 /* If op 2 were present and equal to PC, this function wouldn't
8475 have been called in the first place. */
8476 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8478 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8479 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8480 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8484 inst
.instruction
|= inst
.operands
[1].reg
;
8485 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8488 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8489 extends it to 32-bits, and adds the result to a value in another
8490 register. You can specify a rotation by 0, 8, 16, or 24 bits
8491 before extracting the 16-bit value.
8492 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8493 Condition defaults to COND_ALWAYS.
8494 Error if any register uses R15. */
8499 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8500 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8501 inst
.instruction
|= inst
.operands
[2].reg
;
8502 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8507 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8508 Condition defaults to COND_ALWAYS.
8509 Error if any register uses R15. */
8514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8515 inst
.instruction
|= inst
.operands
[1].reg
;
8516 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8519 /* VFP instructions. In a logical order: SP variant first, monad
8520 before dyad, arithmetic then move then load/store. */
8523 do_vfp_sp_monadic (void)
8525 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8526 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8530 do_vfp_sp_dyadic (void)
8532 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8533 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8534 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8538 do_vfp_sp_compare_z (void)
8540 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8544 do_vfp_dp_sp_cvt (void)
8546 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8547 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8551 do_vfp_sp_dp_cvt (void)
8553 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8554 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8558 do_vfp_reg_from_sp (void)
8560 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8561 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8565 do_vfp_reg2_from_sp2 (void)
8567 constraint (inst
.operands
[2].imm
!= 2,
8568 _("only two consecutive VFP SP registers allowed here"));
8569 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8570 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8571 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8575 do_vfp_sp_from_reg (void)
8577 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8578 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8582 do_vfp_sp2_from_reg2 (void)
8584 constraint (inst
.operands
[0].imm
!= 2,
8585 _("only two consecutive VFP SP registers allowed here"));
8586 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8587 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8588 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8592 do_vfp_sp_ldst (void)
8594 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8595 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8599 do_vfp_dp_ldst (void)
8601 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8602 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8607 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8609 if (inst
.operands
[0].writeback
)
8610 inst
.instruction
|= WRITE_BACK
;
8612 constraint (ldstm_type
!= VFP_LDSTMIA
,
8613 _("this addressing mode requires base-register writeback"));
8614 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8615 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8616 inst
.instruction
|= inst
.operands
[1].imm
;
8620 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8624 if (inst
.operands
[0].writeback
)
8625 inst
.instruction
|= WRITE_BACK
;
8627 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8628 _("this addressing mode requires base-register writeback"));
8630 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8631 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8633 count
= inst
.operands
[1].imm
<< 1;
8634 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8637 inst
.instruction
|= count
;
8641 do_vfp_sp_ldstmia (void)
8643 vfp_sp_ldstm (VFP_LDSTMIA
);
8647 do_vfp_sp_ldstmdb (void)
8649 vfp_sp_ldstm (VFP_LDSTMDB
);
8653 do_vfp_dp_ldstmia (void)
8655 vfp_dp_ldstm (VFP_LDSTMIA
);
8659 do_vfp_dp_ldstmdb (void)
8661 vfp_dp_ldstm (VFP_LDSTMDB
);
8665 do_vfp_xp_ldstmia (void)
8667 vfp_dp_ldstm (VFP_LDSTMIAX
);
8671 do_vfp_xp_ldstmdb (void)
8673 vfp_dp_ldstm (VFP_LDSTMDBX
);
8677 do_vfp_dp_rd_rm (void)
8679 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8680 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8684 do_vfp_dp_rn_rd (void)
8686 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8687 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8691 do_vfp_dp_rd_rn (void)
8693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8694 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8698 do_vfp_dp_rd_rn_rm (void)
8700 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8701 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8702 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8708 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8712 do_vfp_dp_rm_rd_rn (void)
8714 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8715 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8716 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8719 /* VFPv3 instructions. */
8721 do_vfp_sp_const (void)
8723 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8724 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8725 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8729 do_vfp_dp_const (void)
8731 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8732 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8733 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8737 vfp_conv (int srcsize
)
8739 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8740 inst
.instruction
|= (immbits
& 1) << 5;
8741 inst
.instruction
|= (immbits
>> 1);
8745 do_vfp_sp_conv_16 (void)
8747 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8752 do_vfp_dp_conv_16 (void)
8754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8759 do_vfp_sp_conv_32 (void)
8761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8766 do_vfp_dp_conv_32 (void)
8768 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8772 /* FPA instructions. Also in a logical order. */
8777 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8778 inst
.instruction
|= inst
.operands
[1].reg
;
8782 do_fpa_ldmstm (void)
8784 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8785 switch (inst
.operands
[1].imm
)
8787 case 1: inst
.instruction
|= CP_T_X
; break;
8788 case 2: inst
.instruction
|= CP_T_Y
; break;
8789 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8794 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8796 /* The instruction specified "ea" or "fd", so we can only accept
8797 [Rn]{!}. The instruction does not really support stacking or
8798 unstacking, so we have to emulate these by setting appropriate
8799 bits and offsets. */
8800 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8801 || inst
.reloc
.exp
.X_add_number
!= 0,
8802 _("this instruction does not support indexing"));
8804 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8805 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8807 if (!(inst
.instruction
& INDEX_UP
))
8808 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8810 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8812 inst
.operands
[2].preind
= 0;
8813 inst
.operands
[2].postind
= 1;
8817 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8820 /* iWMMXt instructions: strictly in alphabetical order. */
8823 do_iwmmxt_tandorc (void)
8825 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8829 do_iwmmxt_textrc (void)
8831 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8832 inst
.instruction
|= inst
.operands
[1].imm
;
8836 do_iwmmxt_textrm (void)
8838 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8839 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8840 inst
.instruction
|= inst
.operands
[2].imm
;
8844 do_iwmmxt_tinsr (void)
8846 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8847 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8848 inst
.instruction
|= inst
.operands
[2].imm
;
8852 do_iwmmxt_tmia (void)
8854 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8855 inst
.instruction
|= inst
.operands
[1].reg
;
8856 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8860 do_iwmmxt_waligni (void)
8862 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8863 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8864 inst
.instruction
|= inst
.operands
[2].reg
;
8865 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8869 do_iwmmxt_wmerge (void)
8871 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8872 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8873 inst
.instruction
|= inst
.operands
[2].reg
;
8874 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8878 do_iwmmxt_wmov (void)
8880 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8881 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8882 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8883 inst
.instruction
|= inst
.operands
[1].reg
;
8887 do_iwmmxt_wldstbh (void)
8890 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8892 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8894 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8895 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8899 do_iwmmxt_wldstw (void)
8901 /* RIWR_RIWC clears .isreg for a control register. */
8902 if (!inst
.operands
[0].isreg
)
8904 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8905 inst
.instruction
|= 0xf0000000;
8908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8909 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8913 do_iwmmxt_wldstd (void)
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8916 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8917 && inst
.operands
[1].immisreg
)
8919 inst
.instruction
&= ~0x1a000ff;
8920 inst
.instruction
|= (0xf << 28);
8921 if (inst
.operands
[1].preind
)
8922 inst
.instruction
|= PRE_INDEX
;
8923 if (!inst
.operands
[1].negative
)
8924 inst
.instruction
|= INDEX_UP
;
8925 if (inst
.operands
[1].writeback
)
8926 inst
.instruction
|= WRITE_BACK
;
8927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8928 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8929 inst
.instruction
|= inst
.operands
[1].imm
;
8932 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8936 do_iwmmxt_wshufh (void)
8938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8939 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8940 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8941 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8945 do_iwmmxt_wzero (void)
8947 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8948 inst
.instruction
|= inst
.operands
[0].reg
;
8949 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8950 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8954 do_iwmmxt_wrwrwr_or_imm5 (void)
8956 if (inst
.operands
[2].isreg
)
8959 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8960 _("immediate operand requires iWMMXt2"));
8962 if (inst
.operands
[2].imm
== 0)
8964 switch ((inst
.instruction
>> 20) & 0xf)
8970 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8971 inst
.operands
[2].imm
= 16;
8972 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8978 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8979 inst
.operands
[2].imm
= 32;
8980 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8987 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8989 wrn
= (inst
.instruction
>> 16) & 0xf;
8990 inst
.instruction
&= 0xff0fff0f;
8991 inst
.instruction
|= wrn
;
8992 /* Bail out here; the instruction is now assembled. */
8997 /* Map 32 -> 0, etc. */
8998 inst
.operands
[2].imm
&= 0x1f;
8999 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9003 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9004 operations first, then control, shift, and load/store. */
9006 /* Insns like "foo X,Y,Z". */
9009 do_mav_triple (void)
9011 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9012 inst
.instruction
|= inst
.operands
[1].reg
;
9013 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9016 /* Insns like "foo W,X,Y,Z".
9017 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9022 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9023 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9024 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9025 inst
.instruction
|= inst
.operands
[3].reg
;
9028 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9032 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9035 /* Maverick shift immediate instructions.
9036 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9037 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9042 int imm
= inst
.operands
[2].imm
;
9044 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9045 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9047 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9048 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9049 Bit 4 should be 0. */
9050 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9052 inst
.instruction
|= imm
;
9055 /* XScale instructions. Also sorted arithmetic before move. */
9057 /* Xscale multiply-accumulate (argument parse)
9060 MIAxycc acc0,Rm,Rs. */
9065 inst
.instruction
|= inst
.operands
[1].reg
;
9066 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9069 /* Xscale move-accumulator-register (argument parse)
9071 MARcc acc0,RdLo,RdHi. */
9076 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9077 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9080 /* Xscale move-register-accumulator (argument parse)
9082 MRAcc RdLo,RdHi,acc0. */
9087 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9089 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9092 /* Encoding functions relevant only to Thumb. */
9094 /* inst.operands[i] is a shifted-register operand; encode
9095 it into inst.instruction in the format used by Thumb32. */
9098 encode_thumb32_shifted_operand (int i
)
9100 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9101 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9103 constraint (inst
.operands
[i
].immisreg
,
9104 _("shift by register not allowed in thumb mode"));
9105 inst
.instruction
|= inst
.operands
[i
].reg
;
9106 if (shift
== SHIFT_RRX
)
9107 inst
.instruction
|= SHIFT_ROR
<< 4;
9110 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9111 _("expression too complex"));
9113 constraint (value
> 32
9114 || (value
== 32 && (shift
== SHIFT_LSL
9115 || shift
== SHIFT_ROR
)),
9116 _("shift expression is too large"));
9120 else if (value
== 32)
9123 inst
.instruction
|= shift
<< 4;
9124 inst
.instruction
|= (value
& 0x1c) << 10;
9125 inst
.instruction
|= (value
& 0x03) << 6;
9130 /* inst.operands[i] was set up by parse_address. Encode it into a
9131 Thumb32 format load or store instruction. Reject forms that cannot
9132 be used with such instructions. If is_t is true, reject forms that
9133 cannot be used with a T instruction; if is_d is true, reject forms
9134 that cannot be used with a D instruction. If it is a store insn,
9138 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9140 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9142 constraint (!inst
.operands
[i
].isreg
,
9143 _("Instruction does not support =N addresses"));
9145 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9146 if (inst
.operands
[i
].immisreg
)
9148 constraint (is_pc
, BAD_PC_ADDRESSING
);
9149 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9150 constraint (inst
.operands
[i
].negative
,
9151 _("Thumb does not support negative register indexing"));
9152 constraint (inst
.operands
[i
].postind
,
9153 _("Thumb does not support register post-indexing"));
9154 constraint (inst
.operands
[i
].writeback
,
9155 _("Thumb does not support register indexing with writeback"));
9156 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9157 _("Thumb supports only LSL in shifted register indexing"));
9159 inst
.instruction
|= inst
.operands
[i
].imm
;
9160 if (inst
.operands
[i
].shifted
)
9162 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9163 _("expression too complex"));
9164 constraint (inst
.reloc
.exp
.X_add_number
< 0
9165 || inst
.reloc
.exp
.X_add_number
> 3,
9166 _("shift out of range"));
9167 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9169 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9171 else if (inst
.operands
[i
].preind
)
9173 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9174 constraint (is_t
&& inst
.operands
[i
].writeback
,
9175 _("cannot use writeback with this instruction"));
9176 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9177 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9181 inst
.instruction
|= 0x01000000;
9182 if (inst
.operands
[i
].writeback
)
9183 inst
.instruction
|= 0x00200000;
9187 inst
.instruction
|= 0x00000c00;
9188 if (inst
.operands
[i
].writeback
)
9189 inst
.instruction
|= 0x00000100;
9191 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9193 else if (inst
.operands
[i
].postind
)
9195 gas_assert (inst
.operands
[i
].writeback
);
9196 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9197 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9200 inst
.instruction
|= 0x00200000;
9202 inst
.instruction
|= 0x00000900;
9203 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9205 else /* unindexed - only for coprocessor */
9206 inst
.error
= _("instruction does not accept unindexed addressing");
9209 /* Table of Thumb instructions which exist in both 16- and 32-bit
9210 encodings (the latter only in post-V6T2 cores). The index is the
9211 value used in the insns table below. When there is more than one
9212 possible 16-bit encoding for the instruction, this table always
9214 Also contains several pseudo-instructions used during relaxation. */
9215 #define T16_32_TAB \
9216 X(_adc, 4140, eb400000), \
9217 X(_adcs, 4140, eb500000), \
9218 X(_add, 1c00, eb000000), \
9219 X(_adds, 1c00, eb100000), \
9220 X(_addi, 0000, f1000000), \
9221 X(_addis, 0000, f1100000), \
9222 X(_add_pc,000f, f20f0000), \
9223 X(_add_sp,000d, f10d0000), \
9224 X(_adr, 000f, f20f0000), \
9225 X(_and, 4000, ea000000), \
9226 X(_ands, 4000, ea100000), \
9227 X(_asr, 1000, fa40f000), \
9228 X(_asrs, 1000, fa50f000), \
9229 X(_b, e000, f000b000), \
9230 X(_bcond, d000, f0008000), \
9231 X(_bic, 4380, ea200000), \
9232 X(_bics, 4380, ea300000), \
9233 X(_cmn, 42c0, eb100f00), \
9234 X(_cmp, 2800, ebb00f00), \
9235 X(_cpsie, b660, f3af8400), \
9236 X(_cpsid, b670, f3af8600), \
9237 X(_cpy, 4600, ea4f0000), \
9238 X(_dec_sp,80dd, f1ad0d00), \
9239 X(_eor, 4040, ea800000), \
9240 X(_eors, 4040, ea900000), \
9241 X(_inc_sp,00dd, f10d0d00), \
9242 X(_ldmia, c800, e8900000), \
9243 X(_ldr, 6800, f8500000), \
9244 X(_ldrb, 7800, f8100000), \
9245 X(_ldrh, 8800, f8300000), \
9246 X(_ldrsb, 5600, f9100000), \
9247 X(_ldrsh, 5e00, f9300000), \
9248 X(_ldr_pc,4800, f85f0000), \
9249 X(_ldr_pc2,4800, f85f0000), \
9250 X(_ldr_sp,9800, f85d0000), \
9251 X(_lsl, 0000, fa00f000), \
9252 X(_lsls, 0000, fa10f000), \
9253 X(_lsr, 0800, fa20f000), \
9254 X(_lsrs, 0800, fa30f000), \
9255 X(_mov, 2000, ea4f0000), \
9256 X(_movs, 2000, ea5f0000), \
9257 X(_mul, 4340, fb00f000), \
9258 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9259 X(_mvn, 43c0, ea6f0000), \
9260 X(_mvns, 43c0, ea7f0000), \
9261 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9262 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9263 X(_orr, 4300, ea400000), \
9264 X(_orrs, 4300, ea500000), \
9265 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9266 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9267 X(_rev, ba00, fa90f080), \
9268 X(_rev16, ba40, fa90f090), \
9269 X(_revsh, bac0, fa90f0b0), \
9270 X(_ror, 41c0, fa60f000), \
9271 X(_rors, 41c0, fa70f000), \
9272 X(_sbc, 4180, eb600000), \
9273 X(_sbcs, 4180, eb700000), \
9274 X(_stmia, c000, e8800000), \
9275 X(_str, 6000, f8400000), \
9276 X(_strb, 7000, f8000000), \
9277 X(_strh, 8000, f8200000), \
9278 X(_str_sp,9000, f84d0000), \
9279 X(_sub, 1e00, eba00000), \
9280 X(_subs, 1e00, ebb00000), \
9281 X(_subi, 8000, f1a00000), \
9282 X(_subis, 8000, f1b00000), \
9283 X(_sxtb, b240, fa4ff080), \
9284 X(_sxth, b200, fa0ff080), \
9285 X(_tst, 4200, ea100f00), \
9286 X(_uxtb, b2c0, fa5ff080), \
9287 X(_uxth, b280, fa1ff080), \
9288 X(_nop, bf00, f3af8000), \
9289 X(_yield, bf10, f3af8001), \
9290 X(_wfe, bf20, f3af8002), \
9291 X(_wfi, bf30, f3af8003), \
9292 X(_sev, bf40, f3af8004),
9294 /* To catch errors in encoding functions, the codes are all offset by
9295 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9296 as 16-bit instructions. */
9297 #define X(a,b,c) T_MNEM##a
9298 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9301 #define X(a,b,c) 0x##b
9302 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9303 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9306 #define X(a,b,c) 0x##c
9307 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9308 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9309 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9313 /* Thumb instruction encoders, in alphabetical order. */
9318 do_t_add_sub_w (void)
9322 Rd
= inst
.operands
[0].reg
;
9323 Rn
= inst
.operands
[1].reg
;
9325 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9326 is the SP-{plus,minus}-immediate form of the instruction. */
9328 constraint (Rd
== REG_PC
, BAD_PC
);
9330 reject_bad_reg (Rd
);
9332 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9333 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9336 /* Parse an add or subtract instruction. We get here with inst.instruction
9337 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9344 Rd
= inst
.operands
[0].reg
;
9345 Rs
= (inst
.operands
[1].present
9346 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9347 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9350 set_it_insn_type_last ();
9358 flags
= (inst
.instruction
== T_MNEM_adds
9359 || inst
.instruction
== T_MNEM_subs
);
9361 narrow
= !in_it_block ();
9363 narrow
= in_it_block ();
9364 if (!inst
.operands
[2].isreg
)
9368 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9370 add
= (inst
.instruction
== T_MNEM_add
9371 || inst
.instruction
== T_MNEM_adds
);
9373 if (inst
.size_req
!= 4)
9375 /* Attempt to use a narrow opcode, with relaxation if
9377 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9378 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9379 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9380 opcode
= T_MNEM_add_sp
;
9381 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9382 opcode
= T_MNEM_add_pc
;
9383 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9386 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9388 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9392 inst
.instruction
= THUMB_OP16(opcode
);
9393 inst
.instruction
|= (Rd
<< 4) | Rs
;
9394 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9395 if (inst
.size_req
!= 2)
9396 inst
.relax
= opcode
;
9399 constraint (inst
.size_req
== 2, BAD_HIREG
);
9401 if (inst
.size_req
== 4
9402 || (inst
.size_req
!= 2 && !opcode
))
9406 constraint (add
, BAD_PC
);
9407 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9408 _("only SUBS PC, LR, #const allowed"));
9409 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9410 _("expression too complex"));
9411 constraint (inst
.reloc
.exp
.X_add_number
< 0
9412 || inst
.reloc
.exp
.X_add_number
> 0xff,
9413 _("immediate value out of range"));
9414 inst
.instruction
= T2_SUBS_PC_LR
9415 | inst
.reloc
.exp
.X_add_number
;
9416 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9419 else if (Rs
== REG_PC
)
9421 /* Always use addw/subw. */
9422 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9423 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9427 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9428 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9431 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9433 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9435 inst
.instruction
|= Rd
<< 8;
9436 inst
.instruction
|= Rs
<< 16;
9441 Rn
= inst
.operands
[2].reg
;
9442 /* See if we can do this with a 16-bit instruction. */
9443 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9445 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9450 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9451 || inst
.instruction
== T_MNEM_add
)
9454 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9458 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9460 /* Thumb-1 cores (except v6-M) require at least one high
9461 register in a narrow non flag setting add. */
9462 if (Rd
> 7 || Rn
> 7
9463 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9464 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9471 inst
.instruction
= T_OPCODE_ADD_HI
;
9472 inst
.instruction
|= (Rd
& 8) << 4;
9473 inst
.instruction
|= (Rd
& 7);
9474 inst
.instruction
|= Rn
<< 3;
9480 constraint (Rd
== REG_PC
, BAD_PC
);
9481 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9482 constraint (Rs
== REG_PC
, BAD_PC
);
9483 reject_bad_reg (Rn
);
9485 /* If we get here, it can't be done in 16 bits. */
9486 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9487 _("shift must be constant"));
9488 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9489 inst
.instruction
|= Rd
<< 8;
9490 inst
.instruction
|= Rs
<< 16;
9491 encode_thumb32_shifted_operand (2);
9496 constraint (inst
.instruction
== T_MNEM_adds
9497 || inst
.instruction
== T_MNEM_subs
,
9500 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9502 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9503 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9506 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9508 inst
.instruction
|= (Rd
<< 4) | Rs
;
9509 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9513 Rn
= inst
.operands
[2].reg
;
9514 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9516 /* We now have Rd, Rs, and Rn set to registers. */
9517 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9519 /* Can't do this for SUB. */
9520 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9521 inst
.instruction
= T_OPCODE_ADD_HI
;
9522 inst
.instruction
|= (Rd
& 8) << 4;
9523 inst
.instruction
|= (Rd
& 7);
9525 inst
.instruction
|= Rn
<< 3;
9527 inst
.instruction
|= Rs
<< 3;
9529 constraint (1, _("dest must overlap one source register"));
9533 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9534 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9535 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9545 Rd
= inst
.operands
[0].reg
;
9546 reject_bad_reg (Rd
);
9548 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9550 /* Defer to section relaxation. */
9551 inst
.relax
= inst
.instruction
;
9552 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9553 inst
.instruction
|= Rd
<< 4;
9555 else if (unified_syntax
&& inst
.size_req
!= 2)
9557 /* Generate a 32-bit opcode. */
9558 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9559 inst
.instruction
|= Rd
<< 8;
9560 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9561 inst
.reloc
.pc_rel
= 1;
9565 /* Generate a 16-bit opcode. */
9566 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9567 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9568 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9569 inst
.reloc
.pc_rel
= 1;
9571 inst
.instruction
|= Rd
<< 4;
9575 /* Arithmetic instructions for which there is just one 16-bit
9576 instruction encoding, and it allows only two low registers.
9577 For maximal compatibility with ARM syntax, we allow three register
9578 operands even when Thumb-32 instructions are not available, as long
9579 as the first two are identical. For instance, both "sbc r0,r1" and
9580 "sbc r0,r0,r1" are allowed. */
9586 Rd
= inst
.operands
[0].reg
;
9587 Rs
= (inst
.operands
[1].present
9588 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9589 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9590 Rn
= inst
.operands
[2].reg
;
9592 reject_bad_reg (Rd
);
9593 reject_bad_reg (Rs
);
9594 if (inst
.operands
[2].isreg
)
9595 reject_bad_reg (Rn
);
9599 if (!inst
.operands
[2].isreg
)
9601 /* For an immediate, we always generate a 32-bit opcode;
9602 section relaxation will shrink it later if possible. */
9603 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9604 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9605 inst
.instruction
|= Rd
<< 8;
9606 inst
.instruction
|= Rs
<< 16;
9607 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9613 /* See if we can do this with a 16-bit instruction. */
9614 if (THUMB_SETS_FLAGS (inst
.instruction
))
9615 narrow
= !in_it_block ();
9617 narrow
= in_it_block ();
9619 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9621 if (inst
.operands
[2].shifted
)
9623 if (inst
.size_req
== 4)
9629 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9630 inst
.instruction
|= Rd
;
9631 inst
.instruction
|= Rn
<< 3;
9635 /* If we get here, it can't be done in 16 bits. */
9636 constraint (inst
.operands
[2].shifted
9637 && inst
.operands
[2].immisreg
,
9638 _("shift must be constant"));
9639 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9640 inst
.instruction
|= Rd
<< 8;
9641 inst
.instruction
|= Rs
<< 16;
9642 encode_thumb32_shifted_operand (2);
9647 /* On its face this is a lie - the instruction does set the
9648 flags. However, the only supported mnemonic in this mode
9650 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9652 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9653 _("unshifted register required"));
9654 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9655 constraint (Rd
!= Rs
,
9656 _("dest and source1 must be the same register"));
9658 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9659 inst
.instruction
|= Rd
;
9660 inst
.instruction
|= Rn
<< 3;
9664 /* Similarly, but for instructions where the arithmetic operation is
9665 commutative, so we can allow either of them to be different from
9666 the destination operand in a 16-bit instruction. For instance, all
9667 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9674 Rd
= inst
.operands
[0].reg
;
9675 Rs
= (inst
.operands
[1].present
9676 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9677 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9678 Rn
= inst
.operands
[2].reg
;
9680 reject_bad_reg (Rd
);
9681 reject_bad_reg (Rs
);
9682 if (inst
.operands
[2].isreg
)
9683 reject_bad_reg (Rn
);
9687 if (!inst
.operands
[2].isreg
)
9689 /* For an immediate, we always generate a 32-bit opcode;
9690 section relaxation will shrink it later if possible. */
9691 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9692 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9693 inst
.instruction
|= Rd
<< 8;
9694 inst
.instruction
|= Rs
<< 16;
9695 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9701 /* See if we can do this with a 16-bit instruction. */
9702 if (THUMB_SETS_FLAGS (inst
.instruction
))
9703 narrow
= !in_it_block ();
9705 narrow
= in_it_block ();
9707 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9709 if (inst
.operands
[2].shifted
)
9711 if (inst
.size_req
== 4)
9718 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9719 inst
.instruction
|= Rd
;
9720 inst
.instruction
|= Rn
<< 3;
9725 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9726 inst
.instruction
|= Rd
;
9727 inst
.instruction
|= Rs
<< 3;
9732 /* If we get here, it can't be done in 16 bits. */
9733 constraint (inst
.operands
[2].shifted
9734 && inst
.operands
[2].immisreg
,
9735 _("shift must be constant"));
9736 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9737 inst
.instruction
|= Rd
<< 8;
9738 inst
.instruction
|= Rs
<< 16;
9739 encode_thumb32_shifted_operand (2);
9744 /* On its face this is a lie - the instruction does set the
9745 flags. However, the only supported mnemonic in this mode
9747 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9749 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9750 _("unshifted register required"));
9751 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9753 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9754 inst
.instruction
|= Rd
;
9757 inst
.instruction
|= Rn
<< 3;
9759 inst
.instruction
|= Rs
<< 3;
9761 constraint (1, _("dest must overlap one source register"));
9768 if (inst
.operands
[0].present
)
9770 constraint ((inst
.instruction
& 0xf0) != 0x40
9771 && inst
.operands
[0].imm
> 0xf
9772 && inst
.operands
[0].imm
< 0x0,
9773 _("bad barrier type"));
9774 inst
.instruction
|= inst
.operands
[0].imm
;
9777 inst
.instruction
|= 0xf;
9784 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9785 constraint (msb
> 32, _("bit-field extends past end of register"));
9786 /* The instruction encoding stores the LSB and MSB,
9787 not the LSB and width. */
9788 Rd
= inst
.operands
[0].reg
;
9789 reject_bad_reg (Rd
);
9790 inst
.instruction
|= Rd
<< 8;
9791 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9792 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9793 inst
.instruction
|= msb
- 1;
9802 Rd
= inst
.operands
[0].reg
;
9803 reject_bad_reg (Rd
);
9805 /* #0 in second position is alternative syntax for bfc, which is
9806 the same instruction but with REG_PC in the Rm field. */
9807 if (!inst
.operands
[1].isreg
)
9811 Rn
= inst
.operands
[1].reg
;
9812 reject_bad_reg (Rn
);
9815 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9816 constraint (msb
> 32, _("bit-field extends past end of register"));
9817 /* The instruction encoding stores the LSB and MSB,
9818 not the LSB and width. */
9819 inst
.instruction
|= Rd
<< 8;
9820 inst
.instruction
|= Rn
<< 16;
9821 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9822 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9823 inst
.instruction
|= msb
- 1;
9831 Rd
= inst
.operands
[0].reg
;
9832 Rn
= inst
.operands
[1].reg
;
9834 reject_bad_reg (Rd
);
9835 reject_bad_reg (Rn
);
9837 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9838 _("bit-field extends past end of register"));
9839 inst
.instruction
|= Rd
<< 8;
9840 inst
.instruction
|= Rn
<< 16;
9841 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9842 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9843 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9846 /* ARM V5 Thumb BLX (argument parse)
9847 BLX <target_addr> which is BLX(1)
9848 BLX <Rm> which is BLX(2)
9849 Unfortunately, there are two different opcodes for this mnemonic.
9850 So, the insns[].value is not used, and the code here zaps values
9851 into inst.instruction.
9853 ??? How to take advantage of the additional two bits of displacement
9854 available in Thumb32 mode? Need new relocation? */
9859 set_it_insn_type_last ();
9861 if (inst
.operands
[0].isreg
)
9863 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9864 /* We have a register, so this is BLX(2). */
9865 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9869 /* No register. This must be BLX(1). */
9870 inst
.instruction
= 0xf000e800;
9871 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9883 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9887 /* Conditional branches inside IT blocks are encoded as unconditional
9894 if (cond
!= COND_ALWAYS
)
9895 opcode
= T_MNEM_bcond
;
9897 opcode
= inst
.instruction
;
9900 && (inst
.size_req
== 4
9901 || (inst
.size_req
!= 2
9902 && (inst
.operands
[0].hasreloc
9903 || inst
.reloc
.exp
.X_op
== O_constant
))))
9905 inst
.instruction
= THUMB_OP32(opcode
);
9906 if (cond
== COND_ALWAYS
)
9907 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9910 gas_assert (cond
!= 0xF);
9911 inst
.instruction
|= cond
<< 22;
9912 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9917 inst
.instruction
= THUMB_OP16(opcode
);
9918 if (cond
== COND_ALWAYS
)
9919 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9922 inst
.instruction
|= cond
<< 8;
9923 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9925 /* Allow section relaxation. */
9926 if (unified_syntax
&& inst
.size_req
!= 2)
9927 inst
.relax
= opcode
;
9929 inst
.reloc
.type
= reloc
;
9930 inst
.reloc
.pc_rel
= 1;
9936 constraint (inst
.cond
!= COND_ALWAYS
,
9937 _("instruction is always unconditional"));
9938 if (inst
.operands
[0].present
)
9940 constraint (inst
.operands
[0].imm
> 255,
9941 _("immediate value out of range"));
9942 inst
.instruction
|= inst
.operands
[0].imm
;
9943 set_it_insn_type (NEUTRAL_IT_INSN
);
9948 do_t_branch23 (void)
9950 set_it_insn_type_last ();
9951 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
9953 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9954 this file. We used to simply ignore the PLT reloc type here --
9955 the branch encoding is now needed to deal with TLSCALL relocs.
9956 So if we see a PLT reloc now, put it back to how it used to be to
9957 keep the preexisting behaviour. */
9958 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
9959 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9961 #if defined(OBJ_COFF)
9962 /* If the destination of the branch is a defined symbol which does not have
9963 the THUMB_FUNC attribute, then we must be calling a function which has
9964 the (interfacearm) attribute. We look for the Thumb entry point to that
9965 function and change the branch to refer to that function instead. */
9966 if ( inst
.reloc
.exp
.X_op
== O_symbol
9967 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9968 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9969 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9970 inst
.reloc
.exp
.X_add_symbol
=
9971 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9978 set_it_insn_type_last ();
9979 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9980 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9981 should cause the alignment to be checked once it is known. This is
9982 because BX PC only works if the instruction is word aligned. */
9990 set_it_insn_type_last ();
9991 Rm
= inst
.operands
[0].reg
;
9992 reject_bad_reg (Rm
);
9993 inst
.instruction
|= Rm
<< 16;
10002 Rd
= inst
.operands
[0].reg
;
10003 Rm
= inst
.operands
[1].reg
;
10005 reject_bad_reg (Rd
);
10006 reject_bad_reg (Rm
);
10008 inst
.instruction
|= Rd
<< 8;
10009 inst
.instruction
|= Rm
<< 16;
10010 inst
.instruction
|= Rm
;
10016 set_it_insn_type (OUTSIDE_IT_INSN
);
10017 inst
.instruction
|= inst
.operands
[0].imm
;
10023 set_it_insn_type (OUTSIDE_IT_INSN
);
10025 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10026 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10028 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10029 inst
.instruction
= 0xf3af8000;
10030 inst
.instruction
|= imod
<< 9;
10031 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10032 if (inst
.operands
[1].present
)
10033 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10037 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10038 && (inst
.operands
[0].imm
& 4),
10039 _("selected processor does not support 'A' form "
10040 "of this instruction"));
10041 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10042 _("Thumb does not support the 2-argument "
10043 "form of this instruction"));
10044 inst
.instruction
|= inst
.operands
[0].imm
;
10048 /* THUMB CPY instruction (argument parse). */
10053 if (inst
.size_req
== 4)
10055 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10056 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10057 inst
.instruction
|= inst
.operands
[1].reg
;
10061 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10062 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10063 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10070 set_it_insn_type (OUTSIDE_IT_INSN
);
10071 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10072 inst
.instruction
|= inst
.operands
[0].reg
;
10073 inst
.reloc
.pc_rel
= 1;
10074 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10080 inst
.instruction
|= inst
.operands
[0].imm
;
10086 unsigned Rd
, Rn
, Rm
;
10088 Rd
= inst
.operands
[0].reg
;
10089 Rn
= (inst
.operands
[1].present
10090 ? inst
.operands
[1].reg
: Rd
);
10091 Rm
= inst
.operands
[2].reg
;
10093 reject_bad_reg (Rd
);
10094 reject_bad_reg (Rn
);
10095 reject_bad_reg (Rm
);
10097 inst
.instruction
|= Rd
<< 8;
10098 inst
.instruction
|= Rn
<< 16;
10099 inst
.instruction
|= Rm
;
10105 if (unified_syntax
&& inst
.size_req
== 4)
10106 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10108 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10114 unsigned int cond
= inst
.operands
[0].imm
;
10116 set_it_insn_type (IT_INSN
);
10117 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10120 /* If the condition is a negative condition, invert the mask. */
10121 if ((cond
& 0x1) == 0x0)
10123 unsigned int mask
= inst
.instruction
& 0x000f;
10125 if ((mask
& 0x7) == 0)
10126 /* no conversion needed */;
10127 else if ((mask
& 0x3) == 0)
10129 else if ((mask
& 0x1) == 0)
10134 inst
.instruction
&= 0xfff0;
10135 inst
.instruction
|= mask
;
10138 inst
.instruction
|= cond
<< 4;
10141 /* Helper function used for both push/pop and ldm/stm. */
10143 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10147 load
= (inst
.instruction
& (1 << 20)) != 0;
10149 if (mask
& (1 << 13))
10150 inst
.error
= _("SP not allowed in register list");
10152 if ((mask
& (1 << base
)) != 0
10154 inst
.error
= _("having the base register in the register list when "
10155 "using write back is UNPREDICTABLE");
10159 if (mask
& (1 << 15))
10161 if (mask
& (1 << 14))
10162 inst
.error
= _("LR and PC should not both be in register list");
10164 set_it_insn_type_last ();
10169 if (mask
& (1 << 15))
10170 inst
.error
= _("PC not allowed in register list");
10173 if ((mask
& (mask
- 1)) == 0)
10175 /* Single register transfers implemented as str/ldr. */
10178 if (inst
.instruction
& (1 << 23))
10179 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10181 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10185 if (inst
.instruction
& (1 << 23))
10186 inst
.instruction
= 0x00800000; /* ia -> [base] */
10188 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10191 inst
.instruction
|= 0xf8400000;
10193 inst
.instruction
|= 0x00100000;
10195 mask
= ffs (mask
) - 1;
10198 else if (writeback
)
10199 inst
.instruction
|= WRITE_BACK
;
10201 inst
.instruction
|= mask
;
10202 inst
.instruction
|= base
<< 16;
10208 /* This really doesn't seem worth it. */
10209 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10210 _("expression too complex"));
10211 constraint (inst
.operands
[1].writeback
,
10212 _("Thumb load/store multiple does not support {reglist}^"));
10214 if (unified_syntax
)
10216 bfd_boolean narrow
;
10220 /* See if we can use a 16-bit instruction. */
10221 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10222 && inst
.size_req
!= 4
10223 && !(inst
.operands
[1].imm
& ~0xff))
10225 mask
= 1 << inst
.operands
[0].reg
;
10227 if (inst
.operands
[0].reg
<= 7)
10229 if (inst
.instruction
== T_MNEM_stmia
10230 ? inst
.operands
[0].writeback
10231 : (inst
.operands
[0].writeback
10232 == !(inst
.operands
[1].imm
& mask
)))
10234 if (inst
.instruction
== T_MNEM_stmia
10235 && (inst
.operands
[1].imm
& mask
)
10236 && (inst
.operands
[1].imm
& (mask
- 1)))
10237 as_warn (_("value stored for r%d is UNKNOWN"),
10238 inst
.operands
[0].reg
);
10240 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10241 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10242 inst
.instruction
|= inst
.operands
[1].imm
;
10245 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10247 /* This means 1 register in reg list one of 3 situations:
10248 1. Instruction is stmia, but without writeback.
10249 2. lmdia without writeback, but with Rn not in
10251 3. ldmia with writeback, but with Rn in reglist.
10252 Case 3 is UNPREDICTABLE behaviour, so we handle
10253 case 1 and 2 which can be converted into a 16-bit
10254 str or ldr. The SP cases are handled below. */
10255 unsigned long opcode
;
10256 /* First, record an error for Case 3. */
10257 if (inst
.operands
[1].imm
& mask
10258 && inst
.operands
[0].writeback
)
10260 _("having the base register in the register list when "
10261 "using write back is UNPREDICTABLE");
10263 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10265 inst
.instruction
= THUMB_OP16 (opcode
);
10266 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10267 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10271 else if (inst
.operands
[0] .reg
== REG_SP
)
10273 if (inst
.operands
[0].writeback
)
10276 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10277 ? T_MNEM_push
: T_MNEM_pop
);
10278 inst
.instruction
|= inst
.operands
[1].imm
;
10281 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10284 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10285 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10286 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10294 if (inst
.instruction
< 0xffff)
10295 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10297 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10298 inst
.operands
[0].writeback
);
10303 constraint (inst
.operands
[0].reg
> 7
10304 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10305 constraint (inst
.instruction
!= T_MNEM_ldmia
10306 && inst
.instruction
!= T_MNEM_stmia
,
10307 _("Thumb-2 instruction only valid in unified syntax"));
10308 if (inst
.instruction
== T_MNEM_stmia
)
10310 if (!inst
.operands
[0].writeback
)
10311 as_warn (_("this instruction will write back the base register"));
10312 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10313 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10314 as_warn (_("value stored for r%d is UNKNOWN"),
10315 inst
.operands
[0].reg
);
10319 if (!inst
.operands
[0].writeback
10320 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10321 as_warn (_("this instruction will write back the base register"));
10322 else if (inst
.operands
[0].writeback
10323 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10324 as_warn (_("this instruction will not write back the base register"));
10327 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10328 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10329 inst
.instruction
|= inst
.operands
[1].imm
;
10336 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10337 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10338 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10339 || inst
.operands
[1].negative
,
10342 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10344 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10345 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10346 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10352 if (!inst
.operands
[1].present
)
10354 constraint (inst
.operands
[0].reg
== REG_LR
,
10355 _("r14 not allowed as first register "
10356 "when second register is omitted"));
10357 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10359 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10362 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10363 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10364 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10370 unsigned long opcode
;
10373 if (inst
.operands
[0].isreg
10374 && !inst
.operands
[0].preind
10375 && inst
.operands
[0].reg
== REG_PC
)
10376 set_it_insn_type_last ();
10378 opcode
= inst
.instruction
;
10379 if (unified_syntax
)
10381 if (!inst
.operands
[1].isreg
)
10383 if (opcode
<= 0xffff)
10384 inst
.instruction
= THUMB_OP32 (opcode
);
10385 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10388 if (inst
.operands
[1].isreg
10389 && !inst
.operands
[1].writeback
10390 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10391 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10392 && opcode
<= 0xffff
10393 && inst
.size_req
!= 4)
10395 /* Insn may have a 16-bit form. */
10396 Rn
= inst
.operands
[1].reg
;
10397 if (inst
.operands
[1].immisreg
)
10399 inst
.instruction
= THUMB_OP16 (opcode
);
10401 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10403 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10404 reject_bad_reg (inst
.operands
[1].imm
);
10406 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10407 && opcode
!= T_MNEM_ldrsb
)
10408 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10409 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10416 if (inst
.reloc
.pc_rel
)
10417 opcode
= T_MNEM_ldr_pc2
;
10419 opcode
= T_MNEM_ldr_pc
;
10423 if (opcode
== T_MNEM_ldr
)
10424 opcode
= T_MNEM_ldr_sp
;
10426 opcode
= T_MNEM_str_sp
;
10428 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10432 inst
.instruction
= inst
.operands
[0].reg
;
10433 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10435 inst
.instruction
|= THUMB_OP16 (opcode
);
10436 if (inst
.size_req
== 2)
10437 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10439 inst
.relax
= opcode
;
10443 /* Definitely a 32-bit variant. */
10445 /* Warning for Erratum 752419. */
10446 if (opcode
== T_MNEM_ldr
10447 && inst
.operands
[0].reg
== REG_SP
10448 && inst
.operands
[1].writeback
== 1
10449 && !inst
.operands
[1].immisreg
)
10451 if (no_cpu_selected ()
10452 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10453 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10454 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10455 as_warn (_("This instruction may be unpredictable "
10456 "if executed on M-profile cores "
10457 "with interrupts enabled."));
10460 /* Do some validations regarding addressing modes. */
10461 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10462 && opcode
!= T_MNEM_str
)
10463 reject_bad_reg (inst
.operands
[1].imm
);
10465 inst
.instruction
= THUMB_OP32 (opcode
);
10466 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10467 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10471 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10473 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10475 /* Only [Rn,Rm] is acceptable. */
10476 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10477 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10478 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10479 || inst
.operands
[1].negative
,
10480 _("Thumb does not support this addressing mode"));
10481 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10485 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10486 if (!inst
.operands
[1].isreg
)
10487 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10490 constraint (!inst
.operands
[1].preind
10491 || inst
.operands
[1].shifted
10492 || inst
.operands
[1].writeback
,
10493 _("Thumb does not support this addressing mode"));
10494 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10496 constraint (inst
.instruction
& 0x0600,
10497 _("byte or halfword not valid for base register"));
10498 constraint (inst
.operands
[1].reg
== REG_PC
10499 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10500 _("r15 based store not allowed"));
10501 constraint (inst
.operands
[1].immisreg
,
10502 _("invalid base register for register offset"));
10504 if (inst
.operands
[1].reg
== REG_PC
)
10505 inst
.instruction
= T_OPCODE_LDR_PC
;
10506 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10507 inst
.instruction
= T_OPCODE_LDR_SP
;
10509 inst
.instruction
= T_OPCODE_STR_SP
;
10511 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10512 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10516 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10517 if (!inst
.operands
[1].immisreg
)
10519 /* Immediate offset. */
10520 inst
.instruction
|= inst
.operands
[0].reg
;
10521 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10522 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10526 /* Register offset. */
10527 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10528 constraint (inst
.operands
[1].negative
,
10529 _("Thumb does not support this addressing mode"));
10532 switch (inst
.instruction
)
10534 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10535 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10536 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10537 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10538 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10539 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10540 case 0x5600 /* ldrsb */:
10541 case 0x5e00 /* ldrsh */: break;
10545 inst
.instruction
|= inst
.operands
[0].reg
;
10546 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10547 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10553 if (!inst
.operands
[1].present
)
10555 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10556 constraint (inst
.operands
[0].reg
== REG_LR
,
10557 _("r14 not allowed here"));
10559 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10560 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10561 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10567 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10568 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10574 unsigned Rd
, Rn
, Rm
, Ra
;
10576 Rd
= inst
.operands
[0].reg
;
10577 Rn
= inst
.operands
[1].reg
;
10578 Rm
= inst
.operands
[2].reg
;
10579 Ra
= inst
.operands
[3].reg
;
10581 reject_bad_reg (Rd
);
10582 reject_bad_reg (Rn
);
10583 reject_bad_reg (Rm
);
10584 reject_bad_reg (Ra
);
10586 inst
.instruction
|= Rd
<< 8;
10587 inst
.instruction
|= Rn
<< 16;
10588 inst
.instruction
|= Rm
;
10589 inst
.instruction
|= Ra
<< 12;
10595 unsigned RdLo
, RdHi
, Rn
, Rm
;
10597 RdLo
= inst
.operands
[0].reg
;
10598 RdHi
= inst
.operands
[1].reg
;
10599 Rn
= inst
.operands
[2].reg
;
10600 Rm
= inst
.operands
[3].reg
;
10602 reject_bad_reg (RdLo
);
10603 reject_bad_reg (RdHi
);
10604 reject_bad_reg (Rn
);
10605 reject_bad_reg (Rm
);
10607 inst
.instruction
|= RdLo
<< 12;
10608 inst
.instruction
|= RdHi
<< 8;
10609 inst
.instruction
|= Rn
<< 16;
10610 inst
.instruction
|= Rm
;
10614 do_t_mov_cmp (void)
10618 Rn
= inst
.operands
[0].reg
;
10619 Rm
= inst
.operands
[1].reg
;
10622 set_it_insn_type_last ();
10624 if (unified_syntax
)
10626 int r0off
= (inst
.instruction
== T_MNEM_mov
10627 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10628 unsigned long opcode
;
10629 bfd_boolean narrow
;
10630 bfd_boolean low_regs
;
10632 low_regs
= (Rn
<= 7 && Rm
<= 7);
10633 opcode
= inst
.instruction
;
10634 if (in_it_block ())
10635 narrow
= opcode
!= T_MNEM_movs
;
10637 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10638 if (inst
.size_req
== 4
10639 || inst
.operands
[1].shifted
)
10642 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10643 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10644 && !inst
.operands
[1].shifted
10648 inst
.instruction
= T2_SUBS_PC_LR
;
10652 if (opcode
== T_MNEM_cmp
)
10654 constraint (Rn
== REG_PC
, BAD_PC
);
10657 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10659 warn_deprecated_sp (Rm
);
10660 /* R15 was documented as a valid choice for Rm in ARMv6,
10661 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10662 tools reject R15, so we do too. */
10663 constraint (Rm
== REG_PC
, BAD_PC
);
10666 reject_bad_reg (Rm
);
10668 else if (opcode
== T_MNEM_mov
10669 || opcode
== T_MNEM_movs
)
10671 if (inst
.operands
[1].isreg
)
10673 if (opcode
== T_MNEM_movs
)
10675 reject_bad_reg (Rn
);
10676 reject_bad_reg (Rm
);
10680 /* This is mov.n. */
10681 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10682 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10684 as_warn (_("Use of r%u as a source register is "
10685 "deprecated when r%u is the destination "
10686 "register."), Rm
, Rn
);
10691 /* This is mov.w. */
10692 constraint (Rn
== REG_PC
, BAD_PC
);
10693 constraint (Rm
== REG_PC
, BAD_PC
);
10694 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10698 reject_bad_reg (Rn
);
10701 if (!inst
.operands
[1].isreg
)
10703 /* Immediate operand. */
10704 if (!in_it_block () && opcode
== T_MNEM_mov
)
10706 if (low_regs
&& narrow
)
10708 inst
.instruction
= THUMB_OP16 (opcode
);
10709 inst
.instruction
|= Rn
<< 8;
10710 if (inst
.size_req
== 2)
10711 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10713 inst
.relax
= opcode
;
10717 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10718 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10719 inst
.instruction
|= Rn
<< r0off
;
10720 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10723 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10724 && (inst
.instruction
== T_MNEM_mov
10725 || inst
.instruction
== T_MNEM_movs
))
10727 /* Register shifts are encoded as separate shift instructions. */
10728 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10730 if (in_it_block ())
10735 if (inst
.size_req
== 4)
10738 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10744 switch (inst
.operands
[1].shift_kind
)
10747 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10750 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10753 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10756 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10762 inst
.instruction
= opcode
;
10765 inst
.instruction
|= Rn
;
10766 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10771 inst
.instruction
|= CONDS_BIT
;
10773 inst
.instruction
|= Rn
<< 8;
10774 inst
.instruction
|= Rm
<< 16;
10775 inst
.instruction
|= inst
.operands
[1].imm
;
10780 /* Some mov with immediate shift have narrow variants.
10781 Register shifts are handled above. */
10782 if (low_regs
&& inst
.operands
[1].shifted
10783 && (inst
.instruction
== T_MNEM_mov
10784 || inst
.instruction
== T_MNEM_movs
))
10786 if (in_it_block ())
10787 narrow
= (inst
.instruction
== T_MNEM_mov
);
10789 narrow
= (inst
.instruction
== T_MNEM_movs
);
10794 switch (inst
.operands
[1].shift_kind
)
10796 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10797 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10798 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10799 default: narrow
= FALSE
; break;
10805 inst
.instruction
|= Rn
;
10806 inst
.instruction
|= Rm
<< 3;
10807 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10811 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10812 inst
.instruction
|= Rn
<< r0off
;
10813 encode_thumb32_shifted_operand (1);
10817 switch (inst
.instruction
)
10820 inst
.instruction
= T_OPCODE_MOV_HR
;
10821 inst
.instruction
|= (Rn
& 0x8) << 4;
10822 inst
.instruction
|= (Rn
& 0x7);
10823 inst
.instruction
|= Rm
<< 3;
10827 /* We know we have low registers at this point.
10828 Generate LSLS Rd, Rs, #0. */
10829 inst
.instruction
= T_OPCODE_LSL_I
;
10830 inst
.instruction
|= Rn
;
10831 inst
.instruction
|= Rm
<< 3;
10837 inst
.instruction
= T_OPCODE_CMP_LR
;
10838 inst
.instruction
|= Rn
;
10839 inst
.instruction
|= Rm
<< 3;
10843 inst
.instruction
= T_OPCODE_CMP_HR
;
10844 inst
.instruction
|= (Rn
& 0x8) << 4;
10845 inst
.instruction
|= (Rn
& 0x7);
10846 inst
.instruction
|= Rm
<< 3;
10853 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10855 /* PR 10443: Do not silently ignore shifted operands. */
10856 constraint (inst
.operands
[1].shifted
,
10857 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10859 if (inst
.operands
[1].isreg
)
10861 if (Rn
< 8 && Rm
< 8)
10863 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10864 since a MOV instruction produces unpredictable results. */
10865 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10866 inst
.instruction
= T_OPCODE_ADD_I3
;
10868 inst
.instruction
= T_OPCODE_CMP_LR
;
10870 inst
.instruction
|= Rn
;
10871 inst
.instruction
|= Rm
<< 3;
10875 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10876 inst
.instruction
= T_OPCODE_MOV_HR
;
10878 inst
.instruction
= T_OPCODE_CMP_HR
;
10884 constraint (Rn
> 7,
10885 _("only lo regs allowed with immediate"));
10886 inst
.instruction
|= Rn
<< 8;
10887 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10898 top
= (inst
.instruction
& 0x00800000) != 0;
10899 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10901 constraint (top
, _(":lower16: not allowed this instruction"));
10902 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10904 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10906 constraint (!top
, _(":upper16: not allowed this instruction"));
10907 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10910 Rd
= inst
.operands
[0].reg
;
10911 reject_bad_reg (Rd
);
10913 inst
.instruction
|= Rd
<< 8;
10914 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10916 imm
= inst
.reloc
.exp
.X_add_number
;
10917 inst
.instruction
|= (imm
& 0xf000) << 4;
10918 inst
.instruction
|= (imm
& 0x0800) << 15;
10919 inst
.instruction
|= (imm
& 0x0700) << 4;
10920 inst
.instruction
|= (imm
& 0x00ff);
10925 do_t_mvn_tst (void)
10929 Rn
= inst
.operands
[0].reg
;
10930 Rm
= inst
.operands
[1].reg
;
10932 if (inst
.instruction
== T_MNEM_cmp
10933 || inst
.instruction
== T_MNEM_cmn
)
10934 constraint (Rn
== REG_PC
, BAD_PC
);
10936 reject_bad_reg (Rn
);
10937 reject_bad_reg (Rm
);
10939 if (unified_syntax
)
10941 int r0off
= (inst
.instruction
== T_MNEM_mvn
10942 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10943 bfd_boolean narrow
;
10945 if (inst
.size_req
== 4
10946 || inst
.instruction
> 0xffff
10947 || inst
.operands
[1].shifted
10948 || Rn
> 7 || Rm
> 7)
10950 else if (inst
.instruction
== T_MNEM_cmn
)
10952 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10953 narrow
= !in_it_block ();
10955 narrow
= in_it_block ();
10957 if (!inst
.operands
[1].isreg
)
10959 /* For an immediate, we always generate a 32-bit opcode;
10960 section relaxation will shrink it later if possible. */
10961 if (inst
.instruction
< 0xffff)
10962 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10963 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10964 inst
.instruction
|= Rn
<< r0off
;
10965 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10969 /* See if we can do this with a 16-bit instruction. */
10972 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10973 inst
.instruction
|= Rn
;
10974 inst
.instruction
|= Rm
<< 3;
10978 constraint (inst
.operands
[1].shifted
10979 && inst
.operands
[1].immisreg
,
10980 _("shift must be constant"));
10981 if (inst
.instruction
< 0xffff)
10982 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10983 inst
.instruction
|= Rn
<< r0off
;
10984 encode_thumb32_shifted_operand (1);
10990 constraint (inst
.instruction
> 0xffff
10991 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10992 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10993 _("unshifted register required"));
10994 constraint (Rn
> 7 || Rm
> 7,
10997 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10998 inst
.instruction
|= Rn
;
10999 inst
.instruction
|= Rm
<< 3;
11008 if (do_vfp_nsyn_mrs () == SUCCESS
)
11011 Rd
= inst
.operands
[0].reg
;
11012 reject_bad_reg (Rd
);
11013 inst
.instruction
|= Rd
<< 8;
11015 if (inst
.operands
[1].isreg
)
11017 unsigned br
= inst
.operands
[1].reg
;
11018 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11019 as_bad (_("bad register for mrs"));
11021 inst
.instruction
|= br
& (0xf << 16);
11022 inst
.instruction
|= (br
& 0x300) >> 4;
11023 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11027 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11029 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11030 constraint (flags
!= 0, _("selected processor does not support "
11031 "requested special purpose register"));
11033 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11035 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11036 _("'APSR', 'CPSR' or 'SPSR' expected"));
11038 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11039 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11040 inst
.instruction
|= 0xf0000;
11050 if (do_vfp_nsyn_msr () == SUCCESS
)
11053 constraint (!inst
.operands
[1].isreg
,
11054 _("Thumb encoding does not support an immediate here"));
11056 if (inst
.operands
[0].isreg
)
11057 flags
= (int)(inst
.operands
[0].reg
);
11059 flags
= inst
.operands
[0].imm
;
11061 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11063 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11065 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11066 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11067 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11069 _("selected processor does not support requested special "
11070 "purpose register"));
11073 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11074 "requested special purpose register"));
11076 Rn
= inst
.operands
[1].reg
;
11077 reject_bad_reg (Rn
);
11079 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11080 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11081 inst
.instruction
|= (flags
& 0x300) >> 4;
11082 inst
.instruction
|= (flags
& 0xff);
11083 inst
.instruction
|= Rn
<< 16;
11089 bfd_boolean narrow
;
11090 unsigned Rd
, Rn
, Rm
;
11092 if (!inst
.operands
[2].present
)
11093 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11095 Rd
= inst
.operands
[0].reg
;
11096 Rn
= inst
.operands
[1].reg
;
11097 Rm
= inst
.operands
[2].reg
;
11099 if (unified_syntax
)
11101 if (inst
.size_req
== 4
11107 else if (inst
.instruction
== T_MNEM_muls
)
11108 narrow
= !in_it_block ();
11110 narrow
= in_it_block ();
11114 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11115 constraint (Rn
> 7 || Rm
> 7,
11122 /* 16-bit MULS/Conditional MUL. */
11123 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11124 inst
.instruction
|= Rd
;
11127 inst
.instruction
|= Rm
<< 3;
11129 inst
.instruction
|= Rn
<< 3;
11131 constraint (1, _("dest must overlap one source register"));
11135 constraint (inst
.instruction
!= T_MNEM_mul
,
11136 _("Thumb-2 MUL must not set flags"));
11138 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11139 inst
.instruction
|= Rd
<< 8;
11140 inst
.instruction
|= Rn
<< 16;
11141 inst
.instruction
|= Rm
<< 0;
11143 reject_bad_reg (Rd
);
11144 reject_bad_reg (Rn
);
11145 reject_bad_reg (Rm
);
11152 unsigned RdLo
, RdHi
, Rn
, Rm
;
11154 RdLo
= inst
.operands
[0].reg
;
11155 RdHi
= inst
.operands
[1].reg
;
11156 Rn
= inst
.operands
[2].reg
;
11157 Rm
= inst
.operands
[3].reg
;
11159 reject_bad_reg (RdLo
);
11160 reject_bad_reg (RdHi
);
11161 reject_bad_reg (Rn
);
11162 reject_bad_reg (Rm
);
11164 inst
.instruction
|= RdLo
<< 12;
11165 inst
.instruction
|= RdHi
<< 8;
11166 inst
.instruction
|= Rn
<< 16;
11167 inst
.instruction
|= Rm
;
11170 as_tsktsk (_("rdhi and rdlo must be different"));
11176 set_it_insn_type (NEUTRAL_IT_INSN
);
11178 if (unified_syntax
)
11180 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11182 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11183 inst
.instruction
|= inst
.operands
[0].imm
;
11187 /* PR9722: Check for Thumb2 availability before
11188 generating a thumb2 nop instruction. */
11189 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11191 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11192 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11195 inst
.instruction
= 0x46c0;
11200 constraint (inst
.operands
[0].present
,
11201 _("Thumb does not support NOP with hints"));
11202 inst
.instruction
= 0x46c0;
11209 if (unified_syntax
)
11211 bfd_boolean narrow
;
11213 if (THUMB_SETS_FLAGS (inst
.instruction
))
11214 narrow
= !in_it_block ();
11216 narrow
= in_it_block ();
11217 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11219 if (inst
.size_req
== 4)
11224 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11225 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11226 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11230 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11231 inst
.instruction
|= inst
.operands
[0].reg
;
11232 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11237 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11239 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11241 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11242 inst
.instruction
|= inst
.operands
[0].reg
;
11243 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11252 Rd
= inst
.operands
[0].reg
;
11253 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11255 reject_bad_reg (Rd
);
11256 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11257 reject_bad_reg (Rn
);
11259 inst
.instruction
|= Rd
<< 8;
11260 inst
.instruction
|= Rn
<< 16;
11262 if (!inst
.operands
[2].isreg
)
11264 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11265 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11271 Rm
= inst
.operands
[2].reg
;
11272 reject_bad_reg (Rm
);
11274 constraint (inst
.operands
[2].shifted
11275 && inst
.operands
[2].immisreg
,
11276 _("shift must be constant"));
11277 encode_thumb32_shifted_operand (2);
11284 unsigned Rd
, Rn
, Rm
;
11286 Rd
= inst
.operands
[0].reg
;
11287 Rn
= inst
.operands
[1].reg
;
11288 Rm
= inst
.operands
[2].reg
;
11290 reject_bad_reg (Rd
);
11291 reject_bad_reg (Rn
);
11292 reject_bad_reg (Rm
);
11294 inst
.instruction
|= Rd
<< 8;
11295 inst
.instruction
|= Rn
<< 16;
11296 inst
.instruction
|= Rm
;
11297 if (inst
.operands
[3].present
)
11299 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11300 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11301 _("expression too complex"));
11302 inst
.instruction
|= (val
& 0x1c) << 10;
11303 inst
.instruction
|= (val
& 0x03) << 6;
11310 if (!inst
.operands
[3].present
)
11314 inst
.instruction
&= ~0x00000020;
11316 /* PR 10168. Swap the Rm and Rn registers. */
11317 Rtmp
= inst
.operands
[1].reg
;
11318 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11319 inst
.operands
[2].reg
= Rtmp
;
11327 if (inst
.operands
[0].immisreg
)
11328 reject_bad_reg (inst
.operands
[0].imm
);
11330 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11334 do_t_push_pop (void)
11338 constraint (inst
.operands
[0].writeback
,
11339 _("push/pop do not support {reglist}^"));
11340 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11341 _("expression too complex"));
11343 mask
= inst
.operands
[0].imm
;
11344 if ((mask
& ~0xff) == 0)
11345 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11346 else if ((inst
.instruction
== T_MNEM_push
11347 && (mask
& ~0xff) == 1 << REG_LR
)
11348 || (inst
.instruction
== T_MNEM_pop
11349 && (mask
& ~0xff) == 1 << REG_PC
))
11351 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11352 inst
.instruction
|= THUMB_PP_PC_LR
;
11353 inst
.instruction
|= mask
& 0xff;
11355 else if (unified_syntax
)
11357 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11358 encode_thumb2_ldmstm (13, mask
, TRUE
);
11362 inst
.error
= _("invalid register list to push/pop instruction");
11372 Rd
= inst
.operands
[0].reg
;
11373 Rm
= inst
.operands
[1].reg
;
11375 reject_bad_reg (Rd
);
11376 reject_bad_reg (Rm
);
11378 inst
.instruction
|= Rd
<< 8;
11379 inst
.instruction
|= Rm
<< 16;
11380 inst
.instruction
|= Rm
;
11388 Rd
= inst
.operands
[0].reg
;
11389 Rm
= inst
.operands
[1].reg
;
11391 reject_bad_reg (Rd
);
11392 reject_bad_reg (Rm
);
11394 if (Rd
<= 7 && Rm
<= 7
11395 && inst
.size_req
!= 4)
11397 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11398 inst
.instruction
|= Rd
;
11399 inst
.instruction
|= Rm
<< 3;
11401 else if (unified_syntax
)
11403 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11404 inst
.instruction
|= Rd
<< 8;
11405 inst
.instruction
|= Rm
<< 16;
11406 inst
.instruction
|= Rm
;
11409 inst
.error
= BAD_HIREG
;
11417 Rd
= inst
.operands
[0].reg
;
11418 Rm
= inst
.operands
[1].reg
;
11420 reject_bad_reg (Rd
);
11421 reject_bad_reg (Rm
);
11423 inst
.instruction
|= Rd
<< 8;
11424 inst
.instruction
|= Rm
;
11432 Rd
= inst
.operands
[0].reg
;
11433 Rs
= (inst
.operands
[1].present
11434 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11435 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11437 reject_bad_reg (Rd
);
11438 reject_bad_reg (Rs
);
11439 if (inst
.operands
[2].isreg
)
11440 reject_bad_reg (inst
.operands
[2].reg
);
11442 inst
.instruction
|= Rd
<< 8;
11443 inst
.instruction
|= Rs
<< 16;
11444 if (!inst
.operands
[2].isreg
)
11446 bfd_boolean narrow
;
11448 if ((inst
.instruction
& 0x00100000) != 0)
11449 narrow
= !in_it_block ();
11451 narrow
= in_it_block ();
11453 if (Rd
> 7 || Rs
> 7)
11456 if (inst
.size_req
== 4 || !unified_syntax
)
11459 if (inst
.reloc
.exp
.X_op
!= O_constant
11460 || inst
.reloc
.exp
.X_add_number
!= 0)
11463 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11464 relaxation, but it doesn't seem worth the hassle. */
11467 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11468 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11469 inst
.instruction
|= Rs
<< 3;
11470 inst
.instruction
|= Rd
;
11474 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11475 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11479 encode_thumb32_shifted_operand (2);
11485 set_it_insn_type (OUTSIDE_IT_INSN
);
11486 if (inst
.operands
[0].imm
)
11487 inst
.instruction
|= 0x8;
11493 if (!inst
.operands
[1].present
)
11494 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11496 if (unified_syntax
)
11498 bfd_boolean narrow
;
11501 switch (inst
.instruction
)
11504 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11506 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11508 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11510 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11514 if (THUMB_SETS_FLAGS (inst
.instruction
))
11515 narrow
= !in_it_block ();
11517 narrow
= in_it_block ();
11518 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11520 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11522 if (inst
.operands
[2].isreg
11523 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11524 || inst
.operands
[2].reg
> 7))
11526 if (inst
.size_req
== 4)
11529 reject_bad_reg (inst
.operands
[0].reg
);
11530 reject_bad_reg (inst
.operands
[1].reg
);
11534 if (inst
.operands
[2].isreg
)
11536 reject_bad_reg (inst
.operands
[2].reg
);
11537 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11538 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11539 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11540 inst
.instruction
|= inst
.operands
[2].reg
;
11542 /* PR 12854: Error on extraneous shifts. */
11543 constraint (inst
.operands
[2].shifted
,
11544 _("extraneous shift as part of operand to shift insn"));
11548 inst
.operands
[1].shifted
= 1;
11549 inst
.operands
[1].shift_kind
= shift_kind
;
11550 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11551 ? T_MNEM_movs
: T_MNEM_mov
);
11552 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11553 encode_thumb32_shifted_operand (1);
11554 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11555 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11560 if (inst
.operands
[2].isreg
)
11562 switch (shift_kind
)
11564 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11565 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11566 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11567 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11571 inst
.instruction
|= inst
.operands
[0].reg
;
11572 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11574 /* PR 12854: Error on extraneous shifts. */
11575 constraint (inst
.operands
[2].shifted
,
11576 _("extraneous shift as part of operand to shift insn"));
11580 switch (shift_kind
)
11582 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11583 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11584 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11587 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11588 inst
.instruction
|= inst
.operands
[0].reg
;
11589 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11595 constraint (inst
.operands
[0].reg
> 7
11596 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11597 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11599 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11601 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11602 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11603 _("source1 and dest must be same register"));
11605 switch (inst
.instruction
)
11607 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11608 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11609 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11610 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11614 inst
.instruction
|= inst
.operands
[0].reg
;
11615 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11617 /* PR 12854: Error on extraneous shifts. */
11618 constraint (inst
.operands
[2].shifted
,
11619 _("extraneous shift as part of operand to shift insn"));
11623 switch (inst
.instruction
)
11625 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11626 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11627 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11628 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11631 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11632 inst
.instruction
|= inst
.operands
[0].reg
;
11633 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11641 unsigned Rd
, Rn
, Rm
;
11643 Rd
= inst
.operands
[0].reg
;
11644 Rn
= inst
.operands
[1].reg
;
11645 Rm
= inst
.operands
[2].reg
;
11647 reject_bad_reg (Rd
);
11648 reject_bad_reg (Rn
);
11649 reject_bad_reg (Rm
);
11651 inst
.instruction
|= Rd
<< 8;
11652 inst
.instruction
|= Rn
<< 16;
11653 inst
.instruction
|= Rm
;
11659 unsigned Rd
, Rn
, Rm
;
11661 Rd
= inst
.operands
[0].reg
;
11662 Rm
= inst
.operands
[1].reg
;
11663 Rn
= inst
.operands
[2].reg
;
11665 reject_bad_reg (Rd
);
11666 reject_bad_reg (Rn
);
11667 reject_bad_reg (Rm
);
11669 inst
.instruction
|= Rd
<< 8;
11670 inst
.instruction
|= Rn
<< 16;
11671 inst
.instruction
|= Rm
;
11677 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11678 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11679 _("SMC is not permitted on this architecture"));
11680 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11681 _("expression too complex"));
11682 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11683 inst
.instruction
|= (value
& 0xf000) >> 12;
11684 inst
.instruction
|= (value
& 0x0ff0);
11685 inst
.instruction
|= (value
& 0x000f) << 16;
11691 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11693 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11694 inst
.instruction
|= (value
& 0x0fff);
11695 inst
.instruction
|= (value
& 0xf000) << 4;
11699 do_t_ssat_usat (int bias
)
11703 Rd
= inst
.operands
[0].reg
;
11704 Rn
= inst
.operands
[2].reg
;
11706 reject_bad_reg (Rd
);
11707 reject_bad_reg (Rn
);
11709 inst
.instruction
|= Rd
<< 8;
11710 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11711 inst
.instruction
|= Rn
<< 16;
11713 if (inst
.operands
[3].present
)
11715 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11717 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11719 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11720 _("expression too complex"));
11722 if (shift_amount
!= 0)
11724 constraint (shift_amount
> 31,
11725 _("shift expression is too large"));
11727 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11728 inst
.instruction
|= 0x00200000; /* sh bit. */
11730 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11731 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11739 do_t_ssat_usat (1);
11747 Rd
= inst
.operands
[0].reg
;
11748 Rn
= inst
.operands
[2].reg
;
11750 reject_bad_reg (Rd
);
11751 reject_bad_reg (Rn
);
11753 inst
.instruction
|= Rd
<< 8;
11754 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11755 inst
.instruction
|= Rn
<< 16;
11761 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11762 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11763 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11764 || inst
.operands
[2].negative
,
11767 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11769 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11770 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11771 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11772 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11778 if (!inst
.operands
[2].present
)
11779 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11781 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11782 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11783 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11786 inst
.instruction
|= inst
.operands
[0].reg
;
11787 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11788 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11789 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11795 unsigned Rd
, Rn
, Rm
;
11797 Rd
= inst
.operands
[0].reg
;
11798 Rn
= inst
.operands
[1].reg
;
11799 Rm
= inst
.operands
[2].reg
;
11801 reject_bad_reg (Rd
);
11802 reject_bad_reg (Rn
);
11803 reject_bad_reg (Rm
);
11805 inst
.instruction
|= Rd
<< 8;
11806 inst
.instruction
|= Rn
<< 16;
11807 inst
.instruction
|= Rm
;
11808 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11816 Rd
= inst
.operands
[0].reg
;
11817 Rm
= inst
.operands
[1].reg
;
11819 reject_bad_reg (Rd
);
11820 reject_bad_reg (Rm
);
11822 if (inst
.instruction
<= 0xffff
11823 && inst
.size_req
!= 4
11824 && Rd
<= 7 && Rm
<= 7
11825 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11827 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11828 inst
.instruction
|= Rd
;
11829 inst
.instruction
|= Rm
<< 3;
11831 else if (unified_syntax
)
11833 if (inst
.instruction
<= 0xffff)
11834 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11835 inst
.instruction
|= Rd
<< 8;
11836 inst
.instruction
|= Rm
;
11837 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11841 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11842 _("Thumb encoding does not support rotation"));
11843 constraint (1, BAD_HIREG
);
11850 /* We have to do the following check manually as ARM_EXT_OS only applies
11852 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11854 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
11855 /* This only applies to the v6m howver, not later architectures. */
11856 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
11857 as_bad (_("SVC is not permitted on this architecture"));
11858 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11861 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11870 half
= (inst
.instruction
& 0x10) != 0;
11871 set_it_insn_type_last ();
11872 constraint (inst
.operands
[0].immisreg
,
11873 _("instruction requires register index"));
11875 Rn
= inst
.operands
[0].reg
;
11876 Rm
= inst
.operands
[0].imm
;
11878 constraint (Rn
== REG_SP
, BAD_SP
);
11879 reject_bad_reg (Rm
);
11881 constraint (!half
&& inst
.operands
[0].shifted
,
11882 _("instruction does not allow shifted index"));
11883 inst
.instruction
|= (Rn
<< 16) | Rm
;
11889 do_t_ssat_usat (0);
11897 Rd
= inst
.operands
[0].reg
;
11898 Rn
= inst
.operands
[2].reg
;
11900 reject_bad_reg (Rd
);
11901 reject_bad_reg (Rn
);
11903 inst
.instruction
|= Rd
<< 8;
11904 inst
.instruction
|= inst
.operands
[1].imm
;
11905 inst
.instruction
|= Rn
<< 16;
11908 /* Neon instruction encoder helpers. */
11910 /* Encodings for the different types for various Neon opcodes. */
11912 /* An "invalid" code for the following tables. */
11915 struct neon_tab_entry
11918 unsigned float_or_poly
;
11919 unsigned scalar_or_imm
;
11922 /* Map overloaded Neon opcodes to their respective encodings. */
11923 #define NEON_ENC_TAB \
11924 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11925 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11926 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11927 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11928 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11929 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11930 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11931 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11932 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11933 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11934 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11935 /* Register variants of the following two instructions are encoded as
11936 vcge / vcgt with the operands reversed. */ \
11937 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11938 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11939 X(vfma, N_INV, 0x0000c10, N_INV), \
11940 X(vfms, N_INV, 0x0200c10, N_INV), \
11941 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11942 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11943 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11944 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11945 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11946 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11947 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11948 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11949 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11950 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11951 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11952 X(vshl, 0x0000400, N_INV, 0x0800510), \
11953 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11954 X(vand, 0x0000110, N_INV, 0x0800030), \
11955 X(vbic, 0x0100110, N_INV, 0x0800030), \
11956 X(veor, 0x1000110, N_INV, N_INV), \
11957 X(vorn, 0x0300110, N_INV, 0x0800010), \
11958 X(vorr, 0x0200110, N_INV, 0x0800010), \
11959 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11960 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11961 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11962 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11963 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11964 X(vst1, 0x0000000, 0x0800000, N_INV), \
11965 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11966 X(vst2, 0x0000100, 0x0800100, N_INV), \
11967 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11968 X(vst3, 0x0000200, 0x0800200, N_INV), \
11969 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11970 X(vst4, 0x0000300, 0x0800300, N_INV), \
11971 X(vmovn, 0x1b20200, N_INV, N_INV), \
11972 X(vtrn, 0x1b20080, N_INV, N_INV), \
11973 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11974 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11975 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11976 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11977 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11978 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11979 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11980 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11981 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11982 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11983 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11987 #define X(OPC,I,F,S) N_MNEM_##OPC
11992 static const struct neon_tab_entry neon_enc_tab
[] =
11994 #define X(OPC,I,F,S) { (I), (F), (S) }
11999 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12000 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12001 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12002 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12003 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12004 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12005 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12006 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12007 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12008 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12009 #define NEON_ENC_SINGLE_(X) \
12010 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12011 #define NEON_ENC_DOUBLE_(X) \
12012 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12014 #define NEON_ENCODE(type, inst) \
12017 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12018 inst.is_neon = 1; \
12022 #define check_neon_suffixes \
12025 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12027 as_bad (_("invalid neon suffix for non neon instruction")); \
12033 /* Define shapes for instruction operands. The following mnemonic characters
12034 are used in this table:
12036 F - VFP S<n> register
12037 D - Neon D<n> register
12038 Q - Neon Q<n> register
12042 L - D<n> register list
12044 This table is used to generate various data:
12045 - enumerations of the form NS_DDR to be used as arguments to
12047 - a table classifying shapes into single, double, quad, mixed.
12048 - a table used to drive neon_select_shape. */
12050 #define NEON_SHAPE_DEF \
12051 X(3, (D, D, D), DOUBLE), \
12052 X(3, (Q, Q, Q), QUAD), \
12053 X(3, (D, D, I), DOUBLE), \
12054 X(3, (Q, Q, I), QUAD), \
12055 X(3, (D, D, S), DOUBLE), \
12056 X(3, (Q, Q, S), QUAD), \
12057 X(2, (D, D), DOUBLE), \
12058 X(2, (Q, Q), QUAD), \
12059 X(2, (D, S), DOUBLE), \
12060 X(2, (Q, S), QUAD), \
12061 X(2, (D, R), DOUBLE), \
12062 X(2, (Q, R), QUAD), \
12063 X(2, (D, I), DOUBLE), \
12064 X(2, (Q, I), QUAD), \
12065 X(3, (D, L, D), DOUBLE), \
12066 X(2, (D, Q), MIXED), \
12067 X(2, (Q, D), MIXED), \
12068 X(3, (D, Q, I), MIXED), \
12069 X(3, (Q, D, I), MIXED), \
12070 X(3, (Q, D, D), MIXED), \
12071 X(3, (D, Q, Q), MIXED), \
12072 X(3, (Q, Q, D), MIXED), \
12073 X(3, (Q, D, S), MIXED), \
12074 X(3, (D, Q, S), MIXED), \
12075 X(4, (D, D, D, I), DOUBLE), \
12076 X(4, (Q, Q, Q, I), QUAD), \
12077 X(2, (F, F), SINGLE), \
12078 X(3, (F, F, F), SINGLE), \
12079 X(2, (F, I), SINGLE), \
12080 X(2, (F, D), MIXED), \
12081 X(2, (D, F), MIXED), \
12082 X(3, (F, F, I), MIXED), \
12083 X(4, (R, R, F, F), SINGLE), \
12084 X(4, (F, F, R, R), SINGLE), \
12085 X(3, (D, R, R), DOUBLE), \
12086 X(3, (R, R, D), DOUBLE), \
12087 X(2, (S, R), SINGLE), \
12088 X(2, (R, S), SINGLE), \
12089 X(2, (F, R), SINGLE), \
12090 X(2, (R, F), SINGLE)
12092 #define S2(A,B) NS_##A##B
12093 #define S3(A,B,C) NS_##A##B##C
12094 #define S4(A,B,C,D) NS_##A##B##C##D
12096 #define X(N, L, C) S##N L
12109 enum neon_shape_class
12117 #define X(N, L, C) SC_##C
12119 static enum neon_shape_class neon_shape_class
[] =
12137 /* Register widths of above. */
12138 static unsigned neon_shape_el_size
[] =
12149 struct neon_shape_info
12152 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12155 #define S2(A,B) { SE_##A, SE_##B }
12156 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12157 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12159 #define X(N, L, C) { N, S##N L }
12161 static struct neon_shape_info neon_shape_tab
[] =
12171 /* Bit masks used in type checking given instructions.
12172 'N_EQK' means the type must be the same as (or based on in some way) the key
12173 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12174 set, various other bits can be set as well in order to modify the meaning of
12175 the type constraint. */
12177 enum neon_type_mask
12200 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12201 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12202 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12203 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12204 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12205 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12206 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12207 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12208 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12209 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12211 N_MAX_NONSPECIAL
= N_F64
12214 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12216 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12217 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12218 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12219 #define N_SUF_32 (N_SU_32 | N_F32)
12220 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12221 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12223 /* Pass this as the first type argument to neon_check_type to ignore types
12225 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12227 /* Select a "shape" for the current instruction (describing register types or
12228 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12229 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12230 function of operand parsing, so this function doesn't need to be called.
12231 Shapes should be listed in order of decreasing length. */
12233 static enum neon_shape
12234 neon_select_shape (enum neon_shape shape
, ...)
12237 enum neon_shape first_shape
= shape
;
12239 /* Fix missing optional operands. FIXME: we don't know at this point how
12240 many arguments we should have, so this makes the assumption that we have
12241 > 1. This is true of all current Neon opcodes, I think, but may not be
12242 true in the future. */
12243 if (!inst
.operands
[1].present
)
12244 inst
.operands
[1] = inst
.operands
[0];
12246 va_start (ap
, shape
);
12248 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12253 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12255 if (!inst
.operands
[j
].present
)
12261 switch (neon_shape_tab
[shape
].el
[j
])
12264 if (!(inst
.operands
[j
].isreg
12265 && inst
.operands
[j
].isvec
12266 && inst
.operands
[j
].issingle
12267 && !inst
.operands
[j
].isquad
))
12272 if (!(inst
.operands
[j
].isreg
12273 && inst
.operands
[j
].isvec
12274 && !inst
.operands
[j
].isquad
12275 && !inst
.operands
[j
].issingle
))
12280 if (!(inst
.operands
[j
].isreg
12281 && !inst
.operands
[j
].isvec
))
12286 if (!(inst
.operands
[j
].isreg
12287 && inst
.operands
[j
].isvec
12288 && inst
.operands
[j
].isquad
12289 && !inst
.operands
[j
].issingle
))
12294 if (!(!inst
.operands
[j
].isreg
12295 && !inst
.operands
[j
].isscalar
))
12300 if (!(!inst
.operands
[j
].isreg
12301 && inst
.operands
[j
].isscalar
))
12317 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12318 first_error (_("invalid instruction shape"));
12323 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12324 means the Q bit should be set). */
12327 neon_quad (enum neon_shape shape
)
12329 return neon_shape_class
[shape
] == SC_QUAD
;
12333 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12336 /* Allow modification to be made to types which are constrained to be
12337 based on the key element, based on bits set alongside N_EQK. */
12338 if ((typebits
& N_EQK
) != 0)
12340 if ((typebits
& N_HLF
) != 0)
12342 else if ((typebits
& N_DBL
) != 0)
12344 if ((typebits
& N_SGN
) != 0)
12345 *g_type
= NT_signed
;
12346 else if ((typebits
& N_UNS
) != 0)
12347 *g_type
= NT_unsigned
;
12348 else if ((typebits
& N_INT
) != 0)
12349 *g_type
= NT_integer
;
12350 else if ((typebits
& N_FLT
) != 0)
12351 *g_type
= NT_float
;
12352 else if ((typebits
& N_SIZ
) != 0)
12353 *g_type
= NT_untyped
;
12357 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12358 operand type, i.e. the single type specified in a Neon instruction when it
12359 is the only one given. */
12361 static struct neon_type_el
12362 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12364 struct neon_type_el dest
= *key
;
12366 gas_assert ((thisarg
& N_EQK
) != 0);
12368 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12373 /* Convert Neon type and size into compact bitmask representation. */
12375 static enum neon_type_mask
12376 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12383 case 8: return N_8
;
12384 case 16: return N_16
;
12385 case 32: return N_32
;
12386 case 64: return N_64
;
12394 case 8: return N_I8
;
12395 case 16: return N_I16
;
12396 case 32: return N_I32
;
12397 case 64: return N_I64
;
12405 case 16: return N_F16
;
12406 case 32: return N_F32
;
12407 case 64: return N_F64
;
12415 case 8: return N_P8
;
12416 case 16: return N_P16
;
12424 case 8: return N_S8
;
12425 case 16: return N_S16
;
12426 case 32: return N_S32
;
12427 case 64: return N_S64
;
12435 case 8: return N_U8
;
12436 case 16: return N_U16
;
12437 case 32: return N_U32
;
12438 case 64: return N_U64
;
12449 /* Convert compact Neon bitmask type representation to a type and size. Only
12450 handles the case where a single bit is set in the mask. */
12453 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12454 enum neon_type_mask mask
)
12456 if ((mask
& N_EQK
) != 0)
12459 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12461 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12463 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12465 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12470 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12472 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12473 *type
= NT_unsigned
;
12474 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12475 *type
= NT_integer
;
12476 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12477 *type
= NT_untyped
;
12478 else if ((mask
& (N_P8
| N_P16
)) != 0)
12480 else if ((mask
& (N_F32
| N_F64
)) != 0)
12488 /* Modify a bitmask of allowed types. This is only needed for type
12492 modify_types_allowed (unsigned allowed
, unsigned mods
)
12495 enum neon_el_type type
;
12501 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12503 if (el_type_of_type_chk (&type
, &size
,
12504 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12506 neon_modify_type_size (mods
, &type
, &size
);
12507 destmask
|= type_chk_of_el_type (type
, size
);
12514 /* Check type and return type classification.
12515 The manual states (paraphrase): If one datatype is given, it indicates the
12517 - the second operand, if there is one
12518 - the operand, if there is no second operand
12519 - the result, if there are no operands.
12520 This isn't quite good enough though, so we use a concept of a "key" datatype
12521 which is set on a per-instruction basis, which is the one which matters when
12522 only one data type is written.
12523 Note: this function has side-effects (e.g. filling in missing operands). All
12524 Neon instructions should call it before performing bit encoding. */
12526 static struct neon_type_el
12527 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12530 unsigned i
, pass
, key_el
= 0;
12531 unsigned types
[NEON_MAX_TYPE_ELS
];
12532 enum neon_el_type k_type
= NT_invtype
;
12533 unsigned k_size
= -1u;
12534 struct neon_type_el badtype
= {NT_invtype
, -1};
12535 unsigned key_allowed
= 0;
12537 /* Optional registers in Neon instructions are always (not) in operand 1.
12538 Fill in the missing operand here, if it was omitted. */
12539 if (els
> 1 && !inst
.operands
[1].present
)
12540 inst
.operands
[1] = inst
.operands
[0];
12542 /* Suck up all the varargs. */
12544 for (i
= 0; i
< els
; i
++)
12546 unsigned thisarg
= va_arg (ap
, unsigned);
12547 if (thisarg
== N_IGNORE_TYPE
)
12552 types
[i
] = thisarg
;
12553 if ((thisarg
& N_KEY
) != 0)
12558 if (inst
.vectype
.elems
> 0)
12559 for (i
= 0; i
< els
; i
++)
12560 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12562 first_error (_("types specified in both the mnemonic and operands"));
12566 /* Duplicate inst.vectype elements here as necessary.
12567 FIXME: No idea if this is exactly the same as the ARM assembler,
12568 particularly when an insn takes one register and one non-register
12570 if (inst
.vectype
.elems
== 1 && els
> 1)
12573 inst
.vectype
.elems
= els
;
12574 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12575 for (j
= 0; j
< els
; j
++)
12577 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12580 else if (inst
.vectype
.elems
== 0 && els
> 0)
12583 /* No types were given after the mnemonic, so look for types specified
12584 after each operand. We allow some flexibility here; as long as the
12585 "key" operand has a type, we can infer the others. */
12586 for (j
= 0; j
< els
; j
++)
12587 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12588 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12590 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12592 for (j
= 0; j
< els
; j
++)
12593 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12594 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12599 first_error (_("operand types can't be inferred"));
12603 else if (inst
.vectype
.elems
!= els
)
12605 first_error (_("type specifier has the wrong number of parts"));
12609 for (pass
= 0; pass
< 2; pass
++)
12611 for (i
= 0; i
< els
; i
++)
12613 unsigned thisarg
= types
[i
];
12614 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12615 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12616 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12617 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12619 /* Decay more-specific signed & unsigned types to sign-insensitive
12620 integer types if sign-specific variants are unavailable. */
12621 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12622 && (types_allowed
& N_SU_ALL
) == 0)
12623 g_type
= NT_integer
;
12625 /* If only untyped args are allowed, decay any more specific types to
12626 them. Some instructions only care about signs for some element
12627 sizes, so handle that properly. */
12628 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12629 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12630 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12631 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12632 g_type
= NT_untyped
;
12636 if ((thisarg
& N_KEY
) != 0)
12640 key_allowed
= thisarg
& ~N_KEY
;
12645 if ((thisarg
& N_VFP
) != 0)
12647 enum neon_shape_el regshape
;
12648 unsigned regwidth
, match
;
12650 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12653 first_error (_("invalid instruction shape"));
12656 regshape
= neon_shape_tab
[ns
].el
[i
];
12657 regwidth
= neon_shape_el_size
[regshape
];
12659 /* In VFP mode, operands must match register widths. If we
12660 have a key operand, use its width, else use the width of
12661 the current operand. */
12667 if (regwidth
!= match
)
12669 first_error (_("operand size must match register width"));
12674 if ((thisarg
& N_EQK
) == 0)
12676 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12678 if ((given_type
& types_allowed
) == 0)
12680 first_error (_("bad type in Neon instruction"));
12686 enum neon_el_type mod_k_type
= k_type
;
12687 unsigned mod_k_size
= k_size
;
12688 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12689 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12691 first_error (_("inconsistent types in Neon instruction"));
12699 return inst
.vectype
.el
[key_el
];
12702 /* Neon-style VFP instruction forwarding. */
12704 /* Thumb VFP instructions have 0xE in the condition field. */
12707 do_vfp_cond_or_thumb (void)
12712 inst
.instruction
|= 0xe0000000;
12714 inst
.instruction
|= inst
.cond
<< 28;
12717 /* Look up and encode a simple mnemonic, for use as a helper function for the
12718 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12719 etc. It is assumed that operand parsing has already been done, and that the
12720 operands are in the form expected by the given opcode (this isn't necessarily
12721 the same as the form in which they were parsed, hence some massaging must
12722 take place before this function is called).
12723 Checks current arch version against that in the looked-up opcode. */
12726 do_vfp_nsyn_opcode (const char *opname
)
12728 const struct asm_opcode
*opcode
;
12730 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12735 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12736 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12743 inst
.instruction
= opcode
->tvalue
;
12744 opcode
->tencode ();
12748 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12749 opcode
->aencode ();
12754 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12756 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12761 do_vfp_nsyn_opcode ("fadds");
12763 do_vfp_nsyn_opcode ("fsubs");
12768 do_vfp_nsyn_opcode ("faddd");
12770 do_vfp_nsyn_opcode ("fsubd");
12774 /* Check operand types to see if this is a VFP instruction, and if so call
12778 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12780 enum neon_shape rs
;
12781 struct neon_type_el et
;
12786 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12787 et
= neon_check_type (2, rs
,
12788 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12792 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12793 et
= neon_check_type (3, rs
,
12794 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12801 if (et
.type
!= NT_invtype
)
12812 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12814 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12819 do_vfp_nsyn_opcode ("fmacs");
12821 do_vfp_nsyn_opcode ("fnmacs");
12826 do_vfp_nsyn_opcode ("fmacd");
12828 do_vfp_nsyn_opcode ("fnmacd");
12833 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12835 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12840 do_vfp_nsyn_opcode ("ffmas");
12842 do_vfp_nsyn_opcode ("ffnmas");
12847 do_vfp_nsyn_opcode ("ffmad");
12849 do_vfp_nsyn_opcode ("ffnmad");
12854 do_vfp_nsyn_mul (enum neon_shape rs
)
12857 do_vfp_nsyn_opcode ("fmuls");
12859 do_vfp_nsyn_opcode ("fmuld");
12863 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12865 int is_neg
= (inst
.instruction
& 0x80) != 0;
12866 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12871 do_vfp_nsyn_opcode ("fnegs");
12873 do_vfp_nsyn_opcode ("fabss");
12878 do_vfp_nsyn_opcode ("fnegd");
12880 do_vfp_nsyn_opcode ("fabsd");
12884 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12885 insns belong to Neon, and are handled elsewhere. */
12888 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12890 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12894 do_vfp_nsyn_opcode ("fldmdbs");
12896 do_vfp_nsyn_opcode ("fldmias");
12901 do_vfp_nsyn_opcode ("fstmdbs");
12903 do_vfp_nsyn_opcode ("fstmias");
12908 do_vfp_nsyn_sqrt (void)
12910 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12911 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12914 do_vfp_nsyn_opcode ("fsqrts");
12916 do_vfp_nsyn_opcode ("fsqrtd");
12920 do_vfp_nsyn_div (void)
12922 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12923 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12924 N_F32
| N_F64
| N_KEY
| N_VFP
);
12927 do_vfp_nsyn_opcode ("fdivs");
12929 do_vfp_nsyn_opcode ("fdivd");
12933 do_vfp_nsyn_nmul (void)
12935 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12936 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12937 N_F32
| N_F64
| N_KEY
| N_VFP
);
12941 NEON_ENCODE (SINGLE
, inst
);
12942 do_vfp_sp_dyadic ();
12946 NEON_ENCODE (DOUBLE
, inst
);
12947 do_vfp_dp_rd_rn_rm ();
12949 do_vfp_cond_or_thumb ();
12953 do_vfp_nsyn_cmp (void)
12955 if (inst
.operands
[1].isreg
)
12957 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12958 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12962 NEON_ENCODE (SINGLE
, inst
);
12963 do_vfp_sp_monadic ();
12967 NEON_ENCODE (DOUBLE
, inst
);
12968 do_vfp_dp_rd_rm ();
12973 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12974 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12976 switch (inst
.instruction
& 0x0fffffff)
12979 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12982 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12990 NEON_ENCODE (SINGLE
, inst
);
12991 do_vfp_sp_compare_z ();
12995 NEON_ENCODE (DOUBLE
, inst
);
12999 do_vfp_cond_or_thumb ();
13003 nsyn_insert_sp (void)
13005 inst
.operands
[1] = inst
.operands
[0];
13006 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13007 inst
.operands
[0].reg
= REG_SP
;
13008 inst
.operands
[0].isreg
= 1;
13009 inst
.operands
[0].writeback
= 1;
13010 inst
.operands
[0].present
= 1;
13014 do_vfp_nsyn_push (void)
13017 if (inst
.operands
[1].issingle
)
13018 do_vfp_nsyn_opcode ("fstmdbs");
13020 do_vfp_nsyn_opcode ("fstmdbd");
13024 do_vfp_nsyn_pop (void)
13027 if (inst
.operands
[1].issingle
)
13028 do_vfp_nsyn_opcode ("fldmias");
13030 do_vfp_nsyn_opcode ("fldmiad");
13033 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13034 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13037 neon_dp_fixup (struct arm_it
* insn
)
13039 unsigned int i
= insn
->instruction
;
13044 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13055 insn
->instruction
= i
;
13058 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13062 neon_logbits (unsigned x
)
13064 return ffs (x
) - 4;
13067 #define LOW4(R) ((R) & 0xf)
13068 #define HI1(R) (((R) >> 4) & 1)
13070 /* Encode insns with bit pattern:
13072 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13073 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13075 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13076 different meaning for some instruction. */
13079 neon_three_same (int isquad
, int ubit
, int size
)
13081 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13082 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13083 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13084 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13085 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13086 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13087 inst
.instruction
|= (isquad
!= 0) << 6;
13088 inst
.instruction
|= (ubit
!= 0) << 24;
13090 inst
.instruction
|= neon_logbits (size
) << 20;
13092 neon_dp_fixup (&inst
);
13095 /* Encode instructions of the form:
13097 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13098 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13100 Don't write size if SIZE == -1. */
13103 neon_two_same (int qbit
, int ubit
, int size
)
13105 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13106 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13107 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13108 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13109 inst
.instruction
|= (qbit
!= 0) << 6;
13110 inst
.instruction
|= (ubit
!= 0) << 24;
13113 inst
.instruction
|= neon_logbits (size
) << 18;
13115 neon_dp_fixup (&inst
);
13118 /* Neon instruction encoders, in approximate order of appearance. */
13121 do_neon_dyadic_i_su (void)
13123 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13124 struct neon_type_el et
= neon_check_type (3, rs
,
13125 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13126 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13130 do_neon_dyadic_i64_su (void)
13132 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13133 struct neon_type_el et
= neon_check_type (3, rs
,
13134 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13135 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13139 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13142 unsigned size
= et
.size
>> 3;
13143 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13144 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13145 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13146 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13147 inst
.instruction
|= (isquad
!= 0) << 6;
13148 inst
.instruction
|= immbits
<< 16;
13149 inst
.instruction
|= (size
>> 3) << 7;
13150 inst
.instruction
|= (size
& 0x7) << 19;
13152 inst
.instruction
|= (uval
!= 0) << 24;
13154 neon_dp_fixup (&inst
);
13158 do_neon_shl_imm (void)
13160 if (!inst
.operands
[2].isreg
)
13162 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13163 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13164 NEON_ENCODE (IMMED
, inst
);
13165 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13169 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13170 struct neon_type_el et
= neon_check_type (3, rs
,
13171 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13174 /* VSHL/VQSHL 3-register variants have syntax such as:
13176 whereas other 3-register operations encoded by neon_three_same have
13179 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13181 tmp
= inst
.operands
[2].reg
;
13182 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13183 inst
.operands
[1].reg
= tmp
;
13184 NEON_ENCODE (INTEGER
, inst
);
13185 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13190 do_neon_qshl_imm (void)
13192 if (!inst
.operands
[2].isreg
)
13194 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13195 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13197 NEON_ENCODE (IMMED
, inst
);
13198 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13199 inst
.operands
[2].imm
);
13203 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13204 struct neon_type_el et
= neon_check_type (3, rs
,
13205 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13208 /* See note in do_neon_shl_imm. */
13209 tmp
= inst
.operands
[2].reg
;
13210 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13211 inst
.operands
[1].reg
= tmp
;
13212 NEON_ENCODE (INTEGER
, inst
);
13213 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13218 do_neon_rshl (void)
13220 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13221 struct neon_type_el et
= neon_check_type (3, rs
,
13222 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13225 tmp
= inst
.operands
[2].reg
;
13226 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13227 inst
.operands
[1].reg
= tmp
;
13228 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13232 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13234 /* Handle .I8 pseudo-instructions. */
13237 /* Unfortunately, this will make everything apart from zero out-of-range.
13238 FIXME is this the intended semantics? There doesn't seem much point in
13239 accepting .I8 if so. */
13240 immediate
|= immediate
<< 8;
13246 if (immediate
== (immediate
& 0x000000ff))
13248 *immbits
= immediate
;
13251 else if (immediate
== (immediate
& 0x0000ff00))
13253 *immbits
= immediate
>> 8;
13256 else if (immediate
== (immediate
& 0x00ff0000))
13258 *immbits
= immediate
>> 16;
13261 else if (immediate
== (immediate
& 0xff000000))
13263 *immbits
= immediate
>> 24;
13266 if ((immediate
& 0xffff) != (immediate
>> 16))
13267 goto bad_immediate
;
13268 immediate
&= 0xffff;
13271 if (immediate
== (immediate
& 0x000000ff))
13273 *immbits
= immediate
;
13276 else if (immediate
== (immediate
& 0x0000ff00))
13278 *immbits
= immediate
>> 8;
13283 first_error (_("immediate value out of range"));
13287 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13291 neon_bits_same_in_bytes (unsigned imm
)
13293 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13294 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13295 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13296 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13299 /* For immediate of above form, return 0bABCD. */
13302 neon_squash_bits (unsigned imm
)
13304 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13305 | ((imm
& 0x01000000) >> 21);
13308 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13311 neon_qfloat_bits (unsigned imm
)
13313 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13316 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13317 the instruction. *OP is passed as the initial value of the op field, and
13318 may be set to a different value depending on the constant (i.e.
13319 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13320 MVN). If the immediate looks like a repeated pattern then also
13321 try smaller element sizes. */
13324 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13325 unsigned *immbits
, int *op
, int size
,
13326 enum neon_el_type type
)
13328 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13330 if (type
== NT_float
&& !float_p
)
13333 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13335 if (size
!= 32 || *op
== 1)
13337 *immbits
= neon_qfloat_bits (immlo
);
13343 if (neon_bits_same_in_bytes (immhi
)
13344 && neon_bits_same_in_bytes (immlo
))
13348 *immbits
= (neon_squash_bits (immhi
) << 4)
13349 | neon_squash_bits (immlo
);
13354 if (immhi
!= immlo
)
13360 if (immlo
== (immlo
& 0x000000ff))
13365 else if (immlo
== (immlo
& 0x0000ff00))
13367 *immbits
= immlo
>> 8;
13370 else if (immlo
== (immlo
& 0x00ff0000))
13372 *immbits
= immlo
>> 16;
13375 else if (immlo
== (immlo
& 0xff000000))
13377 *immbits
= immlo
>> 24;
13380 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13382 *immbits
= (immlo
>> 8) & 0xff;
13385 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13387 *immbits
= (immlo
>> 16) & 0xff;
13391 if ((immlo
& 0xffff) != (immlo
>> 16))
13398 if (immlo
== (immlo
& 0x000000ff))
13403 else if (immlo
== (immlo
& 0x0000ff00))
13405 *immbits
= immlo
>> 8;
13409 if ((immlo
& 0xff) != (immlo
>> 8))
13414 if (immlo
== (immlo
& 0x000000ff))
13416 /* Don't allow MVN with 8-bit immediate. */
13426 /* Write immediate bits [7:0] to the following locations:
13428 |28/24|23 19|18 16|15 4|3 0|
13429 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13431 This function is used by VMOV/VMVN/VORR/VBIC. */
13434 neon_write_immbits (unsigned immbits
)
13436 inst
.instruction
|= immbits
& 0xf;
13437 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13438 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13441 /* Invert low-order SIZE bits of XHI:XLO. */
13444 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13446 unsigned immlo
= xlo
? *xlo
: 0;
13447 unsigned immhi
= xhi
? *xhi
: 0;
13452 immlo
= (~immlo
) & 0xff;
13456 immlo
= (~immlo
) & 0xffff;
13460 immhi
= (~immhi
) & 0xffffffff;
13461 /* fall through. */
13464 immlo
= (~immlo
) & 0xffffffff;
13479 do_neon_logic (void)
13481 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13483 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13484 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13485 /* U bit and size field were set as part of the bitmask. */
13486 NEON_ENCODE (INTEGER
, inst
);
13487 neon_three_same (neon_quad (rs
), 0, -1);
13491 const int three_ops_form
= (inst
.operands
[2].present
13492 && !inst
.operands
[2].isreg
);
13493 const int immoperand
= (three_ops_form
? 2 : 1);
13494 enum neon_shape rs
= (three_ops_form
13495 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13496 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13497 struct neon_type_el et
= neon_check_type (2, rs
,
13498 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13499 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13503 if (et
.type
== NT_invtype
)
13506 if (three_ops_form
)
13507 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13508 _("first and second operands shall be the same register"));
13510 NEON_ENCODE (IMMED
, inst
);
13512 immbits
= inst
.operands
[immoperand
].imm
;
13515 /* .i64 is a pseudo-op, so the immediate must be a repeating
13517 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13518 inst
.operands
[immoperand
].reg
: 0))
13520 /* Set immbits to an invalid constant. */
13521 immbits
= 0xdeadbeef;
13528 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13532 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13536 /* Pseudo-instruction for VBIC. */
13537 neon_invert_size (&immbits
, 0, et
.size
);
13538 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13542 /* Pseudo-instruction for VORR. */
13543 neon_invert_size (&immbits
, 0, et
.size
);
13544 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13554 inst
.instruction
|= neon_quad (rs
) << 6;
13555 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13556 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13557 inst
.instruction
|= cmode
<< 8;
13558 neon_write_immbits (immbits
);
13560 neon_dp_fixup (&inst
);
13565 do_neon_bitfield (void)
13567 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13568 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13569 neon_three_same (neon_quad (rs
), 0, -1);
13573 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13576 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13577 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13579 if (et
.type
== NT_float
)
13581 NEON_ENCODE (FLOAT
, inst
);
13582 neon_three_same (neon_quad (rs
), 0, -1);
13586 NEON_ENCODE (INTEGER
, inst
);
13587 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13592 do_neon_dyadic_if_su (void)
13594 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13598 do_neon_dyadic_if_su_d (void)
13600 /* This version only allow D registers, but that constraint is enforced during
13601 operand parsing so we don't need to do anything extra here. */
13602 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13606 do_neon_dyadic_if_i_d (void)
13608 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13609 affected if we specify unsigned args. */
13610 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13613 enum vfp_or_neon_is_neon_bits
13616 NEON_CHECK_ARCH
= 2
13619 /* Call this function if an instruction which may have belonged to the VFP or
13620 Neon instruction sets, but turned out to be a Neon instruction (due to the
13621 operand types involved, etc.). We have to check and/or fix-up a couple of
13624 - Make sure the user hasn't attempted to make a Neon instruction
13626 - Alter the value in the condition code field if necessary.
13627 - Make sure that the arch supports Neon instructions.
13629 Which of these operations take place depends on bits from enum
13630 vfp_or_neon_is_neon_bits.
13632 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13633 current instruction's condition is COND_ALWAYS, the condition field is
13634 changed to inst.uncond_value. This is necessary because instructions shared
13635 between VFP and Neon may be conditional for the VFP variants only, and the
13636 unconditional Neon version must have, e.g., 0xF in the condition field. */
13639 vfp_or_neon_is_neon (unsigned check
)
13641 /* Conditions are always legal in Thumb mode (IT blocks). */
13642 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13644 if (inst
.cond
!= COND_ALWAYS
)
13646 first_error (_(BAD_COND
));
13649 if (inst
.uncond_value
!= -1)
13650 inst
.instruction
|= inst
.uncond_value
<< 28;
13653 if ((check
& NEON_CHECK_ARCH
)
13654 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13656 first_error (_(BAD_FPU
));
13664 do_neon_addsub_if_i (void)
13666 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13669 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13672 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13673 affected if we specify unsigned args. */
13674 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13677 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13679 V<op> A,B (A is operand 0, B is operand 2)
13684 so handle that case specially. */
13687 neon_exchange_operands (void)
13689 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13690 if (inst
.operands
[1].present
)
13692 /* Swap operands[1] and operands[2]. */
13693 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13694 inst
.operands
[1] = inst
.operands
[2];
13695 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13699 inst
.operands
[1] = inst
.operands
[2];
13700 inst
.operands
[2] = inst
.operands
[0];
13705 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13707 if (inst
.operands
[2].isreg
)
13710 neon_exchange_operands ();
13711 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13715 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13716 struct neon_type_el et
= neon_check_type (2, rs
,
13717 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13719 NEON_ENCODE (IMMED
, inst
);
13720 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13721 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13722 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13723 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13724 inst
.instruction
|= neon_quad (rs
) << 6;
13725 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13726 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13728 neon_dp_fixup (&inst
);
13735 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13739 do_neon_cmp_inv (void)
13741 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13747 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13750 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13751 scalars, which are encoded in 5 bits, M : Rm.
13752 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13753 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13757 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13759 unsigned regno
= NEON_SCALAR_REG (scalar
);
13760 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13765 if (regno
> 7 || elno
> 3)
13767 return regno
| (elno
<< 3);
13770 if (regno
> 15 || elno
> 1)
13772 return regno
| (elno
<< 4);
13776 first_error (_("scalar out of range for multiply instruction"));
13782 /* Encode multiply / multiply-accumulate scalar instructions. */
13785 neon_mul_mac (struct neon_type_el et
, int ubit
)
13789 /* Give a more helpful error message if we have an invalid type. */
13790 if (et
.type
== NT_invtype
)
13793 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13794 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13795 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13796 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13797 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13798 inst
.instruction
|= LOW4 (scalar
);
13799 inst
.instruction
|= HI1 (scalar
) << 5;
13800 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13801 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13802 inst
.instruction
|= (ubit
!= 0) << 24;
13804 neon_dp_fixup (&inst
);
13808 do_neon_mac_maybe_scalar (void)
13810 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13813 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13816 if (inst
.operands
[2].isscalar
)
13818 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13819 struct neon_type_el et
= neon_check_type (3, rs
,
13820 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13821 NEON_ENCODE (SCALAR
, inst
);
13822 neon_mul_mac (et
, neon_quad (rs
));
13826 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13827 affected if we specify unsigned args. */
13828 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13833 do_neon_fmac (void)
13835 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13838 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13841 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13847 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13848 struct neon_type_el et
= neon_check_type (3, rs
,
13849 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13850 neon_three_same (neon_quad (rs
), 0, et
.size
);
13853 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13854 same types as the MAC equivalents. The polynomial type for this instruction
13855 is encoded the same as the integer type. */
13860 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13863 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13866 if (inst
.operands
[2].isscalar
)
13867 do_neon_mac_maybe_scalar ();
13869 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13873 do_neon_qdmulh (void)
13875 if (inst
.operands
[2].isscalar
)
13877 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13878 struct neon_type_el et
= neon_check_type (3, rs
,
13879 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13880 NEON_ENCODE (SCALAR
, inst
);
13881 neon_mul_mac (et
, neon_quad (rs
));
13885 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13886 struct neon_type_el et
= neon_check_type (3, rs
,
13887 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13888 NEON_ENCODE (INTEGER
, inst
);
13889 /* The U bit (rounding) comes from bit mask. */
13890 neon_three_same (neon_quad (rs
), 0, et
.size
);
13895 do_neon_fcmp_absolute (void)
13897 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13898 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13899 /* Size field comes from bit mask. */
13900 neon_three_same (neon_quad (rs
), 1, -1);
13904 do_neon_fcmp_absolute_inv (void)
13906 neon_exchange_operands ();
13907 do_neon_fcmp_absolute ();
13911 do_neon_step (void)
13913 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13914 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13915 neon_three_same (neon_quad (rs
), 0, -1);
13919 do_neon_abs_neg (void)
13921 enum neon_shape rs
;
13922 struct neon_type_el et
;
13924 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13927 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13930 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13931 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13933 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13934 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13935 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13936 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13937 inst
.instruction
|= neon_quad (rs
) << 6;
13938 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13939 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13941 neon_dp_fixup (&inst
);
13947 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13948 struct neon_type_el et
= neon_check_type (2, rs
,
13949 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13950 int imm
= inst
.operands
[2].imm
;
13951 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13952 _("immediate out of range for insert"));
13953 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13959 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13960 struct neon_type_el et
= neon_check_type (2, rs
,
13961 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13962 int imm
= inst
.operands
[2].imm
;
13963 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13964 _("immediate out of range for insert"));
13965 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13969 do_neon_qshlu_imm (void)
13971 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13972 struct neon_type_el et
= neon_check_type (2, rs
,
13973 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13974 int imm
= inst
.operands
[2].imm
;
13975 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13976 _("immediate out of range for shift"));
13977 /* Only encodes the 'U present' variant of the instruction.
13978 In this case, signed types have OP (bit 8) set to 0.
13979 Unsigned types have OP set to 1. */
13980 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13981 /* The rest of the bits are the same as other immediate shifts. */
13982 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13986 do_neon_qmovn (void)
13988 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13989 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13990 /* Saturating move where operands can be signed or unsigned, and the
13991 destination has the same signedness. */
13992 NEON_ENCODE (INTEGER
, inst
);
13993 if (et
.type
== NT_unsigned
)
13994 inst
.instruction
|= 0xc0;
13996 inst
.instruction
|= 0x80;
13997 neon_two_same (0, 1, et
.size
/ 2);
14001 do_neon_qmovun (void)
14003 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14004 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14005 /* Saturating move with unsigned results. Operands must be signed. */
14006 NEON_ENCODE (INTEGER
, inst
);
14007 neon_two_same (0, 1, et
.size
/ 2);
14011 do_neon_rshift_sat_narrow (void)
14013 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14014 or unsigned. If operands are unsigned, results must also be unsigned. */
14015 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14016 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14017 int imm
= inst
.operands
[2].imm
;
14018 /* This gets the bounds check, size encoding and immediate bits calculation
14022 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14023 VQMOVN.I<size> <Dd>, <Qm>. */
14026 inst
.operands
[2].present
= 0;
14027 inst
.instruction
= N_MNEM_vqmovn
;
14032 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14033 _("immediate out of range"));
14034 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14038 do_neon_rshift_sat_narrow_u (void)
14040 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14041 or unsigned. If operands are unsigned, results must also be unsigned. */
14042 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14043 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14044 int imm
= inst
.operands
[2].imm
;
14045 /* This gets the bounds check, size encoding and immediate bits calculation
14049 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14050 VQMOVUN.I<size> <Dd>, <Qm>. */
14053 inst
.operands
[2].present
= 0;
14054 inst
.instruction
= N_MNEM_vqmovun
;
14059 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14060 _("immediate out of range"));
14061 /* FIXME: The manual is kind of unclear about what value U should have in
14062 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14064 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14068 do_neon_movn (void)
14070 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14071 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14072 NEON_ENCODE (INTEGER
, inst
);
14073 neon_two_same (0, 1, et
.size
/ 2);
14077 do_neon_rshift_narrow (void)
14079 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14080 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14081 int imm
= inst
.operands
[2].imm
;
14082 /* This gets the bounds check, size encoding and immediate bits calculation
14086 /* If immediate is zero then we are a pseudo-instruction for
14087 VMOVN.I<size> <Dd>, <Qm> */
14090 inst
.operands
[2].present
= 0;
14091 inst
.instruction
= N_MNEM_vmovn
;
14096 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14097 _("immediate out of range for narrowing operation"));
14098 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14102 do_neon_shll (void)
14104 /* FIXME: Type checking when lengthening. */
14105 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14106 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14107 unsigned imm
= inst
.operands
[2].imm
;
14109 if (imm
== et
.size
)
14111 /* Maximum shift variant. */
14112 NEON_ENCODE (INTEGER
, inst
);
14113 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14114 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14115 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14116 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14117 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14119 neon_dp_fixup (&inst
);
14123 /* A more-specific type check for non-max versions. */
14124 et
= neon_check_type (2, NS_QDI
,
14125 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14126 NEON_ENCODE (IMMED
, inst
);
14127 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14131 /* Check the various types for the VCVT instruction, and return which version
14132 the current instruction is. */
14135 neon_cvt_flavour (enum neon_shape rs
)
14137 #define CVT_VAR(C,X,Y) \
14138 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14139 if (et.type != NT_invtype) \
14141 inst.error = NULL; \
14144 struct neon_type_el et
;
14145 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14146 || rs
== NS_FF
) ? N_VFP
: 0;
14147 /* The instruction versions which take an immediate take one register
14148 argument, which is extended to the width of the full register. Thus the
14149 "source" and "destination" registers must have the same width. Hack that
14150 here by making the size equal to the key (wider, in this case) operand. */
14151 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14153 CVT_VAR (0, N_S32
, N_F32
);
14154 CVT_VAR (1, N_U32
, N_F32
);
14155 CVT_VAR (2, N_F32
, N_S32
);
14156 CVT_VAR (3, N_F32
, N_U32
);
14157 /* Half-precision conversions. */
14158 CVT_VAR (4, N_F32
, N_F16
);
14159 CVT_VAR (5, N_F16
, N_F32
);
14163 /* VFP instructions. */
14164 CVT_VAR (6, N_F32
, N_F64
);
14165 CVT_VAR (7, N_F64
, N_F32
);
14166 CVT_VAR (8, N_S32
, N_F64
| key
);
14167 CVT_VAR (9, N_U32
, N_F64
| key
);
14168 CVT_VAR (10, N_F64
| key
, N_S32
);
14169 CVT_VAR (11, N_F64
| key
, N_U32
);
14170 /* VFP instructions with bitshift. */
14171 CVT_VAR (12, N_F32
| key
, N_S16
);
14172 CVT_VAR (13, N_F32
| key
, N_U16
);
14173 CVT_VAR (14, N_F64
| key
, N_S16
);
14174 CVT_VAR (15, N_F64
| key
, N_U16
);
14175 CVT_VAR (16, N_S16
, N_F32
| key
);
14176 CVT_VAR (17, N_U16
, N_F32
| key
);
14177 CVT_VAR (18, N_S16
, N_F64
| key
);
14178 CVT_VAR (19, N_U16
, N_F64
| key
);
14184 /* Neon-syntax VFP conversions. */
14187 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14189 const char *opname
= 0;
14191 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14193 /* Conversions with immediate bitshift. */
14194 const char *enc
[] =
14218 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14220 opname
= enc
[flavour
];
14221 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14222 _("operands 0 and 1 must be the same register"));
14223 inst
.operands
[1] = inst
.operands
[2];
14224 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14229 /* Conversions without bitshift. */
14230 const char *enc
[] =
14246 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14247 opname
= enc
[flavour
];
14251 do_vfp_nsyn_opcode (opname
);
14255 do_vfp_nsyn_cvtz (void)
14257 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14258 int flavour
= neon_cvt_flavour (rs
);
14259 const char *enc
[] =
14273 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14274 do_vfp_nsyn_opcode (enc
[flavour
]);
14278 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14280 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14281 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14282 int flavour
= neon_cvt_flavour (rs
);
14284 /* PR11109: Handle round-to-zero for VCVT conversions. */
14286 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14287 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14288 && (rs
== NS_FD
|| rs
== NS_FF
))
14290 do_vfp_nsyn_cvtz ();
14294 /* VFP rather than Neon conversions. */
14297 do_vfp_nsyn_cvt (rs
, flavour
);
14307 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14309 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14312 /* Fixed-point conversion with #0 immediate is encoded as an
14313 integer conversion. */
14314 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14316 immbits
= 32 - inst
.operands
[2].imm
;
14317 NEON_ENCODE (IMMED
, inst
);
14319 inst
.instruction
|= enctab
[flavour
];
14320 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14321 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14322 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14323 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14324 inst
.instruction
|= neon_quad (rs
) << 6;
14325 inst
.instruction
|= 1 << 21;
14326 inst
.instruction
|= immbits
<< 16;
14328 neon_dp_fixup (&inst
);
14336 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14338 NEON_ENCODE (INTEGER
, inst
);
14340 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14344 inst
.instruction
|= enctab
[flavour
];
14346 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14347 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14348 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14349 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14350 inst
.instruction
|= neon_quad (rs
) << 6;
14351 inst
.instruction
|= 2 << 18;
14353 neon_dp_fixup (&inst
);
14357 /* Half-precision conversions for Advanced SIMD -- neon. */
14362 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14364 as_bad (_("operand size must match register width"));
14369 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14371 as_bad (_("operand size must match register width"));
14376 inst
.instruction
= 0x3b60600;
14378 inst
.instruction
= 0x3b60700;
14380 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14381 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14382 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14383 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14384 neon_dp_fixup (&inst
);
14388 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14389 do_vfp_nsyn_cvt (rs
, flavour
);
14394 do_neon_cvtr (void)
14396 do_neon_cvt_1 (FALSE
);
14402 do_neon_cvt_1 (TRUE
);
14406 do_neon_cvtb (void)
14408 inst
.instruction
= 0xeb20a40;
14410 /* The sizes are attached to the mnemonic. */
14411 if (inst
.vectype
.el
[0].type
!= NT_invtype
14412 && inst
.vectype
.el
[0].size
== 16)
14413 inst
.instruction
|= 0x00010000;
14415 /* Programmer's syntax: the sizes are attached to the operands. */
14416 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14417 && inst
.operands
[0].vectype
.size
== 16)
14418 inst
.instruction
|= 0x00010000;
14420 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14421 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14422 do_vfp_cond_or_thumb ();
14427 do_neon_cvtt (void)
14430 inst
.instruction
|= 0x80;
14434 neon_move_immediate (void)
14436 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14437 struct neon_type_el et
= neon_check_type (2, rs
,
14438 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14439 unsigned immlo
, immhi
= 0, immbits
;
14440 int op
, cmode
, float_p
;
14442 constraint (et
.type
== NT_invtype
,
14443 _("operand size must be specified for immediate VMOV"));
14445 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14446 op
= (inst
.instruction
& (1 << 5)) != 0;
14448 immlo
= inst
.operands
[1].imm
;
14449 if (inst
.operands
[1].regisimm
)
14450 immhi
= inst
.operands
[1].reg
;
14452 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14453 _("immediate has bits set outside the operand size"));
14455 float_p
= inst
.operands
[1].immisfloat
;
14457 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14458 et
.size
, et
.type
)) == FAIL
)
14460 /* Invert relevant bits only. */
14461 neon_invert_size (&immlo
, &immhi
, et
.size
);
14462 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14463 with one or the other; those cases are caught by
14464 neon_cmode_for_move_imm. */
14466 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14467 &op
, et
.size
, et
.type
)) == FAIL
)
14469 first_error (_("immediate out of range"));
14474 inst
.instruction
&= ~(1 << 5);
14475 inst
.instruction
|= op
<< 5;
14477 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14478 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14479 inst
.instruction
|= neon_quad (rs
) << 6;
14480 inst
.instruction
|= cmode
<< 8;
14482 neon_write_immbits (immbits
);
14488 if (inst
.operands
[1].isreg
)
14490 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14492 NEON_ENCODE (INTEGER
, inst
);
14493 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14494 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14495 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14496 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14497 inst
.instruction
|= neon_quad (rs
) << 6;
14501 NEON_ENCODE (IMMED
, inst
);
14502 neon_move_immediate ();
14505 neon_dp_fixup (&inst
);
14508 /* Encode instructions of form:
14510 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14511 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14514 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14516 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14517 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14518 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14519 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14520 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14521 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14522 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14523 inst
.instruction
|= neon_logbits (size
) << 20;
14525 neon_dp_fixup (&inst
);
14529 do_neon_dyadic_long (void)
14531 /* FIXME: Type checking for lengthening op. */
14532 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14533 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14534 neon_mixed_length (et
, et
.size
);
14538 do_neon_abal (void)
14540 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14541 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14542 neon_mixed_length (et
, et
.size
);
14546 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14548 if (inst
.operands
[2].isscalar
)
14550 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14551 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14552 NEON_ENCODE (SCALAR
, inst
);
14553 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14557 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14558 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14559 NEON_ENCODE (INTEGER
, inst
);
14560 neon_mixed_length (et
, et
.size
);
14565 do_neon_mac_maybe_scalar_long (void)
14567 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14571 do_neon_dyadic_wide (void)
14573 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14574 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14575 neon_mixed_length (et
, et
.size
);
14579 do_neon_dyadic_narrow (void)
14581 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14582 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14583 /* Operand sign is unimportant, and the U bit is part of the opcode,
14584 so force the operand type to integer. */
14585 et
.type
= NT_integer
;
14586 neon_mixed_length (et
, et
.size
/ 2);
14590 do_neon_mul_sat_scalar_long (void)
14592 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14596 do_neon_vmull (void)
14598 if (inst
.operands
[2].isscalar
)
14599 do_neon_mac_maybe_scalar_long ();
14602 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14603 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14604 if (et
.type
== NT_poly
)
14605 NEON_ENCODE (POLY
, inst
);
14607 NEON_ENCODE (INTEGER
, inst
);
14608 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14609 zero. Should be OK as-is. */
14610 neon_mixed_length (et
, et
.size
);
14617 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14618 struct neon_type_el et
= neon_check_type (3, rs
,
14619 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14620 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14622 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14623 _("shift out of range"));
14624 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14625 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14626 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14627 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14628 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14629 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14630 inst
.instruction
|= neon_quad (rs
) << 6;
14631 inst
.instruction
|= imm
<< 8;
14633 neon_dp_fixup (&inst
);
14639 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14640 struct neon_type_el et
= neon_check_type (2, rs
,
14641 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14642 unsigned op
= (inst
.instruction
>> 7) & 3;
14643 /* N (width of reversed regions) is encoded as part of the bitmask. We
14644 extract it here to check the elements to be reversed are smaller.
14645 Otherwise we'd get a reserved instruction. */
14646 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14647 gas_assert (elsize
!= 0);
14648 constraint (et
.size
>= elsize
,
14649 _("elements must be smaller than reversal region"));
14650 neon_two_same (neon_quad (rs
), 1, et
.size
);
14656 if (inst
.operands
[1].isscalar
)
14658 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14659 struct neon_type_el et
= neon_check_type (2, rs
,
14660 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14661 unsigned sizebits
= et
.size
>> 3;
14662 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14663 int logsize
= neon_logbits (et
.size
);
14664 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14666 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14669 NEON_ENCODE (SCALAR
, inst
);
14670 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14671 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14672 inst
.instruction
|= LOW4 (dm
);
14673 inst
.instruction
|= HI1 (dm
) << 5;
14674 inst
.instruction
|= neon_quad (rs
) << 6;
14675 inst
.instruction
|= x
<< 17;
14676 inst
.instruction
|= sizebits
<< 16;
14678 neon_dp_fixup (&inst
);
14682 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14683 struct neon_type_el et
= neon_check_type (2, rs
,
14684 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14685 /* Duplicate ARM register to lanes of vector. */
14686 NEON_ENCODE (ARMREG
, inst
);
14689 case 8: inst
.instruction
|= 0x400000; break;
14690 case 16: inst
.instruction
|= 0x000020; break;
14691 case 32: inst
.instruction
|= 0x000000; break;
14694 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14695 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14696 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14697 inst
.instruction
|= neon_quad (rs
) << 21;
14698 /* The encoding for this instruction is identical for the ARM and Thumb
14699 variants, except for the condition field. */
14700 do_vfp_cond_or_thumb ();
14704 /* VMOV has particularly many variations. It can be one of:
14705 0. VMOV<c><q> <Qd>, <Qm>
14706 1. VMOV<c><q> <Dd>, <Dm>
14707 (Register operations, which are VORR with Rm = Rn.)
14708 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14709 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14711 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14712 (ARM register to scalar.)
14713 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14714 (Two ARM registers to vector.)
14715 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14716 (Scalar to ARM register.)
14717 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14718 (Vector to two ARM registers.)
14719 8. VMOV.F32 <Sd>, <Sm>
14720 9. VMOV.F64 <Dd>, <Dm>
14721 (VFP register moves.)
14722 10. VMOV.F32 <Sd>, #imm
14723 11. VMOV.F64 <Dd>, #imm
14724 (VFP float immediate load.)
14725 12. VMOV <Rd>, <Sm>
14726 (VFP single to ARM reg.)
14727 13. VMOV <Sd>, <Rm>
14728 (ARM reg to VFP single.)
14729 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14730 (Two ARM regs to two VFP singles.)
14731 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14732 (Two VFP singles to two ARM regs.)
14734 These cases can be disambiguated using neon_select_shape, except cases 1/9
14735 and 3/11 which depend on the operand type too.
14737 All the encoded bits are hardcoded by this function.
14739 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14740 Cases 5, 7 may be used with VFPv2 and above.
14742 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14743 can specify a type where it doesn't make sense to, and is ignored). */
14748 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14749 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14751 struct neon_type_el et
;
14752 const char *ldconst
= 0;
14756 case NS_DD
: /* case 1/9. */
14757 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14758 /* It is not an error here if no type is given. */
14760 if (et
.type
== NT_float
&& et
.size
== 64)
14762 do_vfp_nsyn_opcode ("fcpyd");
14765 /* fall through. */
14767 case NS_QQ
: /* case 0/1. */
14769 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14771 /* The architecture manual I have doesn't explicitly state which
14772 value the U bit should have for register->register moves, but
14773 the equivalent VORR instruction has U = 0, so do that. */
14774 inst
.instruction
= 0x0200110;
14775 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14776 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14777 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14778 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14779 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14780 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14781 inst
.instruction
|= neon_quad (rs
) << 6;
14783 neon_dp_fixup (&inst
);
14787 case NS_DI
: /* case 3/11. */
14788 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14790 if (et
.type
== NT_float
&& et
.size
== 64)
14792 /* case 11 (fconstd). */
14793 ldconst
= "fconstd";
14794 goto encode_fconstd
;
14796 /* fall through. */
14798 case NS_QI
: /* case 2/3. */
14799 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14801 inst
.instruction
= 0x0800010;
14802 neon_move_immediate ();
14803 neon_dp_fixup (&inst
);
14806 case NS_SR
: /* case 4. */
14808 unsigned bcdebits
= 0;
14810 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14811 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14813 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14814 logsize
= neon_logbits (et
.size
);
14816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14818 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14819 && et
.size
!= 32, _(BAD_FPU
));
14820 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14821 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14825 case 8: bcdebits
= 0x8; break;
14826 case 16: bcdebits
= 0x1; break;
14827 case 32: bcdebits
= 0x0; break;
14831 bcdebits
|= x
<< logsize
;
14833 inst
.instruction
= 0xe000b10;
14834 do_vfp_cond_or_thumb ();
14835 inst
.instruction
|= LOW4 (dn
) << 16;
14836 inst
.instruction
|= HI1 (dn
) << 7;
14837 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14838 inst
.instruction
|= (bcdebits
& 3) << 5;
14839 inst
.instruction
|= (bcdebits
>> 2) << 21;
14843 case NS_DRR
: /* case 5 (fmdrr). */
14844 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14847 inst
.instruction
= 0xc400b10;
14848 do_vfp_cond_or_thumb ();
14849 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14850 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14851 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14852 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14855 case NS_RS
: /* case 6. */
14858 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14859 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14860 unsigned abcdebits
= 0;
14862 et
= neon_check_type (2, NS_NULL
,
14863 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14864 logsize
= neon_logbits (et
.size
);
14866 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14868 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14869 && et
.size
!= 32, _(BAD_FPU
));
14870 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14871 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14875 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14876 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14877 case 32: abcdebits
= 0x00; break;
14881 abcdebits
|= x
<< logsize
;
14882 inst
.instruction
= 0xe100b10;
14883 do_vfp_cond_or_thumb ();
14884 inst
.instruction
|= LOW4 (dn
) << 16;
14885 inst
.instruction
|= HI1 (dn
) << 7;
14886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14887 inst
.instruction
|= (abcdebits
& 3) << 5;
14888 inst
.instruction
|= (abcdebits
>> 2) << 21;
14892 case NS_RRD
: /* case 7 (fmrrd). */
14893 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14896 inst
.instruction
= 0xc500b10;
14897 do_vfp_cond_or_thumb ();
14898 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14899 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14900 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14901 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14904 case NS_FF
: /* case 8 (fcpys). */
14905 do_vfp_nsyn_opcode ("fcpys");
14908 case NS_FI
: /* case 10 (fconsts). */
14909 ldconst
= "fconsts";
14911 if (is_quarter_float (inst
.operands
[1].imm
))
14913 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14914 do_vfp_nsyn_opcode (ldconst
);
14917 first_error (_("immediate out of range"));
14920 case NS_RF
: /* case 12 (fmrs). */
14921 do_vfp_nsyn_opcode ("fmrs");
14924 case NS_FR
: /* case 13 (fmsr). */
14925 do_vfp_nsyn_opcode ("fmsr");
14928 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14929 (one of which is a list), but we have parsed four. Do some fiddling to
14930 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14932 case NS_RRFF
: /* case 14 (fmrrs). */
14933 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14934 _("VFP registers must be adjacent"));
14935 inst
.operands
[2].imm
= 2;
14936 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14937 do_vfp_nsyn_opcode ("fmrrs");
14940 case NS_FFRR
: /* case 15 (fmsrr). */
14941 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14942 _("VFP registers must be adjacent"));
14943 inst
.operands
[1] = inst
.operands
[2];
14944 inst
.operands
[2] = inst
.operands
[3];
14945 inst
.operands
[0].imm
= 2;
14946 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14947 do_vfp_nsyn_opcode ("fmsrr");
14956 do_neon_rshift_round_imm (void)
14958 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14959 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14960 int imm
= inst
.operands
[2].imm
;
14962 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14965 inst
.operands
[2].present
= 0;
14970 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14971 _("immediate out of range for shift"));
14972 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14977 do_neon_movl (void)
14979 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14980 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14981 unsigned sizebits
= et
.size
>> 3;
14982 inst
.instruction
|= sizebits
<< 19;
14983 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14989 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14990 struct neon_type_el et
= neon_check_type (2, rs
,
14991 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14992 NEON_ENCODE (INTEGER
, inst
);
14993 neon_two_same (neon_quad (rs
), 1, et
.size
);
14997 do_neon_zip_uzp (void)
14999 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15000 struct neon_type_el et
= neon_check_type (2, rs
,
15001 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15002 if (rs
== NS_DD
&& et
.size
== 32)
15004 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15005 inst
.instruction
= N_MNEM_vtrn
;
15009 neon_two_same (neon_quad (rs
), 1, et
.size
);
15013 do_neon_sat_abs_neg (void)
15015 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15016 struct neon_type_el et
= neon_check_type (2, rs
,
15017 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15018 neon_two_same (neon_quad (rs
), 1, et
.size
);
15022 do_neon_pair_long (void)
15024 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15025 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15026 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15027 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15028 neon_two_same (neon_quad (rs
), 1, et
.size
);
15032 do_neon_recip_est (void)
15034 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15035 struct neon_type_el et
= neon_check_type (2, rs
,
15036 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15037 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15038 neon_two_same (neon_quad (rs
), 1, et
.size
);
15044 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15045 struct neon_type_el et
= neon_check_type (2, rs
,
15046 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15047 neon_two_same (neon_quad (rs
), 1, et
.size
);
15053 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15054 struct neon_type_el et
= neon_check_type (2, rs
,
15055 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15056 neon_two_same (neon_quad (rs
), 1, et
.size
);
15062 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15063 struct neon_type_el et
= neon_check_type (2, rs
,
15064 N_EQK
| N_INT
, N_8
| N_KEY
);
15065 neon_two_same (neon_quad (rs
), 1, et
.size
);
15071 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15072 neon_two_same (neon_quad (rs
), 1, -1);
15076 do_neon_tbl_tbx (void)
15078 unsigned listlenbits
;
15079 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15081 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15083 first_error (_("bad list length for table lookup"));
15087 listlenbits
= inst
.operands
[1].imm
- 1;
15088 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15089 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15090 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15091 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15092 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15093 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15094 inst
.instruction
|= listlenbits
<< 8;
15096 neon_dp_fixup (&inst
);
15100 do_neon_ldm_stm (void)
15102 /* P, U and L bits are part of bitmask. */
15103 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15104 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15106 if (inst
.operands
[1].issingle
)
15108 do_vfp_nsyn_ldm_stm (is_dbmode
);
15112 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15113 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15115 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15116 _("register list must contain at least 1 and at most 16 "
15119 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15120 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15121 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15122 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15124 inst
.instruction
|= offsetbits
;
15126 do_vfp_cond_or_thumb ();
15130 do_neon_ldr_str (void)
15132 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15134 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15135 And is UNPREDICTABLE in thumb mode. */
15137 && inst
.operands
[1].reg
== REG_PC
15138 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15140 if (!thumb_mode
&& warn_on_deprecated
)
15141 as_warn (_("Use of PC here is deprecated"));
15143 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15146 if (inst
.operands
[0].issingle
)
15149 do_vfp_nsyn_opcode ("flds");
15151 do_vfp_nsyn_opcode ("fsts");
15156 do_vfp_nsyn_opcode ("fldd");
15158 do_vfp_nsyn_opcode ("fstd");
15162 /* "interleave" version also handles non-interleaving register VLD1/VST1
15166 do_neon_ld_st_interleave (void)
15168 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15169 N_8
| N_16
| N_32
| N_64
);
15170 unsigned alignbits
= 0;
15172 /* The bits in this table go:
15173 0: register stride of one (0) or two (1)
15174 1,2: register list length, minus one (1, 2, 3, 4).
15175 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15176 We use -1 for invalid entries. */
15177 const int typetable
[] =
15179 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15180 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15181 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15182 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15186 if (et
.type
== NT_invtype
)
15189 if (inst
.operands
[1].immisalign
)
15190 switch (inst
.operands
[1].imm
>> 8)
15192 case 64: alignbits
= 1; break;
15194 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15195 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15196 goto bad_alignment
;
15200 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15201 goto bad_alignment
;
15206 first_error (_("bad alignment"));
15210 inst
.instruction
|= alignbits
<< 4;
15211 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15213 /* Bits [4:6] of the immediate in a list specifier encode register stride
15214 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15215 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15216 up the right value for "type" in a table based on this value and the given
15217 list style, then stick it back. */
15218 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15219 | (((inst
.instruction
>> 8) & 3) << 3);
15221 typebits
= typetable
[idx
];
15223 constraint (typebits
== -1, _("bad list type for instruction"));
15225 inst
.instruction
&= ~0xf00;
15226 inst
.instruction
|= typebits
<< 8;
15229 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15230 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15231 otherwise. The variable arguments are a list of pairs of legal (size, align)
15232 values, terminated with -1. */
15235 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15238 int result
= FAIL
, thissize
, thisalign
;
15240 if (!inst
.operands
[1].immisalign
)
15246 va_start (ap
, do_align
);
15250 thissize
= va_arg (ap
, int);
15251 if (thissize
== -1)
15253 thisalign
= va_arg (ap
, int);
15255 if (size
== thissize
&& align
== thisalign
)
15258 while (result
!= SUCCESS
);
15262 if (result
== SUCCESS
)
15265 first_error (_("unsupported alignment for instruction"));
15271 do_neon_ld_st_lane (void)
15273 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15274 int align_good
, do_align
= 0;
15275 int logsize
= neon_logbits (et
.size
);
15276 int align
= inst
.operands
[1].imm
>> 8;
15277 int n
= (inst
.instruction
>> 8) & 3;
15278 int max_el
= 64 / et
.size
;
15280 if (et
.type
== NT_invtype
)
15283 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15284 _("bad list length"));
15285 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15286 _("scalar index out of range"));
15287 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15289 _("stride of 2 unavailable when element size is 8"));
15293 case 0: /* VLD1 / VST1. */
15294 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15296 if (align_good
== FAIL
)
15300 unsigned alignbits
= 0;
15303 case 16: alignbits
= 0x1; break;
15304 case 32: alignbits
= 0x3; break;
15307 inst
.instruction
|= alignbits
<< 4;
15311 case 1: /* VLD2 / VST2. */
15312 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15314 if (align_good
== FAIL
)
15317 inst
.instruction
|= 1 << 4;
15320 case 2: /* VLD3 / VST3. */
15321 constraint (inst
.operands
[1].immisalign
,
15322 _("can't use alignment with this instruction"));
15325 case 3: /* VLD4 / VST4. */
15326 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15327 16, 64, 32, 64, 32, 128, -1);
15328 if (align_good
== FAIL
)
15332 unsigned alignbits
= 0;
15335 case 8: alignbits
= 0x1; break;
15336 case 16: alignbits
= 0x1; break;
15337 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15340 inst
.instruction
|= alignbits
<< 4;
15347 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15348 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15349 inst
.instruction
|= 1 << (4 + logsize
);
15351 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15352 inst
.instruction
|= logsize
<< 10;
15355 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15358 do_neon_ld_dup (void)
15360 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15361 int align_good
, do_align
= 0;
15363 if (et
.type
== NT_invtype
)
15366 switch ((inst
.instruction
>> 8) & 3)
15368 case 0: /* VLD1. */
15369 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15370 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15371 &do_align
, 16, 16, 32, 32, -1);
15372 if (align_good
== FAIL
)
15374 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15377 case 2: inst
.instruction
|= 1 << 5; break;
15378 default: first_error (_("bad list length")); return;
15380 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15383 case 1: /* VLD2. */
15384 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15385 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15386 if (align_good
== FAIL
)
15388 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15389 _("bad list length"));
15390 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15391 inst
.instruction
|= 1 << 5;
15392 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15395 case 2: /* VLD3. */
15396 constraint (inst
.operands
[1].immisalign
,
15397 _("can't use alignment with this instruction"));
15398 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15399 _("bad list length"));
15400 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15401 inst
.instruction
|= 1 << 5;
15402 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15405 case 3: /* VLD4. */
15407 int align
= inst
.operands
[1].imm
>> 8;
15408 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15409 16, 64, 32, 64, 32, 128, -1);
15410 if (align_good
== FAIL
)
15412 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15413 _("bad list length"));
15414 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15415 inst
.instruction
|= 1 << 5;
15416 if (et
.size
== 32 && align
== 128)
15417 inst
.instruction
|= 0x3 << 6;
15419 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15426 inst
.instruction
|= do_align
<< 4;
15429 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15430 apart from bits [11:4]. */
15433 do_neon_ldx_stx (void)
15435 if (inst
.operands
[1].isreg
)
15436 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15438 switch (NEON_LANE (inst
.operands
[0].imm
))
15440 case NEON_INTERLEAVE_LANES
:
15441 NEON_ENCODE (INTERLV
, inst
);
15442 do_neon_ld_st_interleave ();
15445 case NEON_ALL_LANES
:
15446 NEON_ENCODE (DUP
, inst
);
15451 NEON_ENCODE (LANE
, inst
);
15452 do_neon_ld_st_lane ();
15455 /* L bit comes from bit mask. */
15456 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15457 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15458 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15460 if (inst
.operands
[1].postind
)
15462 int postreg
= inst
.operands
[1].imm
& 0xf;
15463 constraint (!inst
.operands
[1].immisreg
,
15464 _("post-index must be a register"));
15465 constraint (postreg
== 0xd || postreg
== 0xf,
15466 _("bad register for post-index"));
15467 inst
.instruction
|= postreg
;
15469 else if (inst
.operands
[1].writeback
)
15471 inst
.instruction
|= 0xd;
15474 inst
.instruction
|= 0xf;
15477 inst
.instruction
|= 0xf9000000;
15479 inst
.instruction
|= 0xf4000000;
15482 /* Overall per-instruction processing. */
15484 /* We need to be able to fix up arbitrary expressions in some statements.
15485 This is so that we can handle symbols that are an arbitrary distance from
15486 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15487 which returns part of an address in a form which will be valid for
15488 a data instruction. We do this by pushing the expression into a symbol
15489 in the expr_section, and creating a fix for that. */
15492 fix_new_arm (fragS
* frag
,
15506 /* Create an absolute valued symbol, so we have something to
15507 refer to in the object file. Unfortunately for us, gas's
15508 generic expression parsing will already have folded out
15509 any use of .set foo/.type foo %function that may have
15510 been used to set type information of the target location,
15511 that's being specified symbolically. We have to presume
15512 the user knows what they are doing. */
15516 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
15518 symbol
= symbol_find_or_make (name
);
15519 S_SET_SEGMENT (symbol
, absolute_section
);
15520 symbol_set_frag (symbol
, &zero_address_frag
);
15521 S_SET_VALUE (symbol
, exp
->X_add_number
);
15522 exp
->X_op
= O_symbol
;
15523 exp
->X_add_symbol
= symbol
;
15524 exp
->X_add_number
= 0;
15530 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15531 (enum bfd_reloc_code_real
) reloc
);
15535 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15536 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15540 /* Mark whether the fix is to a THUMB instruction, or an ARM
15542 new_fix
->tc_fix_data
= thumb_mode
;
15545 /* Create a frg for an instruction requiring relaxation. */
15547 output_relax_insn (void)
15553 /* The size of the instruction is unknown, so tie the debug info to the
15554 start of the instruction. */
15555 dwarf2_emit_insn (0);
15557 switch (inst
.reloc
.exp
.X_op
)
15560 sym
= inst
.reloc
.exp
.X_add_symbol
;
15561 offset
= inst
.reloc
.exp
.X_add_number
;
15565 offset
= inst
.reloc
.exp
.X_add_number
;
15568 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15572 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15573 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15574 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15577 /* Write a 32-bit thumb instruction to buf. */
15579 put_thumb32_insn (char * buf
, unsigned long insn
)
15581 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15582 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15586 output_inst (const char * str
)
15592 as_bad ("%s -- `%s'", inst
.error
, str
);
15597 output_relax_insn ();
15600 if (inst
.size
== 0)
15603 to
= frag_more (inst
.size
);
15604 /* PR 9814: Record the thumb mode into the current frag so that we know
15605 what type of NOP padding to use, if necessary. We override any previous
15606 setting so that if the mode has changed then the NOPS that we use will
15607 match the encoding of the last instruction in the frag. */
15608 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15610 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15612 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15613 put_thumb32_insn (to
, inst
.instruction
);
15615 else if (inst
.size
> INSN_SIZE
)
15617 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15618 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15619 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15622 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15624 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15625 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15626 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15629 dwarf2_emit_insn (inst
.size
);
15633 output_it_inst (int cond
, int mask
, char * to
)
15635 unsigned long instruction
= 0xbf00;
15638 instruction
|= mask
;
15639 instruction
|= cond
<< 4;
15643 to
= frag_more (2);
15645 dwarf2_emit_insn (2);
15649 md_number_to_chars (to
, instruction
, 2);
15654 /* Tag values used in struct asm_opcode's tag field. */
15657 OT_unconditional
, /* Instruction cannot be conditionalized.
15658 The ARM condition field is still 0xE. */
15659 OT_unconditionalF
, /* Instruction cannot be conditionalized
15660 and carries 0xF in its ARM condition field. */
15661 OT_csuffix
, /* Instruction takes a conditional suffix. */
15662 OT_csuffixF
, /* Some forms of the instruction take a conditional
15663 suffix, others place 0xF where the condition field
15665 OT_cinfix3
, /* Instruction takes a conditional infix,
15666 beginning at character index 3. (In
15667 unified mode, it becomes a suffix.) */
15668 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15669 tsts, cmps, cmns, and teqs. */
15670 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15671 character index 3, even in unified mode. Used for
15672 legacy instructions where suffix and infix forms
15673 may be ambiguous. */
15674 OT_csuf_or_in3
, /* Instruction takes either a conditional
15675 suffix or an infix at character index 3. */
15676 OT_odd_infix_unc
, /* This is the unconditional variant of an
15677 instruction that takes a conditional infix
15678 at an unusual position. In unified mode,
15679 this variant will accept a suffix. */
15680 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15681 are the conditional variants of instructions that
15682 take conditional infixes in unusual positions.
15683 The infix appears at character index
15684 (tag - OT_odd_infix_0). These are not accepted
15685 in unified mode. */
15688 /* Subroutine of md_assemble, responsible for looking up the primary
15689 opcode from the mnemonic the user wrote. STR points to the
15690 beginning of the mnemonic.
15692 This is not simply a hash table lookup, because of conditional
15693 variants. Most instructions have conditional variants, which are
15694 expressed with a _conditional affix_ to the mnemonic. If we were
15695 to encode each conditional variant as a literal string in the opcode
15696 table, it would have approximately 20,000 entries.
15698 Most mnemonics take this affix as a suffix, and in unified syntax,
15699 'most' is upgraded to 'all'. However, in the divided syntax, some
15700 instructions take the affix as an infix, notably the s-variants of
15701 the arithmetic instructions. Of those instructions, all but six
15702 have the infix appear after the third character of the mnemonic.
15704 Accordingly, the algorithm for looking up primary opcodes given
15707 1. Look up the identifier in the opcode table.
15708 If we find a match, go to step U.
15710 2. Look up the last two characters of the identifier in the
15711 conditions table. If we find a match, look up the first N-2
15712 characters of the identifier in the opcode table. If we
15713 find a match, go to step CE.
15715 3. Look up the fourth and fifth characters of the identifier in
15716 the conditions table. If we find a match, extract those
15717 characters from the identifier, and look up the remaining
15718 characters in the opcode table. If we find a match, go
15723 U. Examine the tag field of the opcode structure, in case this is
15724 one of the six instructions with its conditional infix in an
15725 unusual place. If it is, the tag tells us where to find the
15726 infix; look it up in the conditions table and set inst.cond
15727 accordingly. Otherwise, this is an unconditional instruction.
15728 Again set inst.cond accordingly. Return the opcode structure.
15730 CE. Examine the tag field to make sure this is an instruction that
15731 should receive a conditional suffix. If it is not, fail.
15732 Otherwise, set inst.cond from the suffix we already looked up,
15733 and return the opcode structure.
15735 CM. Examine the tag field to make sure this is an instruction that
15736 should receive a conditional infix after the third character.
15737 If it is not, fail. Otherwise, undo the edits to the current
15738 line of input and proceed as for case CE. */
15740 static const struct asm_opcode
*
15741 opcode_lookup (char **str
)
15745 const struct asm_opcode
*opcode
;
15746 const struct asm_cond
*cond
;
15749 /* Scan up to the end of the mnemonic, which must end in white space,
15750 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15751 for (base
= end
= *str
; *end
!= '\0'; end
++)
15752 if (*end
== ' ' || *end
== '.')
15758 /* Handle a possible width suffix and/or Neon type suffix. */
15763 /* The .w and .n suffixes are only valid if the unified syntax is in
15765 if (unified_syntax
&& end
[1] == 'w')
15767 else if (unified_syntax
&& end
[1] == 'n')
15772 inst
.vectype
.elems
= 0;
15774 *str
= end
+ offset
;
15776 if (end
[offset
] == '.')
15778 /* See if we have a Neon type suffix (possible in either unified or
15779 non-unified ARM syntax mode). */
15780 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15783 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15789 /* Look for unaffixed or special-case affixed mnemonic. */
15790 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15795 if (opcode
->tag
< OT_odd_infix_0
)
15797 inst
.cond
= COND_ALWAYS
;
15801 if (warn_on_deprecated
&& unified_syntax
)
15802 as_warn (_("conditional infixes are deprecated in unified syntax"));
15803 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15804 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15807 inst
.cond
= cond
->value
;
15811 /* Cannot have a conditional suffix on a mnemonic of less than two
15813 if (end
- base
< 3)
15816 /* Look for suffixed mnemonic. */
15818 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15819 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15821 if (opcode
&& cond
)
15824 switch (opcode
->tag
)
15826 case OT_cinfix3_legacy
:
15827 /* Ignore conditional suffixes matched on infix only mnemonics. */
15831 case OT_cinfix3_deprecated
:
15832 case OT_odd_infix_unc
:
15833 if (!unified_syntax
)
15835 /* else fall through */
15839 case OT_csuf_or_in3
:
15840 inst
.cond
= cond
->value
;
15843 case OT_unconditional
:
15844 case OT_unconditionalF
:
15846 inst
.cond
= cond
->value
;
15849 /* Delayed diagnostic. */
15850 inst
.error
= BAD_COND
;
15851 inst
.cond
= COND_ALWAYS
;
15860 /* Cannot have a usual-position infix on a mnemonic of less than
15861 six characters (five would be a suffix). */
15862 if (end
- base
< 6)
15865 /* Look for infixed mnemonic in the usual position. */
15867 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15871 memcpy (save
, affix
, 2);
15872 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15873 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15875 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15876 memcpy (affix
, save
, 2);
15879 && (opcode
->tag
== OT_cinfix3
15880 || opcode
->tag
== OT_cinfix3_deprecated
15881 || opcode
->tag
== OT_csuf_or_in3
15882 || opcode
->tag
== OT_cinfix3_legacy
))
15885 if (warn_on_deprecated
&& unified_syntax
15886 && (opcode
->tag
== OT_cinfix3
15887 || opcode
->tag
== OT_cinfix3_deprecated
))
15888 as_warn (_("conditional infixes are deprecated in unified syntax"));
15890 inst
.cond
= cond
->value
;
15897 /* This function generates an initial IT instruction, leaving its block
15898 virtually open for the new instructions. Eventually,
15899 the mask will be updated by now_it_add_mask () each time
15900 a new instruction needs to be included in the IT block.
15901 Finally, the block is closed with close_automatic_it_block ().
15902 The block closure can be requested either from md_assemble (),
15903 a tencode (), or due to a label hook. */
15906 new_automatic_it_block (int cond
)
15908 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15909 now_it
.mask
= 0x18;
15911 now_it
.block_length
= 1;
15912 mapping_state (MAP_THUMB
);
15913 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15916 /* Close an automatic IT block.
15917 See comments in new_automatic_it_block (). */
15920 close_automatic_it_block (void)
15922 now_it
.mask
= 0x10;
15923 now_it
.block_length
= 0;
15926 /* Update the mask of the current automatically-generated IT
15927 instruction. See comments in new_automatic_it_block (). */
15930 now_it_add_mask (int cond
)
15932 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15933 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15934 | ((bitvalue) << (nbit)))
15935 const int resulting_bit
= (cond
& 1);
15937 now_it
.mask
&= 0xf;
15938 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15940 (5 - now_it
.block_length
));
15941 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15943 ((5 - now_it
.block_length
) - 1) );
15944 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15947 #undef SET_BIT_VALUE
15950 /* The IT blocks handling machinery is accessed through the these functions:
15951 it_fsm_pre_encode () from md_assemble ()
15952 set_it_insn_type () optional, from the tencode functions
15953 set_it_insn_type_last () ditto
15954 in_it_block () ditto
15955 it_fsm_post_encode () from md_assemble ()
15956 force_automatic_it_block_close () from label habdling functions
15959 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15960 initializing the IT insn type with a generic initial value depending
15961 on the inst.condition.
15962 2) During the tencode function, two things may happen:
15963 a) The tencode function overrides the IT insn type by
15964 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15965 b) The tencode function queries the IT block state by
15966 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15968 Both set_it_insn_type and in_it_block run the internal FSM state
15969 handling function (handle_it_state), because: a) setting the IT insn
15970 type may incur in an invalid state (exiting the function),
15971 and b) querying the state requires the FSM to be updated.
15972 Specifically we want to avoid creating an IT block for conditional
15973 branches, so it_fsm_pre_encode is actually a guess and we can't
15974 determine whether an IT block is required until the tencode () routine
15975 has decided what type of instruction this actually it.
15976 Because of this, if set_it_insn_type and in_it_block have to be used,
15977 set_it_insn_type has to be called first.
15979 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15980 determines the insn IT type depending on the inst.cond code.
15981 When a tencode () routine encodes an instruction that can be
15982 either outside an IT block, or, in the case of being inside, has to be
15983 the last one, set_it_insn_type_last () will determine the proper
15984 IT instruction type based on the inst.cond code. Otherwise,
15985 set_it_insn_type can be called for overriding that logic or
15986 for covering other cases.
15988 Calling handle_it_state () may not transition the IT block state to
15989 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15990 still queried. Instead, if the FSM determines that the state should
15991 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15992 after the tencode () function: that's what it_fsm_post_encode () does.
15994 Since in_it_block () calls the state handling function to get an
15995 updated state, an error may occur (due to invalid insns combination).
15996 In that case, inst.error is set.
15997 Therefore, inst.error has to be checked after the execution of
15998 the tencode () routine.
16000 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16001 any pending state change (if any) that didn't take place in
16002 handle_it_state () as explained above. */
16005 it_fsm_pre_encode (void)
16007 if (inst
.cond
!= COND_ALWAYS
)
16008 inst
.it_insn_type
= INSIDE_IT_INSN
;
16010 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
16012 now_it
.state_handled
= 0;
16015 /* IT state FSM handling function. */
16018 handle_it_state (void)
16020 now_it
.state_handled
= 1;
16022 switch (now_it
.state
)
16024 case OUTSIDE_IT_BLOCK
:
16025 switch (inst
.it_insn_type
)
16027 case OUTSIDE_IT_INSN
:
16030 case INSIDE_IT_INSN
:
16031 case INSIDE_IT_LAST_INSN
:
16032 if (thumb_mode
== 0)
16035 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
16036 as_tsktsk (_("Warning: conditional outside an IT block"\
16041 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
16042 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
16044 /* Automatically generate the IT instruction. */
16045 new_automatic_it_block (inst
.cond
);
16046 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
16047 close_automatic_it_block ();
16051 inst
.error
= BAD_OUT_IT
;
16057 case IF_INSIDE_IT_LAST_INSN
:
16058 case NEUTRAL_IT_INSN
:
16062 now_it
.state
= MANUAL_IT_BLOCK
;
16063 now_it
.block_length
= 0;
16068 case AUTOMATIC_IT_BLOCK
:
16069 /* Three things may happen now:
16070 a) We should increment current it block size;
16071 b) We should close current it block (closing insn or 4 insns);
16072 c) We should close current it block and start a new one (due
16073 to incompatible conditions or
16074 4 insns-length block reached). */
16076 switch (inst
.it_insn_type
)
16078 case OUTSIDE_IT_INSN
:
16079 /* The closure of the block shall happen immediatelly,
16080 so any in_it_block () call reports the block as closed. */
16081 force_automatic_it_block_close ();
16084 case INSIDE_IT_INSN
:
16085 case INSIDE_IT_LAST_INSN
:
16086 case IF_INSIDE_IT_LAST_INSN
:
16087 now_it
.block_length
++;
16089 if (now_it
.block_length
> 4
16090 || !now_it_compatible (inst
.cond
))
16092 force_automatic_it_block_close ();
16093 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16094 new_automatic_it_block (inst
.cond
);
16098 now_it_add_mask (inst
.cond
);
16101 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16102 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16103 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16104 close_automatic_it_block ();
16107 case NEUTRAL_IT_INSN
:
16108 now_it
.block_length
++;
16110 if (now_it
.block_length
> 4)
16111 force_automatic_it_block_close ();
16113 now_it_add_mask (now_it
.cc
& 1);
16117 close_automatic_it_block ();
16118 now_it
.state
= MANUAL_IT_BLOCK
;
16123 case MANUAL_IT_BLOCK
:
16125 /* Check conditional suffixes. */
16126 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16129 now_it
.mask
&= 0x1f;
16130 is_last
= (now_it
.mask
== 0x10);
16132 switch (inst
.it_insn_type
)
16134 case OUTSIDE_IT_INSN
:
16135 inst
.error
= BAD_NOT_IT
;
16138 case INSIDE_IT_INSN
:
16139 if (cond
!= inst
.cond
)
16141 inst
.error
= BAD_IT_COND
;
16146 case INSIDE_IT_LAST_INSN
:
16147 case IF_INSIDE_IT_LAST_INSN
:
16148 if (cond
!= inst
.cond
)
16150 inst
.error
= BAD_IT_COND
;
16155 inst
.error
= BAD_BRANCH
;
16160 case NEUTRAL_IT_INSN
:
16161 /* The BKPT instruction is unconditional even in an IT block. */
16165 inst
.error
= BAD_IT_IT
;
16176 it_fsm_post_encode (void)
16180 if (!now_it
.state_handled
)
16181 handle_it_state ();
16183 is_last
= (now_it
.mask
== 0x10);
16186 now_it
.state
= OUTSIDE_IT_BLOCK
;
16192 force_automatic_it_block_close (void)
16194 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16196 close_automatic_it_block ();
16197 now_it
.state
= OUTSIDE_IT_BLOCK
;
16205 if (!now_it
.state_handled
)
16206 handle_it_state ();
16208 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16212 md_assemble (char *str
)
16215 const struct asm_opcode
* opcode
;
16217 /* Align the previous label if needed. */
16218 if (last_label_seen
!= NULL
)
16220 symbol_set_frag (last_label_seen
, frag_now
);
16221 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16222 S_SET_SEGMENT (last_label_seen
, now_seg
);
16225 memset (&inst
, '\0', sizeof (inst
));
16226 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16228 opcode
= opcode_lookup (&p
);
16231 /* It wasn't an instruction, but it might be a register alias of
16232 the form alias .req reg, or a Neon .dn/.qn directive. */
16233 if (! create_register_alias (str
, p
)
16234 && ! create_neon_reg_alias (str
, p
))
16235 as_bad (_("bad instruction `%s'"), str
);
16240 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16241 as_warn (_("s suffix on comparison instruction is deprecated"));
16243 /* The value which unconditional instructions should have in place of the
16244 condition field. */
16245 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16249 arm_feature_set variant
;
16251 variant
= cpu_variant
;
16252 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16253 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16254 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16255 /* Check that this instruction is supported for this CPU. */
16256 if (!opcode
->tvariant
16257 || (thumb_mode
== 1
16258 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16260 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16263 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16264 && opcode
->tencode
!= do_t_branch
)
16266 as_bad (_("Thumb does not support conditional execution"));
16270 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16272 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16273 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16274 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16276 /* Two things are addressed here.
16277 1) Implicit require narrow instructions on Thumb-1.
16278 This avoids relaxation accidentally introducing Thumb-2
16280 2) Reject wide instructions in non Thumb-2 cores. */
16281 if (inst
.size_req
== 0)
16283 else if (inst
.size_req
== 4)
16285 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16291 inst
.instruction
= opcode
->tvalue
;
16293 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16295 /* Prepare the it_insn_type for those encodings that don't set
16297 it_fsm_pre_encode ();
16299 opcode
->tencode ();
16301 it_fsm_post_encode ();
16304 if (!(inst
.error
|| inst
.relax
))
16306 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16307 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16308 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16310 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16315 /* Something has gone badly wrong if we try to relax a fixed size
16317 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16319 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16320 *opcode
->tvariant
);
16321 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16322 set those bits when Thumb-2 32-bit instructions are seen. ie.
16323 anything other than bl/blx and v6-M instructions.
16324 This is overly pessimistic for relaxable instructions. */
16325 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16327 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16328 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16329 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16332 check_neon_suffixes
;
16336 mapping_state (MAP_THUMB
);
16339 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16343 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16344 is_bx
= (opcode
->aencode
== do_bx
);
16346 /* Check that this instruction is supported for this CPU. */
16347 if (!(is_bx
&& fix_v4bx
)
16348 && !(opcode
->avariant
&&
16349 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16351 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16356 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16360 inst
.instruction
= opcode
->avalue
;
16361 if (opcode
->tag
== OT_unconditionalF
)
16362 inst
.instruction
|= 0xF << 28;
16364 inst
.instruction
|= inst
.cond
<< 28;
16365 inst
.size
= INSN_SIZE
;
16366 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16368 it_fsm_pre_encode ();
16369 opcode
->aencode ();
16370 it_fsm_post_encode ();
16372 /* Arm mode bx is marked as both v4T and v5 because it's still required
16373 on a hypothetical non-thumb v5 core. */
16375 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16377 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16378 *opcode
->avariant
);
16380 check_neon_suffixes
;
16384 mapping_state (MAP_ARM
);
16389 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16397 check_it_blocks_finished (void)
16402 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16403 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16404 == MANUAL_IT_BLOCK
)
16406 as_warn (_("section '%s' finished with an open IT block."),
16410 if (now_it
.state
== MANUAL_IT_BLOCK
)
16411 as_warn (_("file finished with an open IT block."));
16415 /* Various frobbings of labels and their addresses. */
16418 arm_start_line_hook (void)
16420 last_label_seen
= NULL
;
16424 arm_frob_label (symbolS
* sym
)
16426 last_label_seen
= sym
;
16428 ARM_SET_THUMB (sym
, thumb_mode
);
16430 #if defined OBJ_COFF || defined OBJ_ELF
16431 ARM_SET_INTERWORK (sym
, support_interwork
);
16434 force_automatic_it_block_close ();
16436 /* Note - do not allow local symbols (.Lxxx) to be labelled
16437 as Thumb functions. This is because these labels, whilst
16438 they exist inside Thumb code, are not the entry points for
16439 possible ARM->Thumb calls. Also, these labels can be used
16440 as part of a computed goto or switch statement. eg gcc
16441 can generate code that looks like this:
16443 ldr r2, [pc, .Laaa]
16453 The first instruction loads the address of the jump table.
16454 The second instruction converts a table index into a byte offset.
16455 The third instruction gets the jump address out of the table.
16456 The fourth instruction performs the jump.
16458 If the address stored at .Laaa is that of a symbol which has the
16459 Thumb_Func bit set, then the linker will arrange for this address
16460 to have the bottom bit set, which in turn would mean that the
16461 address computation performed by the third instruction would end
16462 up with the bottom bit set. Since the ARM is capable of unaligned
16463 word loads, the instruction would then load the incorrect address
16464 out of the jump table, and chaos would ensue. */
16465 if (label_is_thumb_function_name
16466 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16467 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16469 /* When the address of a Thumb function is taken the bottom
16470 bit of that address should be set. This will allow
16471 interworking between Arm and Thumb functions to work
16474 THUMB_SET_FUNC (sym
, 1);
16476 label_is_thumb_function_name
= FALSE
;
16479 dwarf2_emit_label (sym
);
16483 arm_data_in_code (void)
16485 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16487 *input_line_pointer
= '/';
16488 input_line_pointer
+= 5;
16489 *input_line_pointer
= 0;
16497 arm_canonicalize_symbol_name (char * name
)
16501 if (thumb_mode
&& (len
= strlen (name
)) > 5
16502 && streq (name
+ len
- 5, "/data"))
16503 *(name
+ len
- 5) = 0;
16508 /* Table of all register names defined by default. The user can
16509 define additional names with .req. Note that all register names
16510 should appear in both upper and lowercase variants. Some registers
16511 also have mixed-case names. */
16513 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16514 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16515 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16516 #define REGSET(p,t) \
16517 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16518 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16519 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16520 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16521 #define REGSETH(p,t) \
16522 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16523 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16524 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16525 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16526 #define REGSET2(p,t) \
16527 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16528 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16529 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16530 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16531 #define SPLRBANK(base,bank,t) \
16532 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16533 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16534 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16535 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16536 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16537 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16539 static const struct reg_entry reg_names
[] =
16541 /* ARM integer registers. */
16542 REGSET(r
, RN
), REGSET(R
, RN
),
16544 /* ATPCS synonyms. */
16545 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16546 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16547 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16549 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16550 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16551 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16553 /* Well-known aliases. */
16554 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16555 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16557 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16558 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16560 /* Coprocessor numbers. */
16561 REGSET(p
, CP
), REGSET(P
, CP
),
16563 /* Coprocessor register numbers. The "cr" variants are for backward
16565 REGSET(c
, CN
), REGSET(C
, CN
),
16566 REGSET(cr
, CN
), REGSET(CR
, CN
),
16568 /* ARM banked registers. */
16569 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16570 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16571 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16572 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16573 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16574 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16575 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16577 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16578 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16579 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16580 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16581 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16582 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16583 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16584 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16586 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16587 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16588 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16589 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16590 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16591 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16592 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16593 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16594 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16596 /* FPA registers. */
16597 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16598 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16600 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16601 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16603 /* VFP SP registers. */
16604 REGSET(s
,VFS
), REGSET(S
,VFS
),
16605 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16607 /* VFP DP Registers. */
16608 REGSET(d
,VFD
), REGSET(D
,VFD
),
16609 /* Extra Neon DP registers. */
16610 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16612 /* Neon QP registers. */
16613 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16615 /* VFP control registers. */
16616 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16617 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16618 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16619 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16620 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16621 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16623 /* Maverick DSP coprocessor registers. */
16624 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16625 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16627 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16628 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16629 REGDEF(dspsc
,0,DSPSC
),
16631 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16632 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16633 REGDEF(DSPSC
,0,DSPSC
),
16635 /* iWMMXt data registers - p0, c0-15. */
16636 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16638 /* iWMMXt control registers - p1, c0-3. */
16639 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16640 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16641 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16642 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16644 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16645 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16646 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16647 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16648 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16650 /* XScale accumulator registers. */
16651 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16657 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16658 within psr_required_here. */
16659 static const struct asm_psr psrs
[] =
16661 /* Backward compatibility notation. Note that "all" is no longer
16662 truly all possible PSR bits. */
16663 {"all", PSR_c
| PSR_f
},
16667 /* Individual flags. */
16673 /* Combinations of flags. */
16674 {"fs", PSR_f
| PSR_s
},
16675 {"fx", PSR_f
| PSR_x
},
16676 {"fc", PSR_f
| PSR_c
},
16677 {"sf", PSR_s
| PSR_f
},
16678 {"sx", PSR_s
| PSR_x
},
16679 {"sc", PSR_s
| PSR_c
},
16680 {"xf", PSR_x
| PSR_f
},
16681 {"xs", PSR_x
| PSR_s
},
16682 {"xc", PSR_x
| PSR_c
},
16683 {"cf", PSR_c
| PSR_f
},
16684 {"cs", PSR_c
| PSR_s
},
16685 {"cx", PSR_c
| PSR_x
},
16686 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16687 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16688 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16689 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16690 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16691 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16692 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16693 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16694 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16695 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16696 {"scf", PSR_s
| PSR_c
| PSR_f
},
16697 {"scx", PSR_s
| PSR_c
| PSR_x
},
16698 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16699 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16700 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16701 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16702 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16703 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16704 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16705 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16706 {"csf", PSR_c
| PSR_s
| PSR_f
},
16707 {"csx", PSR_c
| PSR_s
| PSR_x
},
16708 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16709 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16710 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16711 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16712 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16713 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16714 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16715 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16716 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16717 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16718 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16719 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16720 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16721 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16722 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16723 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16724 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16725 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16726 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16727 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16728 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16729 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16730 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16731 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16732 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16733 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16736 /* Table of V7M psr names. */
16737 static const struct asm_psr v7m_psrs
[] =
16739 {"apsr", 0 }, {"APSR", 0 },
16740 {"iapsr", 1 }, {"IAPSR", 1 },
16741 {"eapsr", 2 }, {"EAPSR", 2 },
16742 {"psr", 3 }, {"PSR", 3 },
16743 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16744 {"ipsr", 5 }, {"IPSR", 5 },
16745 {"epsr", 6 }, {"EPSR", 6 },
16746 {"iepsr", 7 }, {"IEPSR", 7 },
16747 {"msp", 8 }, {"MSP", 8 },
16748 {"psp", 9 }, {"PSP", 9 },
16749 {"primask", 16}, {"PRIMASK", 16},
16750 {"basepri", 17}, {"BASEPRI", 17},
16751 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16752 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16753 {"faultmask", 19}, {"FAULTMASK", 19},
16754 {"control", 20}, {"CONTROL", 20}
16757 /* Table of all shift-in-operand names. */
16758 static const struct asm_shift_name shift_names
[] =
16760 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16761 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16762 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16763 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16764 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16765 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16768 /* Table of all explicit relocation names. */
16770 static struct reloc_entry reloc_names
[] =
16772 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16773 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16774 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16775 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16776 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16777 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16778 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16779 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16780 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16781 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16782 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16783 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16784 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16785 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16786 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16787 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16788 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16789 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16793 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16794 static const struct asm_cond conds
[] =
16798 {"cs", 0x2}, {"hs", 0x2},
16799 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16813 static struct asm_barrier_opt barrier_opt_names
[] =
16815 { "sy", 0xf }, { "SY", 0xf },
16816 { "un", 0x7 }, { "UN", 0x7 },
16817 { "st", 0xe }, { "ST", 0xe },
16818 { "unst", 0x6 }, { "UNST", 0x6 },
16819 { "ish", 0xb }, { "ISH", 0xb },
16820 { "sh", 0xb }, { "SH", 0xb },
16821 { "ishst", 0xa }, { "ISHST", 0xa },
16822 { "shst", 0xa }, { "SHST", 0xa },
16823 { "nsh", 0x7 }, { "NSH", 0x7 },
16824 { "nshst", 0x6 }, { "NSHST", 0x6 },
16825 { "osh", 0x3 }, { "OSH", 0x3 },
16826 { "oshst", 0x2 }, { "OSHST", 0x2 }
16829 /* Table of ARM-format instructions. */
16831 /* Macros for gluing together operand strings. N.B. In all cases
16832 other than OPS0, the trailing OP_stop comes from default
16833 zero-initialization of the unspecified elements of the array. */
16834 #define OPS0() { OP_stop, }
16835 #define OPS1(a) { OP_##a, }
16836 #define OPS2(a,b) { OP_##a,OP_##b, }
16837 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16838 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16839 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16840 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16842 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16843 This is useful when mixing operands for ARM and THUMB, i.e. using the
16844 MIX_ARM_THUMB_OPERANDS macro.
16845 In order to use these macros, prefix the number of operands with _
16847 #define OPS_1(a) { a, }
16848 #define OPS_2(a,b) { a,b, }
16849 #define OPS_3(a,b,c) { a,b,c, }
16850 #define OPS_4(a,b,c,d) { a,b,c,d, }
16851 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16852 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16854 /* These macros abstract out the exact format of the mnemonic table and
16855 save some repeated characters. */
16857 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16858 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16859 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16860 THUMB_VARIANT, do_##ae, do_##te }
16862 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16863 a T_MNEM_xyz enumerator. */
16864 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16865 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16866 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16867 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16869 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16870 infix after the third character. */
16871 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16872 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16873 THUMB_VARIANT, do_##ae, do_##te }
16874 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16875 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16876 THUMB_VARIANT, do_##ae, do_##te }
16877 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16878 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16879 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16880 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16881 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16882 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16883 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16884 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16886 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16887 appear in the condition table. */
16888 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16889 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16890 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16892 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16893 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16894 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16895 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16896 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16897 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16898 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16899 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16900 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16901 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16902 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16903 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16904 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16905 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16906 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16907 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16908 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16909 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16910 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16911 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16913 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16914 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16915 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16916 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16918 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16919 field is still 0xE. Many of the Thumb variants can be executed
16920 conditionally, so this is checked separately. */
16921 #define TUE(mnem, op, top, nops, ops, ae, te) \
16922 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16923 THUMB_VARIANT, do_##ae, do_##te }
16925 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16926 condition code field. */
16927 #define TUF(mnem, op, top, nops, ops, ae, te) \
16928 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16929 THUMB_VARIANT, do_##ae, do_##te }
16931 /* ARM-only variants of all the above. */
16932 #define CE(mnem, op, nops, ops, ae) \
16933 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16935 #define C3(mnem, op, nops, ops, ae) \
16936 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16938 /* Legacy mnemonics that always have conditional infix after the third
16940 #define CL(mnem, op, nops, ops, ae) \
16941 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16942 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16944 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16945 #define cCE(mnem, op, nops, ops, ae) \
16946 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16948 /* Legacy coprocessor instructions where conditional infix and conditional
16949 suffix are ambiguous. For consistency this includes all FPA instructions,
16950 not just the potentially ambiguous ones. */
16951 #define cCL(mnem, op, nops, ops, ae) \
16952 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16953 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16955 /* Coprocessor, takes either a suffix or a position-3 infix
16956 (for an FPA corner case). */
16957 #define C3E(mnem, op, nops, ops, ae) \
16958 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16959 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16961 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16962 { m1 #m2 m3, OPS##nops ops, \
16963 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16964 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16966 #define CM(m1, m2, op, nops, ops, ae) \
16967 xCM_ (m1, , m2, op, nops, ops, ae), \
16968 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16969 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16970 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16971 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16972 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16973 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16974 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16975 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16976 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16977 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16978 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16979 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16980 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16981 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16982 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16983 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16984 xCM_ (m1, le, m2, op, nops, ops, ae), \
16985 xCM_ (m1, al, m2, op, nops, ops, ae)
16987 #define UE(mnem, op, nops, ops, ae) \
16988 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16990 #define UF(mnem, op, nops, ops, ae) \
16991 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16993 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16994 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16995 use the same encoding function for each. */
16996 #define NUF(mnem, op, nops, ops, enc) \
16997 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16998 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17000 /* Neon data processing, version which indirects through neon_enc_tab for
17001 the various overloaded versions of opcodes. */
17002 #define nUF(mnem, op, nops, ops, enc) \
17003 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17004 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17006 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17008 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17009 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17010 THUMB_VARIANT, do_##enc, do_##enc }
17012 #define NCE(mnem, op, nops, ops, enc) \
17013 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17015 #define NCEF(mnem, op, nops, ops, enc) \
17016 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17018 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17019 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17020 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17021 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17023 #define nCE(mnem, op, nops, ops, enc) \
17024 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17026 #define nCEF(mnem, op, nops, ops, enc) \
17027 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17031 static const struct asm_opcode insns
[] =
17033 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17034 #define THUMB_VARIANT &arm_ext_v4t
17035 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17036 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17037 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17038 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17039 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17040 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17041 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17042 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17043 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17044 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17045 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17046 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17047 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17048 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17049 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17050 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17052 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17053 for setting PSR flag bits. They are obsolete in V6 and do not
17054 have Thumb equivalents. */
17055 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17056 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17057 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
17058 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17059 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17060 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
17061 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17062 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17063 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17065 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17066 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17067 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17068 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17070 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17071 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17072 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17074 OP_ADDRGLDR
),ldst
, t_ldst
),
17075 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17077 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17078 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17079 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17080 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17081 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17082 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17084 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17085 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17086 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17087 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17090 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17091 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17092 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17094 /* Thumb-compatibility pseudo ops. */
17095 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17096 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17097 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17098 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17099 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17100 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17101 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17102 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17103 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17104 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17105 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17106 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17108 /* These may simplify to neg. */
17109 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17110 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17112 #undef THUMB_VARIANT
17113 #define THUMB_VARIANT & arm_ext_v6
17115 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17117 /* V1 instructions with no Thumb analogue prior to V6T2. */
17118 #undef THUMB_VARIANT
17119 #define THUMB_VARIANT & arm_ext_v6t2
17121 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17122 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17123 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17125 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17126 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17127 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17128 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17130 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17131 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17133 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17134 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17136 /* V1 instructions with no Thumb analogue at all. */
17137 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17138 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17140 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17141 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17142 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17143 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17144 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17145 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17146 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17147 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17150 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17151 #undef THUMB_VARIANT
17152 #define THUMB_VARIANT & arm_ext_v4t
17154 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17155 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17157 #undef THUMB_VARIANT
17158 #define THUMB_VARIANT & arm_ext_v6t2
17160 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17161 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17163 /* Generic coprocessor instructions. */
17164 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17165 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17166 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17167 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17168 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17169 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17170 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17173 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17175 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17176 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17179 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17180 #undef THUMB_VARIANT
17181 #define THUMB_VARIANT & arm_ext_msr
17183 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17184 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17187 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17188 #undef THUMB_VARIANT
17189 #define THUMB_VARIANT & arm_ext_v6t2
17191 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17192 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17193 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17194 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17195 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17196 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17197 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17198 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17201 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17202 #undef THUMB_VARIANT
17203 #define THUMB_VARIANT & arm_ext_v4t
17205 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17206 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17207 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17208 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17209 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17210 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17213 #define ARM_VARIANT & arm_ext_v4t_5
17215 /* ARM Architecture 4T. */
17216 /* Note: bx (and blx) are required on V5, even if the processor does
17217 not support Thumb. */
17218 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17221 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17222 #undef THUMB_VARIANT
17223 #define THUMB_VARIANT & arm_ext_v5t
17225 /* Note: blx has 2 variants; the .value coded here is for
17226 BLX(2). Only this variant has conditional execution. */
17227 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17228 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17230 #undef THUMB_VARIANT
17231 #define THUMB_VARIANT & arm_ext_v6t2
17233 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17234 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17235 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17236 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17237 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17238 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17239 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17240 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17243 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17244 #undef THUMB_VARIANT
17245 #define THUMB_VARIANT &arm_ext_v5exp
17247 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17248 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17249 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17250 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17252 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17253 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17255 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17256 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17257 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17258 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17260 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17261 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17262 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17263 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17265 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17266 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17268 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17269 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17270 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17271 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17274 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17275 #undef THUMB_VARIANT
17276 #define THUMB_VARIANT &arm_ext_v6t2
17278 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17279 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17281 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17282 ADDRGLDRS
), ldrd
, t_ldstd
),
17284 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17285 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17288 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17290 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17293 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17294 #undef THUMB_VARIANT
17295 #define THUMB_VARIANT & arm_ext_v6
17297 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17298 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17299 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17300 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17301 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17302 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17303 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17304 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17305 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17306 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17308 #undef THUMB_VARIANT
17309 #define THUMB_VARIANT & arm_ext_v6t2
17311 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17312 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17314 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17315 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17317 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17318 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17320 /* ARM V6 not included in V7M. */
17321 #undef THUMB_VARIANT
17322 #define THUMB_VARIANT & arm_ext_v6_notm
17323 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17324 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17325 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17326 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17327 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17328 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17329 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17330 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17331 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17332 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17333 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17334 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17336 /* ARM V6 not included in V7M (eg. integer SIMD). */
17337 #undef THUMB_VARIANT
17338 #define THUMB_VARIANT & arm_ext_v6_dsp
17339 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17340 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17341 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17342 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17343 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17344 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17345 /* Old name for QASX. */
17346 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17347 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17348 /* Old name for QSAX. */
17349 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17350 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17351 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17352 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17353 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17354 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17355 /* Old name for SASX. */
17356 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17357 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17358 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17359 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17360 /* Old name for SHASX. */
17361 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17362 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17363 /* Old name for SHSAX. */
17364 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17365 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17366 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17367 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17368 /* Old name for SSAX. */
17369 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17370 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17371 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17372 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17373 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17374 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17375 /* Old name for UASX. */
17376 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17377 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17378 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17379 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17380 /* Old name for UHASX. */
17381 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17382 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17383 /* Old name for UHSAX. */
17384 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17385 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17386 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17387 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17388 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17389 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17390 /* Old name for UQASX. */
17391 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17392 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17393 /* Old name for UQSAX. */
17394 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17395 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17396 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17397 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17398 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17399 /* Old name for USAX. */
17400 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17401 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17402 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17403 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17404 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17405 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17406 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17407 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17408 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17409 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17410 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17411 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17412 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17413 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17414 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17415 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17416 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17417 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17418 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17419 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17420 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17421 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17422 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17423 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17424 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17425 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17426 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17427 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17428 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17429 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17430 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17431 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17432 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17433 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17436 #define ARM_VARIANT & arm_ext_v6k
17437 #undef THUMB_VARIANT
17438 #define THUMB_VARIANT & arm_ext_v6k
17440 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17441 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17442 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17443 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17445 #undef THUMB_VARIANT
17446 #define THUMB_VARIANT & arm_ext_v6_notm
17447 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17449 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17450 RRnpcb
), strexd
, t_strexd
),
17452 #undef THUMB_VARIANT
17453 #define THUMB_VARIANT & arm_ext_v6t2
17454 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17456 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17458 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17460 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17462 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17465 #define ARM_VARIANT & arm_ext_sec
17466 #undef THUMB_VARIANT
17467 #define THUMB_VARIANT & arm_ext_sec
17469 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17472 #define ARM_VARIANT & arm_ext_virt
17473 #undef THUMB_VARIANT
17474 #define THUMB_VARIANT & arm_ext_virt
17476 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17477 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17480 #define ARM_VARIANT & arm_ext_v6t2
17481 #undef THUMB_VARIANT
17482 #define THUMB_VARIANT & arm_ext_v6t2
17484 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17485 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17486 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17487 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17489 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17490 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17491 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17492 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17494 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17495 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17496 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17497 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17499 /* Thumb-only instructions. */
17501 #define ARM_VARIANT NULL
17502 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17503 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17505 /* ARM does not really have an IT instruction, so always allow it.
17506 The opcode is copied from Thumb in order to allow warnings in
17507 -mimplicit-it=[never | arm] modes. */
17509 #define ARM_VARIANT & arm_ext_v1
17511 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17512 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17513 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17514 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17515 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17516 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17517 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17518 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17519 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17520 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17521 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17522 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17523 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17524 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17525 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17526 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17527 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17528 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17530 /* Thumb2 only instructions. */
17532 #define ARM_VARIANT NULL
17534 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17535 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17536 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17537 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17538 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17539 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17541 /* Hardware division instructions. */
17543 #define ARM_VARIANT & arm_ext_adiv
17544 #undef THUMB_VARIANT
17545 #define THUMB_VARIANT & arm_ext_div
17547 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17548 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17550 /* ARM V6M/V7 instructions. */
17552 #define ARM_VARIANT & arm_ext_barrier
17553 #undef THUMB_VARIANT
17554 #define THUMB_VARIANT & arm_ext_barrier
17556 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17557 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17558 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17560 /* ARM V7 instructions. */
17562 #define ARM_VARIANT & arm_ext_v7
17563 #undef THUMB_VARIANT
17564 #define THUMB_VARIANT & arm_ext_v7
17566 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17567 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17570 #define ARM_VARIANT & arm_ext_mp
17571 #undef THUMB_VARIANT
17572 #define THUMB_VARIANT & arm_ext_mp
17574 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17577 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17579 cCE("wfs", e200110
, 1, (RR
), rd
),
17580 cCE("rfs", e300110
, 1, (RR
), rd
),
17581 cCE("wfc", e400110
, 1, (RR
), rd
),
17582 cCE("rfc", e500110
, 1, (RR
), rd
),
17584 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17585 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17586 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17587 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17589 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17590 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17591 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17592 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17594 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17595 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17596 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17597 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17598 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17599 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17600 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17601 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17602 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17603 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17604 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17605 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17607 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17608 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17609 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17610 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17611 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17612 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17613 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17614 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17615 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17616 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17617 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17618 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17620 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17621 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17622 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17623 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17624 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17625 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17626 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17627 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17628 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17629 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17630 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17631 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17633 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17634 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17635 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17636 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17637 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17638 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17639 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17640 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17641 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17642 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17643 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17644 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17646 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17647 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17648 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17649 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17650 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17651 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17652 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17653 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17654 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17655 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17656 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17657 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17659 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17660 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17661 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17662 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17663 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17664 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17665 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17666 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17667 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17668 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17669 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17670 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17672 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17673 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17674 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17675 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17676 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17677 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17678 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17679 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17680 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17681 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17682 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17683 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17685 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17686 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17687 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17688 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17689 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17690 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17691 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17692 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17693 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17694 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17695 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17696 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17698 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17699 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17700 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17701 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17702 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17703 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17704 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17705 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17706 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17707 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17708 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17709 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17711 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17712 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17713 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17714 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17715 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17716 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17717 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17718 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17719 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17720 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17721 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17722 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17724 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17725 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17726 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17727 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17728 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17729 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17730 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17731 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17732 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17733 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17734 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17735 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17737 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17738 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17739 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17740 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17741 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17742 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17743 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17744 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17745 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17746 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17747 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17748 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17750 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17751 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17752 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17753 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17754 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17755 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17756 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17757 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17758 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17759 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17760 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17761 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17763 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17764 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17765 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17766 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17767 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17768 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17769 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17770 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17771 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17772 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17773 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17774 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17776 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17777 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17778 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17779 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17780 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17781 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17782 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17783 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17784 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17785 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17786 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17787 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17789 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17790 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17791 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17792 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17793 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17794 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17795 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17796 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17797 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17798 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17799 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17800 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17802 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17803 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17804 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17805 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17806 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17807 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17808 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17809 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17810 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17811 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17812 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17813 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17815 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17816 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17817 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17818 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17819 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17820 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17821 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17822 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17823 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17824 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17825 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17826 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17828 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17829 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17830 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17831 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17832 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17833 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17834 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17835 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17836 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17837 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17838 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17839 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17841 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17842 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17843 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17844 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17845 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17846 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17847 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17848 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17849 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17850 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17851 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17852 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17854 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17855 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17856 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17857 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17858 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17859 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17860 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17861 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17862 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17863 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17864 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17865 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17867 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17868 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17869 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17870 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17871 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17872 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17873 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17874 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17875 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17876 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17877 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17878 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17880 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17881 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17882 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17883 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17884 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17885 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17886 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17887 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17888 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17889 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17890 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17891 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17893 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17894 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17895 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17896 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17897 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17898 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17899 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17900 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17901 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17902 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17903 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17904 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17906 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17907 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17908 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17909 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17910 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17911 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17912 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17913 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17914 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17915 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17916 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17917 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17919 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17920 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17921 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17922 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17923 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17924 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17925 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17926 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17927 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17928 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17929 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17930 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17932 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17933 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17934 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17935 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17936 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17937 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17938 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17939 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17940 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17941 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17942 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17943 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17945 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17946 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17947 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17948 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17949 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17950 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17951 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17952 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17953 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17954 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17955 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17956 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17958 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17959 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17960 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17961 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17962 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17963 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17964 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17965 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17966 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17967 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17968 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17969 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17971 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17972 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17973 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17974 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17976 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17977 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17978 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17979 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17980 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17981 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17982 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17983 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17984 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17985 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17986 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17987 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17989 /* The implementation of the FIX instruction is broken on some
17990 assemblers, in that it accepts a precision specifier as well as a
17991 rounding specifier, despite the fact that this is meaningless.
17992 To be more compatible, we accept it as well, though of course it
17993 does not set any bits. */
17994 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17995 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17996 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17997 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17998 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17999 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
18000 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
18001 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
18002 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
18003 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
18004 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
18005 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
18006 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
18008 /* Instructions that were new with the real FPA, call them V2. */
18010 #define ARM_VARIANT & fpu_fpa_ext_v2
18012 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18013 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18014 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18015 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18016 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18017 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18020 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18022 /* Moves and type conversions. */
18023 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18024 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
18025 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
18026 cCE("fmstat", ef1fa10
, 0, (), noargs
),
18027 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
18028 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
18029 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18030 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18031 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18032 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18033 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18034 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18035 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
18036 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
18038 /* Memory operations. */
18039 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18040 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18041 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18042 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18043 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18044 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18045 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18046 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18047 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18048 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18049 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18050 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18051 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18052 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18053 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18054 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18055 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18056 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18058 /* Monadic operations. */
18059 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18060 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18061 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18063 /* Dyadic operations. */
18064 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18065 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18066 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18067 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18068 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18069 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18070 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18071 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18072 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18075 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18076 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
18077 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18078 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
18080 /* Double precision load/store are still present on single precision
18081 implementations. */
18082 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18083 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18084 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18085 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18086 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18087 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18088 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18089 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18090 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18091 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18094 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18096 /* Moves and type conversions. */
18097 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18098 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18099 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18100 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18101 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18102 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18103 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18104 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18105 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18106 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18107 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18108 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18109 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18111 /* Monadic operations. */
18112 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18113 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18114 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18116 /* Dyadic operations. */
18117 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18118 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18119 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18120 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18121 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18122 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18123 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18124 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18125 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18128 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18129 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18130 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18131 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18134 #define ARM_VARIANT & fpu_vfp_ext_v2
18136 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18137 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18138 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18139 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18141 /* Instructions which may belong to either the Neon or VFP instruction sets.
18142 Individual encoder functions perform additional architecture checks. */
18144 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18145 #undef THUMB_VARIANT
18146 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18148 /* These mnemonics are unique to VFP. */
18149 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18150 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18151 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18152 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18153 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18154 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18155 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18156 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18157 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18158 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18160 /* Mnemonics shared by Neon and VFP. */
18161 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18162 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18163 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18165 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18166 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18168 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18169 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18171 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18172 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18173 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18174 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18175 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18176 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18177 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18178 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18180 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
18181 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18182 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18183 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18186 /* NOTE: All VMOV encoding is special-cased! */
18187 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18188 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18190 #undef THUMB_VARIANT
18191 #define THUMB_VARIANT & fpu_neon_ext_v1
18193 #define ARM_VARIANT & fpu_neon_ext_v1
18195 /* Data processing with three registers of the same length. */
18196 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18197 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18198 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18199 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18200 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18201 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18202 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18203 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18204 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18205 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18206 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18207 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18208 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18209 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18210 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18211 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18212 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18213 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18214 /* If not immediate, fall back to neon_dyadic_i64_su.
18215 shl_imm should accept I8 I16 I32 I64,
18216 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18217 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18218 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18219 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18220 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18221 /* Logic ops, types optional & ignored. */
18222 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18223 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18224 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18225 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18226 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18227 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18228 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18229 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18230 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18231 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18232 /* Bitfield ops, untyped. */
18233 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18234 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18235 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18236 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18237 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18238 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18239 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18240 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18241 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18242 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18243 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18244 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18245 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18246 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18247 back to neon_dyadic_if_su. */
18248 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18249 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18250 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18251 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18252 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18253 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18254 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18255 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18256 /* Comparison. Type I8 I16 I32 F32. */
18257 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18258 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18259 /* As above, D registers only. */
18260 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18261 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18262 /* Int and float variants, signedness unimportant. */
18263 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18264 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18265 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18266 /* Add/sub take types I8 I16 I32 I64 F32. */
18267 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18268 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18269 /* vtst takes sizes 8, 16, 32. */
18270 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18271 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18272 /* VMUL takes I8 I16 I32 F32 P8. */
18273 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18274 /* VQD{R}MULH takes S16 S32. */
18275 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18276 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18277 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18278 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18279 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18280 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18281 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18282 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18283 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18284 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18285 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18286 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18287 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18288 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18289 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18290 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18292 /* Two address, int/float. Types S8 S16 S32 F32. */
18293 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18294 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18296 /* Data processing with two registers and a shift amount. */
18297 /* Right shifts, and variants with rounding.
18298 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18299 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18300 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18301 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18302 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18303 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18304 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18305 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18306 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18307 /* Shift and insert. Sizes accepted 8 16 32 64. */
18308 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18309 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18310 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18311 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18312 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18313 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18314 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18315 /* Right shift immediate, saturating & narrowing, with rounding variants.
18316 Types accepted S16 S32 S64 U16 U32 U64. */
18317 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18318 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18319 /* As above, unsigned. Types accepted S16 S32 S64. */
18320 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18321 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18322 /* Right shift narrowing. Types accepted I16 I32 I64. */
18323 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18324 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18325 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18326 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18327 /* CVT with optional immediate for fixed-point variant. */
18328 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18330 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18331 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18333 /* Data processing, three registers of different lengths. */
18334 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18335 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18336 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18337 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18338 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18339 /* If not scalar, fall back to neon_dyadic_long.
18340 Vector types as above, scalar types S16 S32 U16 U32. */
18341 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18342 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18343 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18344 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18345 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18346 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18347 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18348 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18349 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18350 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18351 /* Saturating doubling multiplies. Types S16 S32. */
18352 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18353 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18354 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18355 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18356 S16 S32 U16 U32. */
18357 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18359 /* Extract. Size 8. */
18360 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18361 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18363 /* Two registers, miscellaneous. */
18364 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18365 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18366 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18367 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18368 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18369 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18370 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18371 /* Vector replicate. Sizes 8 16 32. */
18372 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18373 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18374 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18375 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18376 /* VMOVN. Types I16 I32 I64. */
18377 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18378 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18379 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18380 /* VQMOVUN. Types S16 S32 S64. */
18381 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18382 /* VZIP / VUZP. Sizes 8 16 32. */
18383 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18384 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18385 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18386 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18387 /* VQABS / VQNEG. Types S8 S16 S32. */
18388 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18389 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18390 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18391 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18392 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18393 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18394 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18395 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18396 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18397 /* Reciprocal estimates. Types U32 F32. */
18398 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18399 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18400 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18401 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18402 /* VCLS. Types S8 S16 S32. */
18403 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18404 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18405 /* VCLZ. Types I8 I16 I32. */
18406 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18407 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18408 /* VCNT. Size 8. */
18409 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18410 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18411 /* Two address, untyped. */
18412 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18413 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18414 /* VTRN. Sizes 8 16 32. */
18415 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18416 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18418 /* Table lookup. Size 8. */
18419 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18420 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18422 #undef THUMB_VARIANT
18423 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18425 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18427 /* Neon element/structure load/store. */
18428 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18429 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18430 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18431 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18432 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18433 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18434 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18435 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18437 #undef THUMB_VARIANT
18438 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18440 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18441 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18442 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18443 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18444 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18445 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18446 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18447 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18448 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18449 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18451 #undef THUMB_VARIANT
18452 #define THUMB_VARIANT & fpu_vfp_ext_v3
18454 #define ARM_VARIANT & fpu_vfp_ext_v3
18456 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18457 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18458 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18459 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18460 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18461 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18462 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18463 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18464 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18467 #define ARM_VARIANT &fpu_vfp_ext_fma
18468 #undef THUMB_VARIANT
18469 #define THUMB_VARIANT &fpu_vfp_ext_fma
18470 /* Mnemonics shared by Neon and VFP. These are included in the
18471 VFP FMA variant; NEON and VFP FMA always includes the NEON
18472 FMA instructions. */
18473 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18474 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18475 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18476 the v form should always be used. */
18477 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18478 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18479 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18480 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18481 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18482 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18484 #undef THUMB_VARIANT
18486 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18488 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18489 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18490 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18491 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18492 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18493 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18494 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18495 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18498 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18500 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18501 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18502 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18503 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18504 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18505 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18506 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18507 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18508 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18509 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18510 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18511 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18512 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18513 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18514 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18515 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18516 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18517 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18518 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18519 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18520 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18521 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18522 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18523 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18524 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18525 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18526 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18527 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18528 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18529 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18530 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18531 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18532 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18533 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18534 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18535 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18536 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18537 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18538 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18539 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18540 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18541 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18542 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18543 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18544 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18545 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18546 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18547 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18548 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18549 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18550 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18551 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18552 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18553 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18554 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18555 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18556 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18557 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18558 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18559 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18560 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18561 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18562 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18563 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18564 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18565 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18566 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18567 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18568 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18569 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18570 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18571 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18572 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18573 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18574 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18575 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18576 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18577 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18578 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18579 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18580 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18581 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18582 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18583 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18584 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18585 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18586 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18587 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18588 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18589 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18590 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18591 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18592 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18593 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18594 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18595 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18596 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18597 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18598 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18599 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18600 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18601 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18602 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18603 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18604 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18605 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18606 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18607 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18608 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18609 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18610 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18611 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18612 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18613 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18614 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18615 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18616 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18617 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18618 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18619 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18620 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18621 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18622 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18623 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18624 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18625 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18626 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18627 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18628 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18629 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18630 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18631 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18632 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18633 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18634 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18635 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18636 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18637 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18638 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18639 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18640 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18641 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18642 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18643 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18644 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18645 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18646 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18647 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18648 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18649 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18650 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18651 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18652 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18653 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18654 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18655 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18656 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18657 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18658 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18659 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18660 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18661 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18664 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18666 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18667 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18668 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18669 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18670 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18671 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18672 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18673 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18674 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18675 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18676 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18677 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18678 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18679 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18680 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18681 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18682 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18683 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18684 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18685 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18686 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18687 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18688 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18689 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18690 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18691 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18692 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18693 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18694 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18695 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18696 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18697 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18698 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18699 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18700 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18701 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18702 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18703 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18704 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18705 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18706 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18707 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18708 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18709 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18710 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18711 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18712 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18713 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18714 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18715 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18716 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18717 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18718 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18719 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18720 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18721 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18722 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18725 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18727 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18728 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18729 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18730 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18731 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18732 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18733 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18734 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18735 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18736 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18737 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18738 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18739 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18740 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18741 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18742 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18743 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18744 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18745 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18746 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18747 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18748 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18749 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18750 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18751 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18752 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18753 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18754 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18755 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18756 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18757 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18758 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18759 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18760 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18761 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18762 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18763 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18764 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18765 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18766 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18767 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18768 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18769 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18770 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18771 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18772 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18773 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18774 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18775 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18776 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18777 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18778 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18779 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18780 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18781 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18782 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18783 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18784 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18785 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18786 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18787 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18788 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18789 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18790 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18791 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18792 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18793 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18794 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18795 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18796 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18797 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18798 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18799 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18800 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18801 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18802 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18805 #undef THUMB_VARIANT
18832 /* MD interface: bits in the object file. */
18834 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18835 for use in the a.out file, and stores them in the array pointed to by buf.
18836 This knows about the endian-ness of the target machine and does
18837 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18838 2 (short) and 4 (long) Floating numbers are put out as a series of
18839 LITTLENUMS (shorts, here at least). */
18842 md_number_to_chars (char * buf
, valueT val
, int n
)
18844 if (target_big_endian
)
18845 number_to_chars_bigendian (buf
, val
, n
);
18847 number_to_chars_littleendian (buf
, val
, n
);
18851 md_chars_to_number (char * buf
, int n
)
18854 unsigned char * where
= (unsigned char *) buf
;
18856 if (target_big_endian
)
18861 result
|= (*where
++ & 255);
18869 result
|= (where
[n
] & 255);
18876 /* MD interface: Sections. */
18878 /* Estimate the size of a frag before relaxing. Assume everything fits in
18882 md_estimate_size_before_relax (fragS
* fragp
,
18883 segT segtype ATTRIBUTE_UNUSED
)
18889 /* Convert a machine dependent frag. */
18892 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18894 unsigned long insn
;
18895 unsigned long old_op
;
18903 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18905 old_op
= bfd_get_16(abfd
, buf
);
18906 if (fragp
->fr_symbol
)
18908 exp
.X_op
= O_symbol
;
18909 exp
.X_add_symbol
= fragp
->fr_symbol
;
18913 exp
.X_op
= O_constant
;
18915 exp
.X_add_number
= fragp
->fr_offset
;
18916 opcode
= fragp
->fr_subtype
;
18919 case T_MNEM_ldr_pc
:
18920 case T_MNEM_ldr_pc2
:
18921 case T_MNEM_ldr_sp
:
18922 case T_MNEM_str_sp
:
18929 if (fragp
->fr_var
== 4)
18931 insn
= THUMB_OP32 (opcode
);
18932 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18934 insn
|= (old_op
& 0x700) << 4;
18938 insn
|= (old_op
& 7) << 12;
18939 insn
|= (old_op
& 0x38) << 13;
18941 insn
|= 0x00000c00;
18942 put_thumb32_insn (buf
, insn
);
18943 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18947 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18949 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18952 if (fragp
->fr_var
== 4)
18954 insn
= THUMB_OP32 (opcode
);
18955 insn
|= (old_op
& 0xf0) << 4;
18956 put_thumb32_insn (buf
, insn
);
18957 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18961 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18962 exp
.X_add_number
-= 4;
18970 if (fragp
->fr_var
== 4)
18972 int r0off
= (opcode
== T_MNEM_mov
18973 || opcode
== T_MNEM_movs
) ? 0 : 8;
18974 insn
= THUMB_OP32 (opcode
);
18975 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18976 insn
|= (old_op
& 0x700) << r0off
;
18977 put_thumb32_insn (buf
, insn
);
18978 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18982 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18987 if (fragp
->fr_var
== 4)
18989 insn
= THUMB_OP32(opcode
);
18990 put_thumb32_insn (buf
, insn
);
18991 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18994 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18998 if (fragp
->fr_var
== 4)
19000 insn
= THUMB_OP32(opcode
);
19001 insn
|= (old_op
& 0xf00) << 14;
19002 put_thumb32_insn (buf
, insn
);
19003 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
19006 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
19009 case T_MNEM_add_sp
:
19010 case T_MNEM_add_pc
:
19011 case T_MNEM_inc_sp
:
19012 case T_MNEM_dec_sp
:
19013 if (fragp
->fr_var
== 4)
19015 /* ??? Choose between add and addw. */
19016 insn
= THUMB_OP32 (opcode
);
19017 insn
|= (old_op
& 0xf0) << 4;
19018 put_thumb32_insn (buf
, insn
);
19019 if (opcode
== T_MNEM_add_pc
)
19020 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
19022 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19025 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19033 if (fragp
->fr_var
== 4)
19035 insn
= THUMB_OP32 (opcode
);
19036 insn
|= (old_op
& 0xf0) << 4;
19037 insn
|= (old_op
& 0xf) << 16;
19038 put_thumb32_insn (buf
, insn
);
19039 if (insn
& (1 << 20))
19040 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19042 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19045 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19051 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
19052 (enum bfd_reloc_code_real
) reloc_type
);
19053 fixp
->fx_file
= fragp
->fr_file
;
19054 fixp
->fx_line
= fragp
->fr_line
;
19055 fragp
->fr_fix
+= fragp
->fr_var
;
19058 /* Return the size of a relaxable immediate operand instruction.
19059 SHIFT and SIZE specify the form of the allowable immediate. */
19061 relax_immediate (fragS
*fragp
, int size
, int shift
)
19067 /* ??? Should be able to do better than this. */
19068 if (fragp
->fr_symbol
)
19071 low
= (1 << shift
) - 1;
19072 mask
= (1 << (shift
+ size
)) - (1 << shift
);
19073 offset
= fragp
->fr_offset
;
19074 /* Force misaligned offsets to 32-bit variant. */
19077 if (offset
& ~mask
)
19082 /* Get the address of a symbol during relaxation. */
19084 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19090 sym
= fragp
->fr_symbol
;
19091 sym_frag
= symbol_get_frag (sym
);
19092 know (S_GET_SEGMENT (sym
) != absolute_section
19093 || sym_frag
== &zero_address_frag
);
19094 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19096 /* If frag has yet to be reached on this pass, assume it will
19097 move by STRETCH just as we did. If this is not so, it will
19098 be because some frag between grows, and that will force
19102 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19106 /* Adjust stretch for any alignment frag. Note that if have
19107 been expanding the earlier code, the symbol may be
19108 defined in what appears to be an earlier frag. FIXME:
19109 This doesn't handle the fr_subtype field, which specifies
19110 a maximum number of bytes to skip when doing an
19112 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19114 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19117 stretch
= - ((- stretch
)
19118 & ~ ((1 << (int) f
->fr_offset
) - 1));
19120 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19132 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19135 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19140 /* Assume worst case for symbols not known to be in the same section. */
19141 if (fragp
->fr_symbol
== NULL
19142 || !S_IS_DEFINED (fragp
->fr_symbol
)
19143 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19144 || S_IS_WEAK (fragp
->fr_symbol
))
19147 val
= relaxed_symbol_addr (fragp
, stretch
);
19148 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19149 addr
= (addr
+ 4) & ~3;
19150 /* Force misaligned targets to 32-bit variant. */
19154 if (val
< 0 || val
> 1020)
19159 /* Return the size of a relaxable add/sub immediate instruction. */
19161 relax_addsub (fragS
*fragp
, asection
*sec
)
19166 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19167 op
= bfd_get_16(sec
->owner
, buf
);
19168 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19169 return relax_immediate (fragp
, 8, 0);
19171 return relax_immediate (fragp
, 3, 0);
19175 /* Return the size of a relaxable branch instruction. BITS is the
19176 size of the offset field in the narrow instruction. */
19179 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19185 /* Assume worst case for symbols not known to be in the same section. */
19186 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19187 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19188 || S_IS_WEAK (fragp
->fr_symbol
))
19192 if (S_IS_DEFINED (fragp
->fr_symbol
)
19193 && ARM_IS_FUNC (fragp
->fr_symbol
))
19196 /* PR 12532. Global symbols with default visibility might
19197 be preempted, so do not relax relocations to them. */
19198 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19199 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19203 val
= relaxed_symbol_addr (fragp
, stretch
);
19204 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19207 /* Offset is a signed value *2 */
19209 if (val
>= limit
|| val
< -limit
)
19215 /* Relax a machine dependent frag. This returns the amount by which
19216 the current size of the frag should change. */
19219 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19224 oldsize
= fragp
->fr_var
;
19225 switch (fragp
->fr_subtype
)
19227 case T_MNEM_ldr_pc2
:
19228 newsize
= relax_adr (fragp
, sec
, stretch
);
19230 case T_MNEM_ldr_pc
:
19231 case T_MNEM_ldr_sp
:
19232 case T_MNEM_str_sp
:
19233 newsize
= relax_immediate (fragp
, 8, 2);
19237 newsize
= relax_immediate (fragp
, 5, 2);
19241 newsize
= relax_immediate (fragp
, 5, 1);
19245 newsize
= relax_immediate (fragp
, 5, 0);
19248 newsize
= relax_adr (fragp
, sec
, stretch
);
19254 newsize
= relax_immediate (fragp
, 8, 0);
19257 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19260 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19262 case T_MNEM_add_sp
:
19263 case T_MNEM_add_pc
:
19264 newsize
= relax_immediate (fragp
, 8, 2);
19266 case T_MNEM_inc_sp
:
19267 case T_MNEM_dec_sp
:
19268 newsize
= relax_immediate (fragp
, 7, 2);
19274 newsize
= relax_addsub (fragp
, sec
);
19280 fragp
->fr_var
= newsize
;
19281 /* Freeze wide instructions that are at or before the same location as
19282 in the previous pass. This avoids infinite loops.
19283 Don't freeze them unconditionally because targets may be artificially
19284 misaligned by the expansion of preceding frags. */
19285 if (stretch
<= 0 && newsize
> 2)
19287 md_convert_frag (sec
->owner
, sec
, fragp
);
19291 return newsize
- oldsize
;
19294 /* Round up a section size to the appropriate boundary. */
19297 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19300 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19301 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19303 /* For a.out, force the section size to be aligned. If we don't do
19304 this, BFD will align it for us, but it will not write out the
19305 final bytes of the section. This may be a bug in BFD, but it is
19306 easier to fix it here since that is how the other a.out targets
19310 align
= bfd_get_section_alignment (stdoutput
, segment
);
19311 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19318 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19319 of an rs_align_code fragment. */
19322 arm_handle_align (fragS
* fragP
)
19324 static char const arm_noop
[2][2][4] =
19327 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19328 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19331 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19332 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19335 static char const thumb_noop
[2][2][2] =
19338 {0xc0, 0x46}, /* LE */
19339 {0x46, 0xc0}, /* BE */
19342 {0x00, 0xbf}, /* LE */
19343 {0xbf, 0x00} /* BE */
19346 static char const wide_thumb_noop
[2][4] =
19347 { /* Wide Thumb-2 */
19348 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19349 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19352 unsigned bytes
, fix
, noop_size
;
19355 const char *narrow_noop
= NULL
;
19360 if (fragP
->fr_type
!= rs_align_code
)
19363 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19364 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19367 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19368 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19370 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19372 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19374 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19376 narrow_noop
= thumb_noop
[1][target_big_endian
];
19377 noop
= wide_thumb_noop
[target_big_endian
];
19380 noop
= thumb_noop
[0][target_big_endian
];
19388 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19389 [target_big_endian
];
19396 fragP
->fr_var
= noop_size
;
19398 if (bytes
& (noop_size
- 1))
19400 fix
= bytes
& (noop_size
- 1);
19402 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19404 memset (p
, 0, fix
);
19411 if (bytes
& noop_size
)
19413 /* Insert a narrow noop. */
19414 memcpy (p
, narrow_noop
, noop_size
);
19416 bytes
-= noop_size
;
19420 /* Use wide noops for the remainder */
19424 while (bytes
>= noop_size
)
19426 memcpy (p
, noop
, noop_size
);
19428 bytes
-= noop_size
;
19432 fragP
->fr_fix
+= fix
;
19435 /* Called from md_do_align. Used to create an alignment
19436 frag in a code section. */
19439 arm_frag_align_code (int n
, int max
)
19443 /* We assume that there will never be a requirement
19444 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19445 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19450 _("alignments greater than %d bytes not supported in .text sections."),
19451 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19452 as_fatal ("%s", err_msg
);
19455 p
= frag_var (rs_align_code
,
19456 MAX_MEM_FOR_RS_ALIGN_CODE
,
19458 (relax_substateT
) max
,
19465 /* Perform target specific initialisation of a frag.
19466 Note - despite the name this initialisation is not done when the frag
19467 is created, but only when its type is assigned. A frag can be created
19468 and used a long time before its type is set, so beware of assuming that
19469 this initialisationis performed first. */
19473 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19475 /* Record whether this frag is in an ARM or a THUMB area. */
19476 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19479 #else /* OBJ_ELF is defined. */
19481 arm_init_frag (fragS
* fragP
, int max_chars
)
19483 /* If the current ARM vs THUMB mode has not already
19484 been recorded into this frag then do so now. */
19485 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19487 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19489 /* Record a mapping symbol for alignment frags. We will delete this
19490 later if the alignment ends up empty. */
19491 switch (fragP
->fr_type
)
19494 case rs_align_test
:
19496 mapping_state_2 (MAP_DATA
, max_chars
);
19498 case rs_align_code
:
19499 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19507 /* When we change sections we need to issue a new mapping symbol. */
19510 arm_elf_change_section (void)
19512 /* Link an unlinked unwind index table section to the .text section. */
19513 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19514 && elf_linked_to_section (now_seg
) == NULL
)
19515 elf_linked_to_section (now_seg
) = text_section
;
19519 arm_elf_section_type (const char * str
, size_t len
)
19521 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19522 return SHT_ARM_EXIDX
;
19527 /* Code to deal with unwinding tables. */
19529 static void add_unwind_adjustsp (offsetT
);
19531 /* Generate any deferred unwind frame offset. */
19534 flush_pending_unwind (void)
19538 offset
= unwind
.pending_offset
;
19539 unwind
.pending_offset
= 0;
19541 add_unwind_adjustsp (offset
);
19544 /* Add an opcode to this list for this function. Two-byte opcodes should
19545 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19549 add_unwind_opcode (valueT op
, int length
)
19551 /* Add any deferred stack adjustment. */
19552 if (unwind
.pending_offset
)
19553 flush_pending_unwind ();
19555 unwind
.sp_restored
= 0;
19557 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19559 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19560 if (unwind
.opcodes
)
19561 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19562 unwind
.opcode_alloc
);
19564 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19569 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19571 unwind
.opcode_count
++;
19575 /* Add unwind opcodes to adjust the stack pointer. */
19578 add_unwind_adjustsp (offsetT offset
)
19582 if (offset
> 0x200)
19584 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19589 /* Long form: 0xb2, uleb128. */
19590 /* This might not fit in a word so add the individual bytes,
19591 remembering the list is built in reverse order. */
19592 o
= (valueT
) ((offset
- 0x204) >> 2);
19594 add_unwind_opcode (0, 1);
19596 /* Calculate the uleb128 encoding of the offset. */
19600 bytes
[n
] = o
& 0x7f;
19606 /* Add the insn. */
19608 add_unwind_opcode (bytes
[n
- 1], 1);
19609 add_unwind_opcode (0xb2, 1);
19611 else if (offset
> 0x100)
19613 /* Two short opcodes. */
19614 add_unwind_opcode (0x3f, 1);
19615 op
= (offset
- 0x104) >> 2;
19616 add_unwind_opcode (op
, 1);
19618 else if (offset
> 0)
19620 /* Short opcode. */
19621 op
= (offset
- 4) >> 2;
19622 add_unwind_opcode (op
, 1);
19624 else if (offset
< 0)
19627 while (offset
> 0x100)
19629 add_unwind_opcode (0x7f, 1);
19632 op
= ((offset
- 4) >> 2) | 0x40;
19633 add_unwind_opcode (op
, 1);
19637 /* Finish the list of unwind opcodes for this function. */
19639 finish_unwind_opcodes (void)
19643 if (unwind
.fp_used
)
19645 /* Adjust sp as necessary. */
19646 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19647 flush_pending_unwind ();
19649 /* After restoring sp from the frame pointer. */
19650 op
= 0x90 | unwind
.fp_reg
;
19651 add_unwind_opcode (op
, 1);
19654 flush_pending_unwind ();
19658 /* Start an exception table entry. If idx is nonzero this is an index table
19662 start_unwind_section (const segT text_seg
, int idx
)
19664 const char * text_name
;
19665 const char * prefix
;
19666 const char * prefix_once
;
19667 const char * group_name
;
19671 size_t sec_name_len
;
19678 prefix
= ELF_STRING_ARM_unwind
;
19679 prefix_once
= ELF_STRING_ARM_unwind_once
;
19680 type
= SHT_ARM_EXIDX
;
19684 prefix
= ELF_STRING_ARM_unwind_info
;
19685 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19686 type
= SHT_PROGBITS
;
19689 text_name
= segment_name (text_seg
);
19690 if (streq (text_name
, ".text"))
19693 if (strncmp (text_name
, ".gnu.linkonce.t.",
19694 strlen (".gnu.linkonce.t.")) == 0)
19696 prefix
= prefix_once
;
19697 text_name
+= strlen (".gnu.linkonce.t.");
19700 prefix_len
= strlen (prefix
);
19701 text_len
= strlen (text_name
);
19702 sec_name_len
= prefix_len
+ text_len
;
19703 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19704 memcpy (sec_name
, prefix
, prefix_len
);
19705 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19706 sec_name
[prefix_len
+ text_len
] = '\0';
19712 /* Handle COMDAT group. */
19713 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19715 group_name
= elf_group_name (text_seg
);
19716 if (group_name
== NULL
)
19718 as_bad (_("Group section `%s' has no group signature"),
19719 segment_name (text_seg
));
19720 ignore_rest_of_line ();
19723 flags
|= SHF_GROUP
;
19727 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19729 /* Set the section link for index tables. */
19731 elf_linked_to_section (now_seg
) = text_seg
;
19735 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19736 personality routine data. Returns zero, or the index table value for
19737 and inline entry. */
19740 create_unwind_entry (int have_data
)
19745 /* The current word of data. */
19747 /* The number of bytes left in this word. */
19750 finish_unwind_opcodes ();
19752 /* Remember the current text section. */
19753 unwind
.saved_seg
= now_seg
;
19754 unwind
.saved_subseg
= now_subseg
;
19756 start_unwind_section (now_seg
, 0);
19758 if (unwind
.personality_routine
== NULL
)
19760 if (unwind
.personality_index
== -2)
19763 as_bad (_("handlerdata in cantunwind frame"));
19764 return 1; /* EXIDX_CANTUNWIND. */
19767 /* Use a default personality routine if none is specified. */
19768 if (unwind
.personality_index
== -1)
19770 if (unwind
.opcode_count
> 3)
19771 unwind
.personality_index
= 1;
19773 unwind
.personality_index
= 0;
19776 /* Space for the personality routine entry. */
19777 if (unwind
.personality_index
== 0)
19779 if (unwind
.opcode_count
> 3)
19780 as_bad (_("too many unwind opcodes for personality routine 0"));
19784 /* All the data is inline in the index table. */
19787 while (unwind
.opcode_count
> 0)
19789 unwind
.opcode_count
--;
19790 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19794 /* Pad with "finish" opcodes. */
19796 data
= (data
<< 8) | 0xb0;
19803 /* We get two opcodes "free" in the first word. */
19804 size
= unwind
.opcode_count
- 2;
19807 /* An extra byte is required for the opcode count. */
19808 size
= unwind
.opcode_count
+ 1;
19810 size
= (size
+ 3) >> 2;
19812 as_bad (_("too many unwind opcodes"));
19814 frag_align (2, 0, 0);
19815 record_alignment (now_seg
, 2);
19816 unwind
.table_entry
= expr_build_dot ();
19818 /* Allocate the table entry. */
19819 ptr
= frag_more ((size
<< 2) + 4);
19820 where
= frag_now_fix () - ((size
<< 2) + 4);
19822 switch (unwind
.personality_index
)
19825 /* ??? Should this be a PLT generating relocation? */
19826 /* Custom personality routine. */
19827 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19828 BFD_RELOC_ARM_PREL31
);
19833 /* Set the first byte to the number of additional words. */
19838 /* ABI defined personality routines. */
19840 /* Three opcodes bytes are packed into the first word. */
19847 /* The size and first two opcode bytes go in the first word. */
19848 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19853 /* Should never happen. */
19857 /* Pack the opcodes into words (MSB first), reversing the list at the same
19859 while (unwind
.opcode_count
> 0)
19863 md_number_to_chars (ptr
, data
, 4);
19868 unwind
.opcode_count
--;
19870 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19873 /* Finish off the last word. */
19876 /* Pad with "finish" opcodes. */
19878 data
= (data
<< 8) | 0xb0;
19880 md_number_to_chars (ptr
, data
, 4);
19885 /* Add an empty descriptor if there is no user-specified data. */
19886 ptr
= frag_more (4);
19887 md_number_to_chars (ptr
, 0, 4);
19894 /* Initialize the DWARF-2 unwind information for this procedure. */
19897 tc_arm_frame_initial_instructions (void)
19899 cfi_add_CFA_def_cfa (REG_SP
, 0);
19901 #endif /* OBJ_ELF */
19903 /* Convert REGNAME to a DWARF-2 register number. */
19906 tc_arm_regname_to_dw2regnum (char *regname
)
19908 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19918 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19922 exp
.X_op
= O_secrel
;
19923 exp
.X_add_symbol
= symbol
;
19924 exp
.X_add_number
= 0;
19925 emit_expr (&exp
, size
);
19929 /* MD interface: Symbol and relocation handling. */
19931 /* Return the address within the segment that a PC-relative fixup is
19932 relative to. For ARM, PC-relative fixups applied to instructions
19933 are generally relative to the location of the fixup plus 8 bytes.
19934 Thumb branches are offset by 4, and Thumb loads relative to PC
19935 require special handling. */
19938 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19940 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19942 /* If this is pc-relative and we are going to emit a relocation
19943 then we just want to put out any pipeline compensation that the linker
19944 will need. Otherwise we want to use the calculated base.
19945 For WinCE we skip the bias for externals as well, since this
19946 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19948 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19949 || (arm_force_relocation (fixP
)
19951 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19957 switch (fixP
->fx_r_type
)
19959 /* PC relative addressing on the Thumb is slightly odd as the
19960 bottom two bits of the PC are forced to zero for the
19961 calculation. This happens *after* application of the
19962 pipeline offset. However, Thumb adrl already adjusts for
19963 this, so we need not do it again. */
19964 case BFD_RELOC_ARM_THUMB_ADD
:
19967 case BFD_RELOC_ARM_THUMB_OFFSET
:
19968 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19969 case BFD_RELOC_ARM_T32_ADD_PC12
:
19970 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19971 return (base
+ 4) & ~3;
19973 /* Thumb branches are simply offset by +4. */
19974 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19975 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19976 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19977 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19978 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19981 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19983 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19984 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19985 && ARM_IS_FUNC (fixP
->fx_addsy
)
19986 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19987 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19990 /* BLX is like branches above, but forces the low two bits of PC to
19992 case BFD_RELOC_THUMB_PCREL_BLX
:
19994 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19995 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
19996 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19997 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19998 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19999 return (base
+ 4) & ~3;
20001 /* ARM mode branches are offset by +8. However, the Windows CE
20002 loader expects the relocation not to take this into account. */
20003 case BFD_RELOC_ARM_PCREL_BLX
:
20005 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20006 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20007 && ARM_IS_FUNC (fixP
->fx_addsy
)
20008 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20009 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20012 case BFD_RELOC_ARM_PCREL_CALL
:
20014 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20015 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20016 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20017 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20018 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20021 case BFD_RELOC_ARM_PCREL_BRANCH
:
20022 case BFD_RELOC_ARM_PCREL_JUMP
:
20023 case BFD_RELOC_ARM_PLT32
:
20025 /* When handling fixups immediately, because we have already
20026 discovered the value of a symbol, or the address of the frag involved
20027 we must account for the offset by +8, as the OS loader will never see the reloc.
20028 see fixup_segment() in write.c
20029 The S_IS_EXTERNAL test handles the case of global symbols.
20030 Those need the calculated base, not just the pipe compensation the linker will need. */
20032 && fixP
->fx_addsy
!= NULL
20033 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20034 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
20042 /* ARM mode loads relative to PC are also offset by +8. Unlike
20043 branches, the Windows CE loader *does* expect the relocation
20044 to take this into account. */
20045 case BFD_RELOC_ARM_OFFSET_IMM
:
20046 case BFD_RELOC_ARM_OFFSET_IMM8
:
20047 case BFD_RELOC_ARM_HWLITERAL
:
20048 case BFD_RELOC_ARM_LITERAL
:
20049 case BFD_RELOC_ARM_CP_OFF_IMM
:
20053 /* Other PC-relative relocations are un-offset. */
20059 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20060 Otherwise we have no need to default values of symbols. */
20063 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
20066 if (name
[0] == '_' && name
[1] == 'G'
20067 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
20071 if (symbol_find (name
))
20072 as_bad (_("GOT already in the symbol table"));
20074 GOT_symbol
= symbol_new (name
, undefined_section
,
20075 (valueT
) 0, & zero_address_frag
);
20085 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20086 computed as two separate immediate values, added together. We
20087 already know that this value cannot be computed by just one ARM
20090 static unsigned int
20091 validate_immediate_twopart (unsigned int val
,
20092 unsigned int * highpart
)
20097 for (i
= 0; i
< 32; i
+= 2)
20098 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20104 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20106 else if (a
& 0xff0000)
20108 if (a
& 0xff000000)
20110 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20114 gas_assert (a
& 0xff000000);
20115 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20118 return (a
& 0xff) | (i
<< 7);
20125 validate_offset_imm (unsigned int val
, int hwse
)
20127 if ((hwse
&& val
> 255) || val
> 4095)
20132 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20133 negative immediate constant by altering the instruction. A bit of
20138 by inverting the second operand, and
20141 by negating the second operand. */
20144 negate_data_op (unsigned long * instruction
,
20145 unsigned long value
)
20148 unsigned long negated
, inverted
;
20150 negated
= encode_arm_immediate (-value
);
20151 inverted
= encode_arm_immediate (~value
);
20153 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20156 /* First negates. */
20157 case OPCODE_SUB
: /* ADD <-> SUB */
20158 new_inst
= OPCODE_ADD
;
20163 new_inst
= OPCODE_SUB
;
20167 case OPCODE_CMP
: /* CMP <-> CMN */
20168 new_inst
= OPCODE_CMN
;
20173 new_inst
= OPCODE_CMP
;
20177 /* Now Inverted ops. */
20178 case OPCODE_MOV
: /* MOV <-> MVN */
20179 new_inst
= OPCODE_MVN
;
20184 new_inst
= OPCODE_MOV
;
20188 case OPCODE_AND
: /* AND <-> BIC */
20189 new_inst
= OPCODE_BIC
;
20194 new_inst
= OPCODE_AND
;
20198 case OPCODE_ADC
: /* ADC <-> SBC */
20199 new_inst
= OPCODE_SBC
;
20204 new_inst
= OPCODE_ADC
;
20208 /* We cannot do anything. */
20213 if (value
== (unsigned) FAIL
)
20216 *instruction
&= OPCODE_MASK
;
20217 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20221 /* Like negate_data_op, but for Thumb-2. */
20223 static unsigned int
20224 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20228 unsigned int negated
, inverted
;
20230 negated
= encode_thumb32_immediate (-value
);
20231 inverted
= encode_thumb32_immediate (~value
);
20233 rd
= (*instruction
>> 8) & 0xf;
20234 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20237 /* ADD <-> SUB. Includes CMP <-> CMN. */
20238 case T2_OPCODE_SUB
:
20239 new_inst
= T2_OPCODE_ADD
;
20243 case T2_OPCODE_ADD
:
20244 new_inst
= T2_OPCODE_SUB
;
20248 /* ORR <-> ORN. Includes MOV <-> MVN. */
20249 case T2_OPCODE_ORR
:
20250 new_inst
= T2_OPCODE_ORN
;
20254 case T2_OPCODE_ORN
:
20255 new_inst
= T2_OPCODE_ORR
;
20259 /* AND <-> BIC. TST has no inverted equivalent. */
20260 case T2_OPCODE_AND
:
20261 new_inst
= T2_OPCODE_BIC
;
20268 case T2_OPCODE_BIC
:
20269 new_inst
= T2_OPCODE_AND
;
20274 case T2_OPCODE_ADC
:
20275 new_inst
= T2_OPCODE_SBC
;
20279 case T2_OPCODE_SBC
:
20280 new_inst
= T2_OPCODE_ADC
;
20284 /* We cannot do anything. */
20289 if (value
== (unsigned int)FAIL
)
20292 *instruction
&= T2_OPCODE_MASK
;
20293 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20297 /* Read a 32-bit thumb instruction from buf. */
20298 static unsigned long
20299 get_thumb32_insn (char * buf
)
20301 unsigned long insn
;
20302 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20303 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20309 /* We usually want to set the low bit on the address of thumb function
20310 symbols. In particular .word foo - . should have the low bit set.
20311 Generic code tries to fold the difference of two symbols to
20312 a constant. Prevent this and force a relocation when the first symbols
20313 is a thumb function. */
20316 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20318 if (op
== O_subtract
20319 && l
->X_op
== O_symbol
20320 && r
->X_op
== O_symbol
20321 && THUMB_IS_FUNC (l
->X_add_symbol
))
20323 l
->X_op
= O_subtract
;
20324 l
->X_op_symbol
= r
->X_add_symbol
;
20325 l
->X_add_number
-= r
->X_add_number
;
20329 /* Process as normal. */
20333 /* Encode Thumb2 unconditional branches and calls. The encoding
20334 for the 2 are identical for the immediate values. */
20337 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20339 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20342 addressT S
, I1
, I2
, lo
, hi
;
20344 S
= (value
>> 24) & 0x01;
20345 I1
= (value
>> 23) & 0x01;
20346 I2
= (value
>> 22) & 0x01;
20347 hi
= (value
>> 12) & 0x3ff;
20348 lo
= (value
>> 1) & 0x7ff;
20349 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20350 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20351 newval
|= (S
<< 10) | hi
;
20352 newval2
&= ~T2I1I2MASK
;
20353 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20354 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20355 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20359 md_apply_fix (fixS
* fixP
,
20363 offsetT value
= * valP
;
20365 unsigned int newimm
;
20366 unsigned long temp
;
20368 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20370 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20372 /* Note whether this will delete the relocation. */
20374 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20377 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20378 consistency with the behaviour on 32-bit hosts. Remember value
20380 value
&= 0xffffffff;
20381 value
^= 0x80000000;
20382 value
-= 0x80000000;
20385 fixP
->fx_addnumber
= value
;
20387 /* Same treatment for fixP->fx_offset. */
20388 fixP
->fx_offset
&= 0xffffffff;
20389 fixP
->fx_offset
^= 0x80000000;
20390 fixP
->fx_offset
-= 0x80000000;
20392 switch (fixP
->fx_r_type
)
20394 case BFD_RELOC_NONE
:
20395 /* This will need to go in the object file. */
20399 case BFD_RELOC_ARM_IMMEDIATE
:
20400 /* We claim that this fixup has been processed here,
20401 even if in fact we generate an error because we do
20402 not have a reloc for it, so tc_gen_reloc will reject it. */
20405 if (fixP
->fx_addsy
)
20407 const char *msg
= 0;
20409 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20410 msg
= _("undefined symbol %s used as an immediate value");
20411 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20412 msg
= _("symbol %s is in a different section");
20413 else if (S_IS_WEAK (fixP
->fx_addsy
))
20414 msg
= _("symbol %s is weak and may be overridden later");
20418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20419 msg
, S_GET_NAME (fixP
->fx_addsy
));
20424 newimm
= encode_arm_immediate (value
);
20425 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20427 /* If the instruction will fail, see if we can fix things up by
20428 changing the opcode. */
20429 if (newimm
== (unsigned int) FAIL
20430 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20432 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20433 _("invalid constant (%lx) after fixup"),
20434 (unsigned long) value
);
20438 newimm
|= (temp
& 0xfffff000);
20439 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20442 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20444 unsigned int highpart
= 0;
20445 unsigned int newinsn
= 0xe1a00000; /* nop. */
20447 if (fixP
->fx_addsy
)
20449 const char *msg
= 0;
20451 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20452 msg
= _("undefined symbol %s used as an immediate value");
20453 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20454 msg
= _("symbol %s is in a different section");
20455 else if (S_IS_WEAK (fixP
->fx_addsy
))
20456 msg
= _("symbol %s is weak and may be overridden later");
20460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20461 msg
, S_GET_NAME (fixP
->fx_addsy
));
20466 newimm
= encode_arm_immediate (value
);
20467 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20469 /* If the instruction will fail, see if we can fix things up by
20470 changing the opcode. */
20471 if (newimm
== (unsigned int) FAIL
20472 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20474 /* No ? OK - try using two ADD instructions to generate
20476 newimm
= validate_immediate_twopart (value
, & highpart
);
20478 /* Yes - then make sure that the second instruction is
20480 if (newimm
!= (unsigned int) FAIL
)
20482 /* Still No ? Try using a negated value. */
20483 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20484 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20485 /* Otherwise - give up. */
20488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20489 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20494 /* Replace the first operand in the 2nd instruction (which
20495 is the PC) with the destination register. We have
20496 already added in the PC in the first instruction and we
20497 do not want to do it again. */
20498 newinsn
&= ~ 0xf0000;
20499 newinsn
|= ((newinsn
& 0x0f000) << 4);
20502 newimm
|= (temp
& 0xfffff000);
20503 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20505 highpart
|= (newinsn
& 0xfffff000);
20506 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20510 case BFD_RELOC_ARM_OFFSET_IMM
:
20511 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20514 case BFD_RELOC_ARM_LITERAL
:
20520 if (validate_offset_imm (value
, 0) == FAIL
)
20522 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20524 _("invalid literal constant: pool needs to be closer"));
20526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20527 _("bad immediate value for offset (%ld)"),
20532 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20534 newval
&= 0xfffff000;
20537 newval
&= 0xff7ff000;
20538 newval
|= value
| (sign
? INDEX_UP
: 0);
20540 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20543 case BFD_RELOC_ARM_OFFSET_IMM8
:
20544 case BFD_RELOC_ARM_HWLITERAL
:
20550 if (validate_offset_imm (value
, 1) == FAIL
)
20552 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20554 _("invalid literal constant: pool needs to be closer"));
20556 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20561 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20563 newval
&= 0xfffff0f0;
20566 newval
&= 0xff7ff0f0;
20567 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20569 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20572 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20573 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20575 _("bad immediate value for offset (%ld)"), (long) value
);
20578 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20580 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20583 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20584 /* This is a complicated relocation used for all varieties of Thumb32
20585 load/store instruction with immediate offset:
20587 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20588 *4, optional writeback(W)
20589 (doubleword load/store)
20591 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20592 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20593 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20594 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20595 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20597 Uppercase letters indicate bits that are already encoded at
20598 this point. Lowercase letters are our problem. For the
20599 second block of instructions, the secondary opcode nybble
20600 (bits 8..11) is present, and bit 23 is zero, even if this is
20601 a PC-relative operation. */
20602 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20604 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20606 if ((newval
& 0xf0000000) == 0xe0000000)
20608 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20610 newval
|= (1 << 23);
20613 if (value
% 4 != 0)
20615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20616 _("offset not a multiple of 4"));
20622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20623 _("offset out of range"));
20628 else if ((newval
& 0x000f0000) == 0x000f0000)
20630 /* PC-relative, 12-bit offset. */
20632 newval
|= (1 << 23);
20637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20638 _("offset out of range"));
20643 else if ((newval
& 0x00000100) == 0x00000100)
20645 /* Writeback: 8-bit, +/- offset. */
20647 newval
|= (1 << 9);
20652 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20653 _("offset out of range"));
20658 else if ((newval
& 0x00000f00) == 0x00000e00)
20660 /* T-instruction: positive 8-bit offset. */
20661 if (value
< 0 || value
> 0xff)
20663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20664 _("offset out of range"));
20672 /* Positive 12-bit or negative 8-bit offset. */
20676 newval
|= (1 << 23);
20686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20687 _("offset out of range"));
20694 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20695 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20698 case BFD_RELOC_ARM_SHIFT_IMM
:
20699 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20700 if (((unsigned long) value
) > 32
20702 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20705 _("shift expression is too large"));
20710 /* Shifts of zero must be done as lsl. */
20712 else if (value
== 32)
20714 newval
&= 0xfffff07f;
20715 newval
|= (value
& 0x1f) << 7;
20716 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20719 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20720 case BFD_RELOC_ARM_T32_ADD_IMM
:
20721 case BFD_RELOC_ARM_T32_IMM12
:
20722 case BFD_RELOC_ARM_T32_ADD_PC12
:
20723 /* We claim that this fixup has been processed here,
20724 even if in fact we generate an error because we do
20725 not have a reloc for it, so tc_gen_reloc will reject it. */
20729 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20732 _("undefined symbol %s used as an immediate value"),
20733 S_GET_NAME (fixP
->fx_addsy
));
20737 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20739 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20742 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20743 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20745 newimm
= encode_thumb32_immediate (value
);
20746 if (newimm
== (unsigned int) FAIL
)
20747 newimm
= thumb32_negate_data_op (&newval
, value
);
20749 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20750 && newimm
== (unsigned int) FAIL
)
20752 /* Turn add/sum into addw/subw. */
20753 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20754 newval
= (newval
& 0xfeffffff) | 0x02000000;
20755 /* No flat 12-bit imm encoding for addsw/subsw. */
20756 if ((newval
& 0x00100000) == 0)
20758 /* 12 bit immediate for addw/subw. */
20762 newval
^= 0x00a00000;
20765 newimm
= (unsigned int) FAIL
;
20771 if (newimm
== (unsigned int)FAIL
)
20773 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20774 _("invalid constant (%lx) after fixup"),
20775 (unsigned long) value
);
20779 newval
|= (newimm
& 0x800) << 15;
20780 newval
|= (newimm
& 0x700) << 4;
20781 newval
|= (newimm
& 0x0ff);
20783 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20784 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20787 case BFD_RELOC_ARM_SMC
:
20788 if (((unsigned long) value
) > 0xffff)
20789 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20790 _("invalid smc expression"));
20791 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20792 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20793 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20796 case BFD_RELOC_ARM_HVC
:
20797 if (((unsigned long) value
) > 0xffff)
20798 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20799 _("invalid hvc expression"));
20800 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20801 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20802 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20805 case BFD_RELOC_ARM_SWI
:
20806 if (fixP
->tc_fix_data
!= 0)
20808 if (((unsigned long) value
) > 0xff)
20809 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20810 _("invalid swi expression"));
20811 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20813 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20817 if (((unsigned long) value
) > 0x00ffffff)
20818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20819 _("invalid swi expression"));
20820 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20822 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20826 case BFD_RELOC_ARM_MULTI
:
20827 if (((unsigned long) value
) > 0xffff)
20828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20829 _("invalid expression in load/store multiple"));
20830 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20831 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20835 case BFD_RELOC_ARM_PCREL_CALL
:
20837 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20839 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20840 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20841 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20842 /* Flip the bl to blx. This is a simple flip
20843 bit here because we generate PCREL_CALL for
20844 unconditional bls. */
20846 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20847 newval
= newval
| 0x10000000;
20848 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20854 goto arm_branch_common
;
20856 case BFD_RELOC_ARM_PCREL_JUMP
:
20857 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20859 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20860 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20861 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20863 /* This would map to a bl<cond>, b<cond>,
20864 b<always> to a Thumb function. We
20865 need to force a relocation for this particular
20867 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20871 case BFD_RELOC_ARM_PLT32
:
20873 case BFD_RELOC_ARM_PCREL_BRANCH
:
20875 goto arm_branch_common
;
20877 case BFD_RELOC_ARM_PCREL_BLX
:
20880 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20882 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20883 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20884 && ARM_IS_FUNC (fixP
->fx_addsy
))
20886 /* Flip the blx to a bl and warn. */
20887 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20888 newval
= 0xeb000000;
20889 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20890 _("blx to '%s' an ARM ISA state function changed to bl"),
20892 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20898 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20899 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20903 /* We are going to store value (shifted right by two) in the
20904 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20905 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20906 also be be clear. */
20908 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20909 _("misaligned branch destination"));
20910 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20911 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20913 _("branch out of range"));
20915 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20917 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20918 newval
|= (value
>> 2) & 0x00ffffff;
20919 /* Set the H bit on BLX instructions. */
20923 newval
|= 0x01000000;
20925 newval
&= ~0x01000000;
20927 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20931 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20932 /* CBZ can only branch forward. */
20934 /* Attempts to use CBZ to branch to the next instruction
20935 (which, strictly speaking, are prohibited) will be turned into
20938 FIXME: It may be better to remove the instruction completely and
20939 perform relaxation. */
20942 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20943 newval
= 0xbf00; /* NOP encoding T1 */
20944 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20950 _("branch out of range"));
20952 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20954 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20955 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20956 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20961 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20962 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20964 _("branch out of range"));
20966 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20968 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20969 newval
|= (value
& 0x1ff) >> 1;
20970 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20974 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20975 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20976 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20977 _("branch out of range"));
20979 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20981 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20982 newval
|= (value
& 0xfff) >> 1;
20983 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20987 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20989 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20990 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20991 && ARM_IS_FUNC (fixP
->fx_addsy
)
20992 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20994 /* Force a relocation for a branch 20 bits wide. */
20997 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20999 _("conditional branch out of range"));
21001 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21004 addressT S
, J1
, J2
, lo
, hi
;
21006 S
= (value
& 0x00100000) >> 20;
21007 J2
= (value
& 0x00080000) >> 19;
21008 J1
= (value
& 0x00040000) >> 18;
21009 hi
= (value
& 0x0003f000) >> 12;
21010 lo
= (value
& 0x00000ffe) >> 1;
21012 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21013 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21014 newval
|= (S
<< 10) | hi
;
21015 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
21016 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21017 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21021 case BFD_RELOC_THUMB_PCREL_BLX
:
21023 /* If there is a blx from a thumb state function to
21024 another thumb function flip this to a bl and warn
21028 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21029 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21030 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21032 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21033 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21034 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21036 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21037 newval
= newval
| 0x1000;
21038 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21039 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21044 goto thumb_bl_common
;
21046 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21048 /* A bl from Thumb state ISA to an internal ARM state function
21049 is converted to a blx. */
21051 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21052 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21053 && ARM_IS_FUNC (fixP
->fx_addsy
)
21054 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21056 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21057 newval
= newval
& ~0x1000;
21058 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21059 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
21066 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
21067 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21068 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21071 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21072 /* For a BLX instruction, make sure that the relocation is rounded up
21073 to a word boundary. This follows the semantics of the instruction
21074 which specifies that bit 1 of the target address will come from bit
21075 1 of the base address. */
21076 value
= (value
+ 1) & ~ 1;
21079 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
21081 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
21083 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21084 _("branch out of range"));
21086 else if ((value
& ~0x1ffffff)
21087 && ((value
& ~0x1ffffff) != ~0x1ffffff))
21089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21090 _("Thumb2 branch out of range"));
21094 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21095 encode_thumb2_b_bl_offset (buf
, value
);
21099 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21100 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
21101 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21102 _("branch out of range"));
21104 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21105 encode_thumb2_b_bl_offset (buf
, value
);
21110 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21111 md_number_to_chars (buf
, value
, 1);
21115 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21116 md_number_to_chars (buf
, value
, 2);
21120 case BFD_RELOC_ARM_TLS_CALL
:
21121 case BFD_RELOC_ARM_THM_TLS_CALL
:
21122 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21123 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21124 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21127 case BFD_RELOC_ARM_TLS_GOTDESC
:
21128 case BFD_RELOC_ARM_TLS_GD32
:
21129 case BFD_RELOC_ARM_TLS_LE32
:
21130 case BFD_RELOC_ARM_TLS_IE32
:
21131 case BFD_RELOC_ARM_TLS_LDM32
:
21132 case BFD_RELOC_ARM_TLS_LDO32
:
21133 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21136 case BFD_RELOC_ARM_GOT32
:
21137 case BFD_RELOC_ARM_GOTOFF
:
21138 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21139 md_number_to_chars (buf
, 0, 4);
21142 case BFD_RELOC_ARM_GOT_PREL
:
21143 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21144 md_number_to_chars (buf
, value
, 4);
21147 case BFD_RELOC_ARM_TARGET2
:
21148 /* TARGET2 is not partial-inplace, so we need to write the
21149 addend here for REL targets, because it won't be written out
21150 during reloc processing later. */
21151 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21152 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21156 case BFD_RELOC_RVA
:
21158 case BFD_RELOC_ARM_TARGET1
:
21159 case BFD_RELOC_ARM_ROSEGREL32
:
21160 case BFD_RELOC_ARM_SBREL32
:
21161 case BFD_RELOC_32_PCREL
:
21163 case BFD_RELOC_32_SECREL
:
21165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21167 /* For WinCE we only do this for pcrel fixups. */
21168 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21170 md_number_to_chars (buf
, value
, 4);
21174 case BFD_RELOC_ARM_PREL31
:
21175 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21177 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21178 if ((value
^ (value
>> 1)) & 0x40000000)
21180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21181 _("rel31 relocation overflow"));
21183 newval
|= value
& 0x7fffffff;
21184 md_number_to_chars (buf
, newval
, 4);
21189 case BFD_RELOC_ARM_CP_OFF_IMM
:
21190 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21191 if (value
< -1023 || value
> 1023 || (value
& 3))
21192 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21193 _("co-processor offset out of range"));
21198 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21199 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21200 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21202 newval
= get_thumb32_insn (buf
);
21204 newval
&= 0xffffff00;
21207 newval
&= 0xff7fff00;
21208 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21210 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21211 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21212 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21214 put_thumb32_insn (buf
, newval
);
21217 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21218 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21219 if (value
< -255 || value
> 255)
21220 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21221 _("co-processor offset out of range"));
21223 goto cp_off_common
;
21225 case BFD_RELOC_ARM_THUMB_OFFSET
:
21226 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21227 /* Exactly what ranges, and where the offset is inserted depends
21228 on the type of instruction, we can establish this from the
21230 switch (newval
>> 12)
21232 case 4: /* PC load. */
21233 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21234 forced to zero for these loads; md_pcrel_from has already
21235 compensated for this. */
21237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21238 _("invalid offset, target not word aligned (0x%08lX)"),
21239 (((unsigned long) fixP
->fx_frag
->fr_address
21240 + (unsigned long) fixP
->fx_where
) & ~3)
21241 + (unsigned long) value
);
21243 if (value
& ~0x3fc)
21244 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21245 _("invalid offset, value too big (0x%08lX)"),
21248 newval
|= value
>> 2;
21251 case 9: /* SP load/store. */
21252 if (value
& ~0x3fc)
21253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21254 _("invalid offset, value too big (0x%08lX)"),
21256 newval
|= value
>> 2;
21259 case 6: /* Word load/store. */
21261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21262 _("invalid offset, value too big (0x%08lX)"),
21264 newval
|= value
<< 4; /* 6 - 2. */
21267 case 7: /* Byte load/store. */
21269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21270 _("invalid offset, value too big (0x%08lX)"),
21272 newval
|= value
<< 6;
21275 case 8: /* Halfword load/store. */
21277 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21278 _("invalid offset, value too big (0x%08lX)"),
21280 newval
|= value
<< 5; /* 6 - 1. */
21284 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21285 "Unable to process relocation for thumb opcode: %lx",
21286 (unsigned long) newval
);
21289 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21292 case BFD_RELOC_ARM_THUMB_ADD
:
21293 /* This is a complicated relocation, since we use it for all of
21294 the following immediate relocations:
21298 9bit ADD/SUB SP word-aligned
21299 10bit ADD PC/SP word-aligned
21301 The type of instruction being processed is encoded in the
21308 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21310 int rd
= (newval
>> 4) & 0xf;
21311 int rs
= newval
& 0xf;
21312 int subtract
= !!(newval
& 0x8000);
21314 /* Check for HI regs, only very restricted cases allowed:
21315 Adjusting SP, and using PC or SP to get an address. */
21316 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21317 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21319 _("invalid Hi register with immediate"));
21321 /* If value is negative, choose the opposite instruction. */
21325 subtract
= !subtract
;
21327 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21328 _("immediate value out of range"));
21333 if (value
& ~0x1fc)
21334 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21335 _("invalid immediate for stack address calculation"));
21336 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21337 newval
|= value
>> 2;
21339 else if (rs
== REG_PC
|| rs
== REG_SP
)
21341 if (subtract
|| value
& ~0x3fc)
21342 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21343 _("invalid immediate for address calculation (value = 0x%08lX)"),
21344 (unsigned long) value
);
21345 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21347 newval
|= value
>> 2;
21352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21353 _("immediate value out of range"));
21354 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21355 newval
|= (rd
<< 8) | value
;
21360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21361 _("immediate value out of range"));
21362 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21363 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21366 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21369 case BFD_RELOC_ARM_THUMB_IMM
:
21370 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21371 if (value
< 0 || value
> 255)
21372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21373 _("invalid immediate: %ld is out of range"),
21376 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21379 case BFD_RELOC_ARM_THUMB_SHIFT
:
21380 /* 5bit shift value (0..32). LSL cannot take 32. */
21381 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21382 temp
= newval
& 0xf800;
21383 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21385 _("invalid shift value: %ld"), (long) value
);
21386 /* Shifts of zero must be encoded as LSL. */
21388 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21389 /* Shifts of 32 are encoded as zero. */
21390 else if (value
== 32)
21392 newval
|= value
<< 6;
21393 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21396 case BFD_RELOC_VTABLE_INHERIT
:
21397 case BFD_RELOC_VTABLE_ENTRY
:
21401 case BFD_RELOC_ARM_MOVW
:
21402 case BFD_RELOC_ARM_MOVT
:
21403 case BFD_RELOC_ARM_THUMB_MOVW
:
21404 case BFD_RELOC_ARM_THUMB_MOVT
:
21405 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21407 /* REL format relocations are limited to a 16-bit addend. */
21408 if (!fixP
->fx_done
)
21410 if (value
< -0x8000 || value
> 0x7fff)
21411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21412 _("offset out of range"));
21414 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21415 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21420 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21421 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21423 newval
= get_thumb32_insn (buf
);
21424 newval
&= 0xfbf08f00;
21425 newval
|= (value
& 0xf000) << 4;
21426 newval
|= (value
& 0x0800) << 15;
21427 newval
|= (value
& 0x0700) << 4;
21428 newval
|= (value
& 0x00ff);
21429 put_thumb32_insn (buf
, newval
);
21433 newval
= md_chars_to_number (buf
, 4);
21434 newval
&= 0xfff0f000;
21435 newval
|= value
& 0x0fff;
21436 newval
|= (value
& 0xf000) << 4;
21437 md_number_to_chars (buf
, newval
, 4);
21442 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21443 case BFD_RELOC_ARM_ALU_PC_G0
:
21444 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21445 case BFD_RELOC_ARM_ALU_PC_G1
:
21446 case BFD_RELOC_ARM_ALU_PC_G2
:
21447 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21448 case BFD_RELOC_ARM_ALU_SB_G0
:
21449 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21450 case BFD_RELOC_ARM_ALU_SB_G1
:
21451 case BFD_RELOC_ARM_ALU_SB_G2
:
21452 gas_assert (!fixP
->fx_done
);
21453 if (!seg
->use_rela_p
)
21456 bfd_vma encoded_addend
;
21457 bfd_vma addend_abs
= abs (value
);
21459 /* Check that the absolute value of the addend can be
21460 expressed as an 8-bit constant plus a rotation. */
21461 encoded_addend
= encode_arm_immediate (addend_abs
);
21462 if (encoded_addend
== (unsigned int) FAIL
)
21463 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21464 _("the offset 0x%08lX is not representable"),
21465 (unsigned long) addend_abs
);
21467 /* Extract the instruction. */
21468 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21470 /* If the addend is positive, use an ADD instruction.
21471 Otherwise use a SUB. Take care not to destroy the S bit. */
21472 insn
&= 0xff1fffff;
21478 /* Place the encoded addend into the first 12 bits of the
21480 insn
&= 0xfffff000;
21481 insn
|= encoded_addend
;
21483 /* Update the instruction. */
21484 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21488 case BFD_RELOC_ARM_LDR_PC_G0
:
21489 case BFD_RELOC_ARM_LDR_PC_G1
:
21490 case BFD_RELOC_ARM_LDR_PC_G2
:
21491 case BFD_RELOC_ARM_LDR_SB_G0
:
21492 case BFD_RELOC_ARM_LDR_SB_G1
:
21493 case BFD_RELOC_ARM_LDR_SB_G2
:
21494 gas_assert (!fixP
->fx_done
);
21495 if (!seg
->use_rela_p
)
21498 bfd_vma addend_abs
= abs (value
);
21500 /* Check that the absolute value of the addend can be
21501 encoded in 12 bits. */
21502 if (addend_abs
>= 0x1000)
21503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21504 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21505 (unsigned long) addend_abs
);
21507 /* Extract the instruction. */
21508 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21510 /* If the addend is negative, clear bit 23 of the instruction.
21511 Otherwise set it. */
21513 insn
&= ~(1 << 23);
21517 /* Place the absolute value of the addend into the first 12 bits
21518 of the instruction. */
21519 insn
&= 0xfffff000;
21520 insn
|= addend_abs
;
21522 /* Update the instruction. */
21523 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21527 case BFD_RELOC_ARM_LDRS_PC_G0
:
21528 case BFD_RELOC_ARM_LDRS_PC_G1
:
21529 case BFD_RELOC_ARM_LDRS_PC_G2
:
21530 case BFD_RELOC_ARM_LDRS_SB_G0
:
21531 case BFD_RELOC_ARM_LDRS_SB_G1
:
21532 case BFD_RELOC_ARM_LDRS_SB_G2
:
21533 gas_assert (!fixP
->fx_done
);
21534 if (!seg
->use_rela_p
)
21537 bfd_vma addend_abs
= abs (value
);
21539 /* Check that the absolute value of the addend can be
21540 encoded in 8 bits. */
21541 if (addend_abs
>= 0x100)
21542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21543 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21544 (unsigned long) addend_abs
);
21546 /* Extract the instruction. */
21547 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21549 /* If the addend is negative, clear bit 23 of the instruction.
21550 Otherwise set it. */
21552 insn
&= ~(1 << 23);
21556 /* Place the first four bits of the absolute value of the addend
21557 into the first 4 bits of the instruction, and the remaining
21558 four into bits 8 .. 11. */
21559 insn
&= 0xfffff0f0;
21560 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21562 /* Update the instruction. */
21563 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21567 case BFD_RELOC_ARM_LDC_PC_G0
:
21568 case BFD_RELOC_ARM_LDC_PC_G1
:
21569 case BFD_RELOC_ARM_LDC_PC_G2
:
21570 case BFD_RELOC_ARM_LDC_SB_G0
:
21571 case BFD_RELOC_ARM_LDC_SB_G1
:
21572 case BFD_RELOC_ARM_LDC_SB_G2
:
21573 gas_assert (!fixP
->fx_done
);
21574 if (!seg
->use_rela_p
)
21577 bfd_vma addend_abs
= abs (value
);
21579 /* Check that the absolute value of the addend is a multiple of
21580 four and, when divided by four, fits in 8 bits. */
21581 if (addend_abs
& 0x3)
21582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21583 _("bad offset 0x%08lX (must be word-aligned)"),
21584 (unsigned long) addend_abs
);
21586 if ((addend_abs
>> 2) > 0xff)
21587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21588 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21589 (unsigned long) addend_abs
);
21591 /* Extract the instruction. */
21592 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21594 /* If the addend is negative, clear bit 23 of the instruction.
21595 Otherwise set it. */
21597 insn
&= ~(1 << 23);
21601 /* Place the addend (divided by four) into the first eight
21602 bits of the instruction. */
21603 insn
&= 0xfffffff0;
21604 insn
|= addend_abs
>> 2;
21606 /* Update the instruction. */
21607 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21611 case BFD_RELOC_ARM_V4BX
:
21612 /* This will need to go in the object file. */
21616 case BFD_RELOC_UNUSED
:
21618 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21619 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21623 /* Translate internal representation of relocation info to BFD target
21627 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21630 bfd_reloc_code_real_type code
;
21632 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21634 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21635 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21636 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21638 if (fixp
->fx_pcrel
)
21640 if (section
->use_rela_p
)
21641 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21643 fixp
->fx_offset
= reloc
->address
;
21645 reloc
->addend
= fixp
->fx_offset
;
21647 switch (fixp
->fx_r_type
)
21650 if (fixp
->fx_pcrel
)
21652 code
= BFD_RELOC_8_PCREL
;
21657 if (fixp
->fx_pcrel
)
21659 code
= BFD_RELOC_16_PCREL
;
21664 if (fixp
->fx_pcrel
)
21666 code
= BFD_RELOC_32_PCREL
;
21670 case BFD_RELOC_ARM_MOVW
:
21671 if (fixp
->fx_pcrel
)
21673 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21677 case BFD_RELOC_ARM_MOVT
:
21678 if (fixp
->fx_pcrel
)
21680 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21684 case BFD_RELOC_ARM_THUMB_MOVW
:
21685 if (fixp
->fx_pcrel
)
21687 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21691 case BFD_RELOC_ARM_THUMB_MOVT
:
21692 if (fixp
->fx_pcrel
)
21694 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21698 case BFD_RELOC_NONE
:
21699 case BFD_RELOC_ARM_PCREL_BRANCH
:
21700 case BFD_RELOC_ARM_PCREL_BLX
:
21701 case BFD_RELOC_RVA
:
21702 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21703 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21704 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21705 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21706 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21707 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21708 case BFD_RELOC_VTABLE_ENTRY
:
21709 case BFD_RELOC_VTABLE_INHERIT
:
21711 case BFD_RELOC_32_SECREL
:
21713 code
= fixp
->fx_r_type
;
21716 case BFD_RELOC_THUMB_PCREL_BLX
:
21718 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21719 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21722 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21725 case BFD_RELOC_ARM_LITERAL
:
21726 case BFD_RELOC_ARM_HWLITERAL
:
21727 /* If this is called then the a literal has
21728 been referenced across a section boundary. */
21729 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21730 _("literal referenced across section boundary"));
21734 case BFD_RELOC_ARM_TLS_CALL
:
21735 case BFD_RELOC_ARM_THM_TLS_CALL
:
21736 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21737 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21738 case BFD_RELOC_ARM_GOT32
:
21739 case BFD_RELOC_ARM_GOTOFF
:
21740 case BFD_RELOC_ARM_GOT_PREL
:
21741 case BFD_RELOC_ARM_PLT32
:
21742 case BFD_RELOC_ARM_TARGET1
:
21743 case BFD_RELOC_ARM_ROSEGREL32
:
21744 case BFD_RELOC_ARM_SBREL32
:
21745 case BFD_RELOC_ARM_PREL31
:
21746 case BFD_RELOC_ARM_TARGET2
:
21747 case BFD_RELOC_ARM_TLS_LE32
:
21748 case BFD_RELOC_ARM_TLS_LDO32
:
21749 case BFD_RELOC_ARM_PCREL_CALL
:
21750 case BFD_RELOC_ARM_PCREL_JUMP
:
21751 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21752 case BFD_RELOC_ARM_ALU_PC_G0
:
21753 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21754 case BFD_RELOC_ARM_ALU_PC_G1
:
21755 case BFD_RELOC_ARM_ALU_PC_G2
:
21756 case BFD_RELOC_ARM_LDR_PC_G0
:
21757 case BFD_RELOC_ARM_LDR_PC_G1
:
21758 case BFD_RELOC_ARM_LDR_PC_G2
:
21759 case BFD_RELOC_ARM_LDRS_PC_G0
:
21760 case BFD_RELOC_ARM_LDRS_PC_G1
:
21761 case BFD_RELOC_ARM_LDRS_PC_G2
:
21762 case BFD_RELOC_ARM_LDC_PC_G0
:
21763 case BFD_RELOC_ARM_LDC_PC_G1
:
21764 case BFD_RELOC_ARM_LDC_PC_G2
:
21765 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21766 case BFD_RELOC_ARM_ALU_SB_G0
:
21767 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21768 case BFD_RELOC_ARM_ALU_SB_G1
:
21769 case BFD_RELOC_ARM_ALU_SB_G2
:
21770 case BFD_RELOC_ARM_LDR_SB_G0
:
21771 case BFD_RELOC_ARM_LDR_SB_G1
:
21772 case BFD_RELOC_ARM_LDR_SB_G2
:
21773 case BFD_RELOC_ARM_LDRS_SB_G0
:
21774 case BFD_RELOC_ARM_LDRS_SB_G1
:
21775 case BFD_RELOC_ARM_LDRS_SB_G2
:
21776 case BFD_RELOC_ARM_LDC_SB_G0
:
21777 case BFD_RELOC_ARM_LDC_SB_G1
:
21778 case BFD_RELOC_ARM_LDC_SB_G2
:
21779 case BFD_RELOC_ARM_V4BX
:
21780 code
= fixp
->fx_r_type
;
21783 case BFD_RELOC_ARM_TLS_GOTDESC
:
21784 case BFD_RELOC_ARM_TLS_GD32
:
21785 case BFD_RELOC_ARM_TLS_IE32
:
21786 case BFD_RELOC_ARM_TLS_LDM32
:
21787 /* BFD will include the symbol's address in the addend.
21788 But we don't want that, so subtract it out again here. */
21789 if (!S_IS_COMMON (fixp
->fx_addsy
))
21790 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21791 code
= fixp
->fx_r_type
;
21795 case BFD_RELOC_ARM_IMMEDIATE
:
21796 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21797 _("internal relocation (type: IMMEDIATE) not fixed up"));
21800 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21801 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21802 _("ADRL used for a symbol not defined in the same file"));
21805 case BFD_RELOC_ARM_OFFSET_IMM
:
21806 if (section
->use_rela_p
)
21808 code
= fixp
->fx_r_type
;
21812 if (fixp
->fx_addsy
!= NULL
21813 && !S_IS_DEFINED (fixp
->fx_addsy
)
21814 && S_IS_LOCAL (fixp
->fx_addsy
))
21816 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21817 _("undefined local label `%s'"),
21818 S_GET_NAME (fixp
->fx_addsy
));
21822 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21823 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21830 switch (fixp
->fx_r_type
)
21832 case BFD_RELOC_NONE
: type
= "NONE"; break;
21833 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21834 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21835 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21836 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21837 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21838 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21839 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21840 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21841 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21842 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21843 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21844 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21845 default: type
= _("<unknown>"); break;
21847 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21848 _("cannot represent %s relocation in this object file format"),
21855 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21857 && fixp
->fx_addsy
== GOT_symbol
)
21859 code
= BFD_RELOC_ARM_GOTPC
;
21860 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21864 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21866 if (reloc
->howto
== NULL
)
21868 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21869 _("cannot represent %s relocation in this object file format"),
21870 bfd_get_reloc_code_name (code
));
21874 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21875 vtable entry to be used in the relocation's section offset. */
21876 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21877 reloc
->address
= fixp
->fx_offset
;
21882 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21885 cons_fix_new_arm (fragS
* frag
,
21890 bfd_reloc_code_real_type type
;
21894 FIXME: @@ Should look at CPU word size. */
21898 type
= BFD_RELOC_8
;
21901 type
= BFD_RELOC_16
;
21905 type
= BFD_RELOC_32
;
21908 type
= BFD_RELOC_64
;
21913 if (exp
->X_op
== O_secrel
)
21915 exp
->X_op
= O_symbol
;
21916 type
= BFD_RELOC_32_SECREL
;
21920 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21923 #if defined (OBJ_COFF)
21925 arm_validate_fix (fixS
* fixP
)
21927 /* If the destination of the branch is a defined symbol which does not have
21928 the THUMB_FUNC attribute, then we must be calling a function which has
21929 the (interfacearm) attribute. We look for the Thumb entry point to that
21930 function and change the branch to refer to that function instead. */
21931 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21932 && fixP
->fx_addsy
!= NULL
21933 && S_IS_DEFINED (fixP
->fx_addsy
)
21934 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21936 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21943 arm_force_relocation (struct fix
* fixp
)
21945 #if defined (OBJ_COFF) && defined (TE_PE)
21946 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21950 /* In case we have a call or a branch to a function in ARM ISA mode from
21951 a thumb function or vice-versa force the relocation. These relocations
21952 are cleared off for some cores that might have blx and simple transformations
21956 switch (fixp
->fx_r_type
)
21958 case BFD_RELOC_ARM_PCREL_JUMP
:
21959 case BFD_RELOC_ARM_PCREL_CALL
:
21960 case BFD_RELOC_THUMB_PCREL_BLX
:
21961 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21965 case BFD_RELOC_ARM_PCREL_BLX
:
21966 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21967 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21968 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21969 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21978 /* Resolve these relocations even if the symbol is extern or weak.
21979 Technically this is probably wrong due to symbol preemption.
21980 In practice these relocations do not have enough range to be useful
21981 at dynamic link time, and some code (e.g. in the Linux kernel)
21982 expects these references to be resolved. */
21983 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21984 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21985 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
21986 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21987 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21988 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
21989 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
21990 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21991 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21992 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21993 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
21994 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
21995 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
21996 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
21999 /* Always leave these relocations for the linker. */
22000 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22001 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22002 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22005 /* Always generate relocations against function symbols. */
22006 if (fixp
->fx_r_type
== BFD_RELOC_32
22008 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
22011 return generic_force_reloc (fixp
);
22014 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22015 /* Relocations against function names must be left unadjusted,
22016 so that the linker can use this information to generate interworking
22017 stubs. The MIPS version of this function
22018 also prevents relocations that are mips-16 specific, but I do not
22019 know why it does this.
22022 There is one other problem that ought to be addressed here, but
22023 which currently is not: Taking the address of a label (rather
22024 than a function) and then later jumping to that address. Such
22025 addresses also ought to have their bottom bit set (assuming that
22026 they reside in Thumb code), but at the moment they will not. */
22029 arm_fix_adjustable (fixS
* fixP
)
22031 if (fixP
->fx_addsy
== NULL
)
22034 /* Preserve relocations against symbols with function type. */
22035 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
22038 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
22039 && fixP
->fx_subsy
== NULL
)
22042 /* We need the symbol name for the VTABLE entries. */
22043 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
22044 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22047 /* Don't allow symbols to be discarded on GOT related relocs. */
22048 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
22049 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
22050 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
22051 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
22052 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
22053 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
22054 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
22055 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
22056 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
22057 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
22058 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
22059 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
22060 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
22061 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
22064 /* Similarly for group relocations. */
22065 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22066 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22067 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22070 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22071 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
22072 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22073 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
22074 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
22075 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22076 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
22077 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
22078 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
22083 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22088 elf32_arm_target_format (void)
22091 return (target_big_endian
22092 ? "elf32-bigarm-symbian"
22093 : "elf32-littlearm-symbian");
22094 #elif defined (TE_VXWORKS)
22095 return (target_big_endian
22096 ? "elf32-bigarm-vxworks"
22097 : "elf32-littlearm-vxworks");
22099 if (target_big_endian
)
22100 return "elf32-bigarm";
22102 return "elf32-littlearm";
22107 armelf_frob_symbol (symbolS
* symp
,
22110 elf_frob_symbol (symp
, puntp
);
22114 /* MD interface: Finalization. */
22119 literal_pool
* pool
;
22121 /* Ensure that all the IT blocks are properly closed. */
22122 check_it_blocks_finished ();
22124 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22126 /* Put it at the end of the relevant section. */
22127 subseg_set (pool
->section
, pool
->sub_section
);
22129 arm_elf_change_section ();
22136 /* Remove any excess mapping symbols generated for alignment frags in
22137 SEC. We may have created a mapping symbol before a zero byte
22138 alignment; remove it if there's a mapping symbol after the
22141 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22142 void *dummy ATTRIBUTE_UNUSED
)
22144 segment_info_type
*seginfo
= seg_info (sec
);
22147 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22150 for (fragp
= seginfo
->frchainP
->frch_root
;
22152 fragp
= fragp
->fr_next
)
22154 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22155 fragS
*next
= fragp
->fr_next
;
22157 /* Variable-sized frags have been converted to fixed size by
22158 this point. But if this was variable-sized to start with,
22159 there will be a fixed-size frag after it. So don't handle
22161 if (sym
== NULL
|| next
== NULL
)
22164 if (S_GET_VALUE (sym
) < next
->fr_address
)
22165 /* Not at the end of this frag. */
22167 know (S_GET_VALUE (sym
) == next
->fr_address
);
22171 if (next
->tc_frag_data
.first_map
!= NULL
)
22173 /* Next frag starts with a mapping symbol. Discard this
22175 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22179 if (next
->fr_next
== NULL
)
22181 /* This mapping symbol is at the end of the section. Discard
22183 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22184 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22188 /* As long as we have empty frags without any mapping symbols,
22190 /* If the next frag is non-empty and does not start with a
22191 mapping symbol, then this mapping symbol is required. */
22192 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22195 next
= next
->fr_next
;
22197 while (next
!= NULL
);
22202 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22206 arm_adjust_symtab (void)
22211 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22213 if (ARM_IS_THUMB (sym
))
22215 if (THUMB_IS_FUNC (sym
))
22217 /* Mark the symbol as a Thumb function. */
22218 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22219 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22220 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22222 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22223 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22225 as_bad (_("%s: unexpected function type: %d"),
22226 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22228 else switch (S_GET_STORAGE_CLASS (sym
))
22231 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22234 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22237 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22245 if (ARM_IS_INTERWORK (sym
))
22246 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22253 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22255 if (ARM_IS_THUMB (sym
))
22257 elf_symbol_type
* elf_sym
;
22259 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22260 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22262 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22263 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22265 /* If it's a .thumb_func, declare it as so,
22266 otherwise tag label as .code 16. */
22267 if (THUMB_IS_FUNC (sym
))
22268 elf_sym
->internal_elf_sym
.st_target_internal
22269 = ST_BRANCH_TO_THUMB
;
22270 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22271 elf_sym
->internal_elf_sym
.st_info
=
22272 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22277 /* Remove any overlapping mapping symbols generated by alignment frags. */
22278 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22279 /* Now do generic ELF adjustments. */
22280 elf_adjust_symtab ();
22284 /* MD interface: Initialization. */
22287 set_constant_flonums (void)
22291 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22292 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22296 /* Auto-select Thumb mode if it's the only available instruction set for the
22297 given architecture. */
22300 autoselect_thumb_from_cpu_variant (void)
22302 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22303 opcode_select (16);
22312 if ( (arm_ops_hsh
= hash_new ()) == NULL
22313 || (arm_cond_hsh
= hash_new ()) == NULL
22314 || (arm_shift_hsh
= hash_new ()) == NULL
22315 || (arm_psr_hsh
= hash_new ()) == NULL
22316 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22317 || (arm_reg_hsh
= hash_new ()) == NULL
22318 || (arm_reloc_hsh
= hash_new ()) == NULL
22319 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22320 as_fatal (_("virtual memory exhausted"));
22322 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22323 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22324 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22325 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22326 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22327 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22328 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22329 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22330 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22331 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22332 (void *) (v7m_psrs
+ i
));
22333 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22334 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22336 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22338 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22339 (void *) (barrier_opt_names
+ i
));
22341 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22342 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22345 set_constant_flonums ();
22347 /* Set the cpu variant based on the command-line options. We prefer
22348 -mcpu= over -march= if both are set (as for GCC); and we prefer
22349 -mfpu= over any other way of setting the floating point unit.
22350 Use of legacy options with new options are faulted. */
22353 if (mcpu_cpu_opt
|| march_cpu_opt
)
22354 as_bad (_("use of old and new-style options to set CPU type"));
22356 mcpu_cpu_opt
= legacy_cpu
;
22358 else if (!mcpu_cpu_opt
)
22359 mcpu_cpu_opt
= march_cpu_opt
;
22364 as_bad (_("use of old and new-style options to set FPU type"));
22366 mfpu_opt
= legacy_fpu
;
22368 else if (!mfpu_opt
)
22370 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22371 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22372 /* Some environments specify a default FPU. If they don't, infer it
22373 from the processor. */
22375 mfpu_opt
= mcpu_fpu_opt
;
22377 mfpu_opt
= march_fpu_opt
;
22379 mfpu_opt
= &fpu_default
;
22385 if (mcpu_cpu_opt
!= NULL
)
22386 mfpu_opt
= &fpu_default
;
22387 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22388 mfpu_opt
= &fpu_arch_vfp_v2
;
22390 mfpu_opt
= &fpu_arch_fpa
;
22396 mcpu_cpu_opt
= &cpu_default
;
22397 selected_cpu
= cpu_default
;
22401 selected_cpu
= *mcpu_cpu_opt
;
22403 mcpu_cpu_opt
= &arm_arch_any
;
22406 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22408 autoselect_thumb_from_cpu_variant ();
22410 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22412 #if defined OBJ_COFF || defined OBJ_ELF
22414 unsigned int flags
= 0;
22416 #if defined OBJ_ELF
22417 flags
= meabi_flags
;
22419 switch (meabi_flags
)
22421 case EF_ARM_EABI_UNKNOWN
:
22423 /* Set the flags in the private structure. */
22424 if (uses_apcs_26
) flags
|= F_APCS26
;
22425 if (support_interwork
) flags
|= F_INTERWORK
;
22426 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22427 if (pic_code
) flags
|= F_PIC
;
22428 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22429 flags
|= F_SOFT_FLOAT
;
22431 switch (mfloat_abi_opt
)
22433 case ARM_FLOAT_ABI_SOFT
:
22434 case ARM_FLOAT_ABI_SOFTFP
:
22435 flags
|= F_SOFT_FLOAT
;
22438 case ARM_FLOAT_ABI_HARD
:
22439 if (flags
& F_SOFT_FLOAT
)
22440 as_bad (_("hard-float conflicts with specified fpu"));
22444 /* Using pure-endian doubles (even if soft-float). */
22445 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22446 flags
|= F_VFP_FLOAT
;
22448 #if defined OBJ_ELF
22449 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22450 flags
|= EF_ARM_MAVERICK_FLOAT
;
22453 case EF_ARM_EABI_VER4
:
22454 case EF_ARM_EABI_VER5
:
22455 /* No additional flags to set. */
22462 bfd_set_private_flags (stdoutput
, flags
);
22464 /* We have run out flags in the COFF header to encode the
22465 status of ATPCS support, so instead we create a dummy,
22466 empty, debug section called .arm.atpcs. */
22471 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22475 bfd_set_section_flags
22476 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22477 bfd_set_section_size (stdoutput
, sec
, 0);
22478 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22484 /* Record the CPU type as well. */
22485 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22486 mach
= bfd_mach_arm_iWMMXt2
;
22487 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22488 mach
= bfd_mach_arm_iWMMXt
;
22489 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22490 mach
= bfd_mach_arm_XScale
;
22491 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22492 mach
= bfd_mach_arm_ep9312
;
22493 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22494 mach
= bfd_mach_arm_5TE
;
22495 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22497 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22498 mach
= bfd_mach_arm_5T
;
22500 mach
= bfd_mach_arm_5
;
22502 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22504 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22505 mach
= bfd_mach_arm_4T
;
22507 mach
= bfd_mach_arm_4
;
22509 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22510 mach
= bfd_mach_arm_3M
;
22511 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22512 mach
= bfd_mach_arm_3
;
22513 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22514 mach
= bfd_mach_arm_2a
;
22515 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22516 mach
= bfd_mach_arm_2
;
22518 mach
= bfd_mach_arm_unknown
;
22520 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22523 /* Command line processing. */
22526 Invocation line includes a switch not recognized by the base assembler.
22527 See if it's a processor-specific option.
22529 This routine is somewhat complicated by the need for backwards
22530 compatibility (since older releases of gcc can't be changed).
22531 The new options try to make the interface as compatible as
22534 New options (supported) are:
22536 -mcpu=<cpu name> Assemble for selected processor
22537 -march=<architecture name> Assemble for selected architecture
22538 -mfpu=<fpu architecture> Assemble for selected FPU.
22539 -EB/-mbig-endian Big-endian
22540 -EL/-mlittle-endian Little-endian
22541 -k Generate PIC code
22542 -mthumb Start in Thumb mode
22543 -mthumb-interwork Code supports ARM/Thumb interworking
22545 -m[no-]warn-deprecated Warn about deprecated features
22547 For now we will also provide support for:
22549 -mapcs-32 32-bit Program counter
22550 -mapcs-26 26-bit Program counter
22551 -macps-float Floats passed in FP registers
22552 -mapcs-reentrant Reentrant code
22554 (sometime these will probably be replaced with -mapcs=<list of options>
22555 and -matpcs=<list of options>)
22557 The remaining options are only supported for back-wards compatibility.
22558 Cpu variants, the arm part is optional:
22559 -m[arm]1 Currently not supported.
22560 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22561 -m[arm]3 Arm 3 processor
22562 -m[arm]6[xx], Arm 6 processors
22563 -m[arm]7[xx][t][[d]m] Arm 7 processors
22564 -m[arm]8[10] Arm 8 processors
22565 -m[arm]9[20][tdmi] Arm 9 processors
22566 -mstrongarm[110[0]] StrongARM processors
22567 -mxscale XScale processors
22568 -m[arm]v[2345[t[e]]] Arm architectures
22569 -mall All (except the ARM1)
22571 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22572 -mfpe-old (No float load/store multiples)
22573 -mvfpxd VFP Single precision
22575 -mno-fpu Disable all floating point instructions
22577 The following CPU names are recognized:
22578 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22579 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22580 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22581 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22582 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22583 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22584 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22588 const char * md_shortopts
= "m:k";
22590 #ifdef ARM_BI_ENDIAN
22591 #define OPTION_EB (OPTION_MD_BASE + 0)
22592 #define OPTION_EL (OPTION_MD_BASE + 1)
22594 #if TARGET_BYTES_BIG_ENDIAN
22595 #define OPTION_EB (OPTION_MD_BASE + 0)
22597 #define OPTION_EL (OPTION_MD_BASE + 1)
22600 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22602 struct option md_longopts
[] =
22605 {"EB", no_argument
, NULL
, OPTION_EB
},
22608 {"EL", no_argument
, NULL
, OPTION_EL
},
22610 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22611 {NULL
, no_argument
, NULL
, 0}
22614 size_t md_longopts_size
= sizeof (md_longopts
);
22616 struct arm_option_table
22618 char *option
; /* Option name to match. */
22619 char *help
; /* Help information. */
22620 int *var
; /* Variable to change. */
22621 int value
; /* What to change it to. */
22622 char *deprecated
; /* If non-null, print this message. */
22625 struct arm_option_table arm_opts
[] =
22627 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22628 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22629 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22630 &support_interwork
, 1, NULL
},
22631 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22632 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22633 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22635 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22636 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22637 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22638 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22641 /* These are recognized by the assembler, but have no affect on code. */
22642 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22643 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22645 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22646 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22647 &warn_on_deprecated
, 0, NULL
},
22648 {NULL
, NULL
, NULL
, 0, NULL
}
22651 struct arm_legacy_option_table
22653 char *option
; /* Option name to match. */
22654 const arm_feature_set
**var
; /* Variable to change. */
22655 const arm_feature_set value
; /* What to change it to. */
22656 char *deprecated
; /* If non-null, print this message. */
22659 const struct arm_legacy_option_table arm_legacy_opts
[] =
22661 /* DON'T add any new processors to this list -- we want the whole list
22662 to go away... Add them to the processors table instead. */
22663 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22664 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22665 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22666 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22667 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22668 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22669 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22670 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22671 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22672 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22673 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22674 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22675 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22676 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22677 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22678 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22679 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22680 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22681 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22682 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22683 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22684 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22685 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22686 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22687 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22688 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22689 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22690 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22691 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22692 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22693 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22694 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22695 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22696 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22697 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22698 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22699 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22700 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22701 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22702 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22703 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22704 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22705 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22706 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22707 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22708 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22709 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22710 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22711 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22712 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22713 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22714 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22715 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22716 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22717 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22718 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22719 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22720 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22721 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22722 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22723 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22724 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22725 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22726 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22727 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22728 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22729 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22730 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22731 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22732 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22733 N_("use -mcpu=strongarm110")},
22734 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22735 N_("use -mcpu=strongarm1100")},
22736 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22737 N_("use -mcpu=strongarm1110")},
22738 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22739 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22740 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22742 /* Architecture variants -- don't add any more to this list either. */
22743 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22744 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22745 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22746 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22747 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22748 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22749 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22750 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22751 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22752 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22753 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22754 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22755 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22756 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22757 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22758 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22759 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22760 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22762 /* Floating point variants -- don't add any more to this list either. */
22763 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22764 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22765 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22766 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22767 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22769 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22772 struct arm_cpu_option_table
22775 const arm_feature_set value
;
22776 /* For some CPUs we assume an FPU unless the user explicitly sets
22778 const arm_feature_set default_fpu
;
22779 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22781 const char *canonical_name
;
22784 /* This list should, at a minimum, contain all the cpu names
22785 recognized by GCC. */
22786 static const struct arm_cpu_option_table arm_cpus
[] =
22788 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22789 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22790 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22791 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22792 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22793 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22794 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22795 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22796 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22797 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22798 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22799 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22800 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22801 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22802 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22803 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22804 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22805 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22806 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22807 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22808 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22809 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22810 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22811 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22812 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22813 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22814 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22815 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22816 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22817 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22818 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22819 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22820 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22821 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22822 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22823 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22824 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22825 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22826 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22827 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22828 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22829 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22830 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22831 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22832 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22833 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22834 /* For V5 or later processors we default to using VFP; but the user
22835 should really set the FPU type explicitly. */
22836 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22837 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22838 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22839 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22840 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22841 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22842 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22843 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22844 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22845 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22846 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22847 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22848 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22849 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22850 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22851 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22852 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22853 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22854 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22855 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22856 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22857 {"fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22858 {"fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22859 {"fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22860 {"fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22861 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22862 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22863 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22864 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22865 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22866 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22867 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22868 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22869 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22870 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22871 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22872 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22873 FPU_NONE
, "Cortex-A5"},
22874 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22875 ARM_FEATURE (0, FPU_VFP_V3
22876 | FPU_NEON_EXT_V1
),
22878 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22879 ARM_FEATURE (0, FPU_VFP_V3
22880 | FPU_NEON_EXT_V1
),
22882 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22883 FPU_ARCH_NEON_VFP_V4
,
22885 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22886 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22888 {"cortex-r5", ARM_ARCH_V7R_IDIV
,
22889 FPU_NONE
, "Cortex-R5"},
22890 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22891 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22892 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22893 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22894 /* ??? XSCALE is really an architecture. */
22895 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22896 /* ??? iwmmxt is not a processor. */
22897 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22898 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22899 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22901 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22902 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22905 struct arm_arch_option_table
22908 const arm_feature_set value
;
22909 const arm_feature_set default_fpu
;
22912 /* This list should, at a minimum, contain all the architecture names
22913 recognized by GCC. */
22914 static const struct arm_arch_option_table arm_archs
[] =
22916 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22917 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22918 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22919 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22920 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22921 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22922 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22923 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22924 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22925 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22926 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22927 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22928 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22929 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22930 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22931 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22932 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22933 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22934 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22935 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22936 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22937 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22938 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22939 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22940 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22941 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22942 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22943 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22944 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22945 /* The official spelling of the ARMv7 profile variants is the dashed form.
22946 Accept the non-dashed form for compatibility with old toolchains. */
22947 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22948 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22949 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22950 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22951 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22952 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22953 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22954 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22955 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22956 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22957 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22960 /* ISA extensions in the co-processor and main instruction set space. */
22961 struct arm_option_extension_value_table
22964 const arm_feature_set value
;
22965 const arm_feature_set allowed_archs
;
22968 /* The following table must be in alphabetical order with a NULL last entry.
22970 static const struct arm_option_extension_value_table arm_extensions
[] =
22972 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22973 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22974 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22975 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22976 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22977 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22978 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22979 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22980 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22981 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22982 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22983 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22984 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22985 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22986 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22989 /* ISA floating-point and Advanced SIMD extensions. */
22990 struct arm_option_fpu_value_table
22993 const arm_feature_set value
;
22996 /* This list should, at a minimum, contain all the fpu names
22997 recognized by GCC. */
22998 static const struct arm_option_fpu_value_table arm_fpus
[] =
23000 {"softfpa", FPU_NONE
},
23001 {"fpe", FPU_ARCH_FPE
},
23002 {"fpe2", FPU_ARCH_FPE
},
23003 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
23004 {"fpa", FPU_ARCH_FPA
},
23005 {"fpa10", FPU_ARCH_FPA
},
23006 {"fpa11", FPU_ARCH_FPA
},
23007 {"arm7500fe", FPU_ARCH_FPA
},
23008 {"softvfp", FPU_ARCH_VFP
},
23009 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
23010 {"vfp", FPU_ARCH_VFP_V2
},
23011 {"vfp9", FPU_ARCH_VFP_V2
},
23012 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
23013 {"vfp10", FPU_ARCH_VFP_V2
},
23014 {"vfp10-r0", FPU_ARCH_VFP_V1
},
23015 {"vfpxd", FPU_ARCH_VFP_V1xD
},
23016 {"vfpv2", FPU_ARCH_VFP_V2
},
23017 {"vfpv3", FPU_ARCH_VFP_V3
},
23018 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
23019 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
23020 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
23021 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
23022 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
23023 {"arm1020t", FPU_ARCH_VFP_V1
},
23024 {"arm1020e", FPU_ARCH_VFP_V2
},
23025 {"arm1136jfs", FPU_ARCH_VFP_V2
},
23026 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
23027 {"maverick", FPU_ARCH_MAVERICK
},
23028 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
23029 {"neon-fp16", FPU_ARCH_NEON_FP16
},
23030 {"vfpv4", FPU_ARCH_VFP_V4
},
23031 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
23032 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
23033 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
23034 {NULL
, ARM_ARCH_NONE
}
23037 struct arm_option_value_table
23043 static const struct arm_option_value_table arm_float_abis
[] =
23045 {"hard", ARM_FLOAT_ABI_HARD
},
23046 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
23047 {"soft", ARM_FLOAT_ABI_SOFT
},
23052 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23053 static const struct arm_option_value_table arm_eabis
[] =
23055 {"gnu", EF_ARM_EABI_UNKNOWN
},
23056 {"4", EF_ARM_EABI_VER4
},
23057 {"5", EF_ARM_EABI_VER5
},
23062 struct arm_long_option_table
23064 char * option
; /* Substring to match. */
23065 char * help
; /* Help information. */
23066 int (* func
) (char * subopt
); /* Function to decode sub-option. */
23067 char * deprecated
; /* If non-null, print this message. */
23071 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
23073 arm_feature_set
*ext_set
= (arm_feature_set
*)
23074 xmalloc (sizeof (arm_feature_set
));
23076 /* We insist on extensions being specified in alphabetical order, and with
23077 extensions being added before being removed. We achieve this by having
23078 the global ARM_EXTENSIONS table in alphabetical order, and using the
23079 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23080 or removing it (0) and only allowing it to change in the order
23082 const struct arm_option_extension_value_table
* opt
= NULL
;
23083 int adding_value
= -1;
23085 /* Copy the feature set, so that we can modify it. */
23086 *ext_set
= **opt_p
;
23089 while (str
!= NULL
&& *str
!= 0)
23096 as_bad (_("invalid architectural extension"));
23101 ext
= strchr (str
, '+');
23104 optlen
= ext
- str
;
23106 optlen
= strlen (str
);
23109 && strncmp (str
, "no", 2) == 0)
23111 if (adding_value
!= 0)
23114 opt
= arm_extensions
;
23120 else if (optlen
> 0)
23122 if (adding_value
== -1)
23125 opt
= arm_extensions
;
23127 else if (adding_value
!= 1)
23129 as_bad (_("must specify extensions to add before specifying "
23130 "those to remove"));
23137 as_bad (_("missing architectural extension"));
23141 gas_assert (adding_value
!= -1);
23142 gas_assert (opt
!= NULL
);
23144 /* Scan over the options table trying to find an exact match. */
23145 for (; opt
->name
!= NULL
; opt
++)
23146 if (strncmp (opt
->name
, str
, optlen
) == 0
23147 && strlen (opt
->name
) == optlen
)
23149 /* Check we can apply the extension to this architecture. */
23150 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23152 as_bad (_("extension does not apply to the base architecture"));
23156 /* Add or remove the extension. */
23158 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23160 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23165 if (opt
->name
== NULL
)
23167 /* Did we fail to find an extension because it wasn't specified in
23168 alphabetical order, or because it does not exist? */
23170 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23171 if (strncmp (opt
->name
, str
, optlen
) == 0)
23174 if (opt
->name
== NULL
)
23175 as_bad (_("unknown architectural extension `%s'"), str
);
23177 as_bad (_("architectural extensions must be specified in "
23178 "alphabetical order"));
23184 /* We should skip the extension we've just matched the next time
23196 arm_parse_cpu (char * str
)
23198 const struct arm_cpu_option_table
* opt
;
23199 char * ext
= strchr (str
, '+');
23203 optlen
= ext
- str
;
23205 optlen
= strlen (str
);
23209 as_bad (_("missing cpu name `%s'"), str
);
23213 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23214 if (strncmp (opt
->name
, str
, optlen
) == 0)
23216 mcpu_cpu_opt
= &opt
->value
;
23217 mcpu_fpu_opt
= &opt
->default_fpu
;
23218 if (opt
->canonical_name
)
23219 strcpy (selected_cpu_name
, opt
->canonical_name
);
23224 for (i
= 0; i
< optlen
; i
++)
23225 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23226 selected_cpu_name
[i
] = 0;
23230 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23235 as_bad (_("unknown cpu `%s'"), str
);
23240 arm_parse_arch (char * str
)
23242 const struct arm_arch_option_table
*opt
;
23243 char *ext
= strchr (str
, '+');
23247 optlen
= ext
- str
;
23249 optlen
= strlen (str
);
23253 as_bad (_("missing architecture name `%s'"), str
);
23257 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23258 if (strncmp (opt
->name
, str
, optlen
) == 0)
23260 march_cpu_opt
= &opt
->value
;
23261 march_fpu_opt
= &opt
->default_fpu
;
23262 strcpy (selected_cpu_name
, opt
->name
);
23265 return arm_parse_extension (ext
, &march_cpu_opt
);
23270 as_bad (_("unknown architecture `%s'\n"), str
);
23275 arm_parse_fpu (char * str
)
23277 const struct arm_option_fpu_value_table
* opt
;
23279 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23280 if (streq (opt
->name
, str
))
23282 mfpu_opt
= &opt
->value
;
23286 as_bad (_("unknown floating point format `%s'\n"), str
);
23291 arm_parse_float_abi (char * str
)
23293 const struct arm_option_value_table
* opt
;
23295 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23296 if (streq (opt
->name
, str
))
23298 mfloat_abi_opt
= opt
->value
;
23302 as_bad (_("unknown floating point abi `%s'\n"), str
);
23308 arm_parse_eabi (char * str
)
23310 const struct arm_option_value_table
*opt
;
23312 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23313 if (streq (opt
->name
, str
))
23315 meabi_flags
= opt
->value
;
23318 as_bad (_("unknown EABI `%s'\n"), str
);
23324 arm_parse_it_mode (char * str
)
23326 bfd_boolean ret
= TRUE
;
23328 if (streq ("arm", str
))
23329 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23330 else if (streq ("thumb", str
))
23331 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23332 else if (streq ("always", str
))
23333 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23334 else if (streq ("never", str
))
23335 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23338 as_bad (_("unknown implicit IT mode `%s', should be "\
23339 "arm, thumb, always, or never."), str
);
23346 struct arm_long_option_table arm_long_opts
[] =
23348 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23349 arm_parse_cpu
, NULL
},
23350 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23351 arm_parse_arch
, NULL
},
23352 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23353 arm_parse_fpu
, NULL
},
23354 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23355 arm_parse_float_abi
, NULL
},
23357 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23358 arm_parse_eabi
, NULL
},
23360 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23361 arm_parse_it_mode
, NULL
},
23362 {NULL
, NULL
, 0, NULL
}
23366 md_parse_option (int c
, char * arg
)
23368 struct arm_option_table
*opt
;
23369 const struct arm_legacy_option_table
*fopt
;
23370 struct arm_long_option_table
*lopt
;
23376 target_big_endian
= 1;
23382 target_big_endian
= 0;
23386 case OPTION_FIX_V4BX
:
23391 /* Listing option. Just ignore these, we don't support additional
23396 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23398 if (c
== opt
->option
[0]
23399 && ((arg
== NULL
&& opt
->option
[1] == 0)
23400 || streq (arg
, opt
->option
+ 1)))
23402 /* If the option is deprecated, tell the user. */
23403 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23404 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23405 arg
? arg
: "", _(opt
->deprecated
));
23407 if (opt
->var
!= NULL
)
23408 *opt
->var
= opt
->value
;
23414 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23416 if (c
== fopt
->option
[0]
23417 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23418 || streq (arg
, fopt
->option
+ 1)))
23420 /* If the option is deprecated, tell the user. */
23421 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23422 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23423 arg
? arg
: "", _(fopt
->deprecated
));
23425 if (fopt
->var
!= NULL
)
23426 *fopt
->var
= &fopt
->value
;
23432 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23434 /* These options are expected to have an argument. */
23435 if (c
== lopt
->option
[0]
23437 && strncmp (arg
, lopt
->option
+ 1,
23438 strlen (lopt
->option
+ 1)) == 0)
23440 /* If the option is deprecated, tell the user. */
23441 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23442 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23443 _(lopt
->deprecated
));
23445 /* Call the sup-option parser. */
23446 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23457 md_show_usage (FILE * fp
)
23459 struct arm_option_table
*opt
;
23460 struct arm_long_option_table
*lopt
;
23462 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23464 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23465 if (opt
->help
!= NULL
)
23466 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23468 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23469 if (lopt
->help
!= NULL
)
23470 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23474 -EB assemble code for a big-endian cpu\n"));
23479 -EL assemble code for a little-endian cpu\n"));
23483 --fix-v4bx Allow BX in ARMv4 code\n"));
23491 arm_feature_set flags
;
23492 } cpu_arch_ver_table
;
23494 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23495 least features first. */
23496 static const cpu_arch_ver_table cpu_arch_ver
[] =
23502 {4, ARM_ARCH_V5TE
},
23503 {5, ARM_ARCH_V5TEJ
},
23507 {11, ARM_ARCH_V6M
},
23508 {12, ARM_ARCH_V6SM
},
23509 {8, ARM_ARCH_V6T2
},
23510 {10, ARM_ARCH_V7A
},
23511 {10, ARM_ARCH_V7R
},
23512 {10, ARM_ARCH_V7M
},
23516 /* Set an attribute if it has not already been set by the user. */
23518 aeabi_set_attribute_int (int tag
, int value
)
23521 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23522 || !attributes_set_explicitly
[tag
])
23523 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23527 aeabi_set_attribute_string (int tag
, const char *value
)
23530 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23531 || !attributes_set_explicitly
[tag
])
23532 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23535 /* Set the public EABI object attributes. */
23537 aeabi_set_public_attributes (void)
23541 arm_feature_set flags
;
23542 arm_feature_set tmp
;
23543 const cpu_arch_ver_table
*p
;
23545 /* Choose the architecture based on the capabilities of the requested cpu
23546 (if any) and/or the instructions actually used. */
23547 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23548 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23549 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23550 /*Allow the user to override the reported architecture. */
23553 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23554 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23557 /* We need to make sure that the attributes do not identify us as v6S-M
23558 when the only v6S-M feature in use is the Operating System Extensions. */
23559 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23560 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23561 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23565 for (p
= cpu_arch_ver
; p
->val
; p
++)
23567 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23570 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23574 /* The table lookup above finds the last architecture to contribute
23575 a new feature. Unfortunately, Tag13 is a subset of the union of
23576 v6T2 and v7-M, so it is never seen as contributing a new feature.
23577 We can not search for the last entry which is entirely used,
23578 because if no CPU is specified we build up only those flags
23579 actually used. Perhaps we should separate out the specified
23580 and implicit cases. Avoid taking this path for -march=all by
23581 checking for contradictory v7-A / v7-M features. */
23583 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23584 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23585 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23588 /* Tag_CPU_name. */
23589 if (selected_cpu_name
[0])
23593 q
= selected_cpu_name
;
23594 if (strncmp (q
, "armv", 4) == 0)
23599 for (i
= 0; q
[i
]; i
++)
23600 q
[i
] = TOUPPER (q
[i
]);
23602 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23605 /* Tag_CPU_arch. */
23606 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23608 /* Tag_CPU_arch_profile. */
23609 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23610 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23611 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23612 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23613 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23614 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23616 /* Tag_ARM_ISA_use. */
23617 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23619 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23621 /* Tag_THUMB_ISA_use. */
23622 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23624 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23625 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23627 /* Tag_VFP_arch. */
23628 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23629 aeabi_set_attribute_int (Tag_VFP_arch
,
23630 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23632 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23633 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23634 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23635 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23636 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23637 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23638 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23639 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23640 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23642 /* Tag_ABI_HardFP_use. */
23643 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23644 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23645 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23647 /* Tag_WMMX_arch. */
23648 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23649 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23650 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23651 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23653 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23654 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23655 aeabi_set_attribute_int
23656 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23659 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23660 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23661 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23664 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23665 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23666 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23667 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23669 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23671 /* Tag_MP_extension_use. */
23672 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23673 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23675 /* Tag Virtualization_use. */
23676 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23678 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23681 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23684 /* Add the default contents for the .ARM.attributes section. */
23688 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23691 aeabi_set_public_attributes ();
23693 #endif /* OBJ_ELF */
23696 /* Parse a .cpu directive. */
23699 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23701 const struct arm_cpu_option_table
*opt
;
23705 name
= input_line_pointer
;
23706 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23707 input_line_pointer
++;
23708 saved_char
= *input_line_pointer
;
23709 *input_line_pointer
= 0;
23711 /* Skip the first "all" entry. */
23712 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23713 if (streq (opt
->name
, name
))
23715 mcpu_cpu_opt
= &opt
->value
;
23716 selected_cpu
= opt
->value
;
23717 if (opt
->canonical_name
)
23718 strcpy (selected_cpu_name
, opt
->canonical_name
);
23722 for (i
= 0; opt
->name
[i
]; i
++)
23723 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23724 selected_cpu_name
[i
] = 0;
23726 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23727 *input_line_pointer
= saved_char
;
23728 demand_empty_rest_of_line ();
23731 as_bad (_("unknown cpu `%s'"), name
);
23732 *input_line_pointer
= saved_char
;
23733 ignore_rest_of_line ();
23737 /* Parse a .arch directive. */
23740 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23742 const struct arm_arch_option_table
*opt
;
23746 name
= input_line_pointer
;
23747 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23748 input_line_pointer
++;
23749 saved_char
= *input_line_pointer
;
23750 *input_line_pointer
= 0;
23752 /* Skip the first "all" entry. */
23753 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23754 if (streq (opt
->name
, name
))
23756 mcpu_cpu_opt
= &opt
->value
;
23757 selected_cpu
= opt
->value
;
23758 strcpy (selected_cpu_name
, opt
->name
);
23759 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23760 *input_line_pointer
= saved_char
;
23761 demand_empty_rest_of_line ();
23765 as_bad (_("unknown architecture `%s'\n"), name
);
23766 *input_line_pointer
= saved_char
;
23767 ignore_rest_of_line ();
23771 /* Parse a .object_arch directive. */
23774 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23776 const struct arm_arch_option_table
*opt
;
23780 name
= input_line_pointer
;
23781 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23782 input_line_pointer
++;
23783 saved_char
= *input_line_pointer
;
23784 *input_line_pointer
= 0;
23786 /* Skip the first "all" entry. */
23787 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23788 if (streq (opt
->name
, name
))
23790 object_arch
= &opt
->value
;
23791 *input_line_pointer
= saved_char
;
23792 demand_empty_rest_of_line ();
23796 as_bad (_("unknown architecture `%s'\n"), name
);
23797 *input_line_pointer
= saved_char
;
23798 ignore_rest_of_line ();
23801 /* Parse a .arch_extension directive. */
23804 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23806 const struct arm_option_extension_value_table
*opt
;
23809 int adding_value
= 1;
23811 name
= input_line_pointer
;
23812 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23813 input_line_pointer
++;
23814 saved_char
= *input_line_pointer
;
23815 *input_line_pointer
= 0;
23817 if (strlen (name
) >= 2
23818 && strncmp (name
, "no", 2) == 0)
23824 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23825 if (streq (opt
->name
, name
))
23827 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23829 as_bad (_("architectural extension `%s' is not allowed for the "
23830 "current base architecture"), name
);
23835 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23837 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23839 mcpu_cpu_opt
= &selected_cpu
;
23840 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23841 *input_line_pointer
= saved_char
;
23842 demand_empty_rest_of_line ();
23846 if (opt
->name
== NULL
)
23847 as_bad (_("unknown architecture `%s'\n"), name
);
23849 *input_line_pointer
= saved_char
;
23850 ignore_rest_of_line ();
23853 /* Parse a .fpu directive. */
23856 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23858 const struct arm_option_fpu_value_table
*opt
;
23862 name
= input_line_pointer
;
23863 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23864 input_line_pointer
++;
23865 saved_char
= *input_line_pointer
;
23866 *input_line_pointer
= 0;
23868 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23869 if (streq (opt
->name
, name
))
23871 mfpu_opt
= &opt
->value
;
23872 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23873 *input_line_pointer
= saved_char
;
23874 demand_empty_rest_of_line ();
23878 as_bad (_("unknown floating point format `%s'\n"), name
);
23879 *input_line_pointer
= saved_char
;
23880 ignore_rest_of_line ();
23883 /* Copy symbol information. */
23886 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23888 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23892 /* Given a symbolic attribute NAME, return the proper integer value.
23893 Returns -1 if the attribute is not known. */
23896 arm_convert_symbolic_attribute (const char *name
)
23898 static const struct
23903 attribute_table
[] =
23905 /* When you modify this table you should
23906 also modify the list in doc/c-arm.texi. */
23907 #define T(tag) {#tag, tag}
23908 T (Tag_CPU_raw_name
),
23911 T (Tag_CPU_arch_profile
),
23912 T (Tag_ARM_ISA_use
),
23913 T (Tag_THUMB_ISA_use
),
23917 T (Tag_Advanced_SIMD_arch
),
23918 T (Tag_PCS_config
),
23919 T (Tag_ABI_PCS_R9_use
),
23920 T (Tag_ABI_PCS_RW_data
),
23921 T (Tag_ABI_PCS_RO_data
),
23922 T (Tag_ABI_PCS_GOT_use
),
23923 T (Tag_ABI_PCS_wchar_t
),
23924 T (Tag_ABI_FP_rounding
),
23925 T (Tag_ABI_FP_denormal
),
23926 T (Tag_ABI_FP_exceptions
),
23927 T (Tag_ABI_FP_user_exceptions
),
23928 T (Tag_ABI_FP_number_model
),
23929 T (Tag_ABI_align_needed
),
23930 T (Tag_ABI_align8_needed
),
23931 T (Tag_ABI_align_preserved
),
23932 T (Tag_ABI_align8_preserved
),
23933 T (Tag_ABI_enum_size
),
23934 T (Tag_ABI_HardFP_use
),
23935 T (Tag_ABI_VFP_args
),
23936 T (Tag_ABI_WMMX_args
),
23937 T (Tag_ABI_optimization_goals
),
23938 T (Tag_ABI_FP_optimization_goals
),
23939 T (Tag_compatibility
),
23940 T (Tag_CPU_unaligned_access
),
23941 T (Tag_FP_HP_extension
),
23942 T (Tag_VFP_HP_extension
),
23943 T (Tag_ABI_FP_16bit_format
),
23944 T (Tag_MPextension_use
),
23946 T (Tag_nodefaults
),
23947 T (Tag_also_compatible_with
),
23948 T (Tag_conformance
),
23950 T (Tag_Virtualization_use
),
23951 /* We deliberately do not include Tag_MPextension_use_legacy. */
23959 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23960 if (streq (name
, attribute_table
[i
].name
))
23961 return attribute_table
[i
].tag
;
23967 /* Apply sym value for relocations only in the case that
23968 they are for local symbols and you have the respective
23969 architectural feature for blx and simple switches. */
23971 arm_apply_sym_value (struct fix
* fixP
)
23974 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23975 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
23977 switch (fixP
->fx_r_type
)
23979 case BFD_RELOC_ARM_PCREL_BLX
:
23980 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23981 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23985 case BFD_RELOC_ARM_PCREL_CALL
:
23986 case BFD_RELOC_THUMB_PCREL_BLX
:
23987 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23998 #endif /* OBJ_ELF */