opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int, int);
  59 static void OP_E_extended (int, int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_VEX_FMA (int, int);
  97 static void OP_EX_Vex (int, int);
  98 static void OP_EX_VexW (int, int);
  99 static void OP_EX_VexImmW (int, int);
 100 static void OP_XMM_Vex (int, int);
 101 static void OP_XMM_VexW (int, int);
 102 static void OP_REG_VexI4 (int, int);
 103 static void PCLMUL_Fixup (int, int);
 104 static void VEXI4_Fixup (int, int);
 105 static void VZERO_Fixup (int, int);
 106 static void VCMP_Fixup (int, int);
 107 static void VPERMIL2_Fixup (int, int);
 108 static void OP_0f07 (int, int);
 109 static void OP_Monitor (int, int);
 110 static void OP_Mwait (int, int);
 111 static void NOP_Fixup1 (int, int);
 112 static void NOP_Fixup2 (int, int);
 113 static void OP_3DNowSuffix (int, int);
 114 static void CMP_Fixup (int, int);
 115 static void BadOp (void);
 116 static void REP_Fixup (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void print_drex_arg (unsigned int, int, int);
 121 static void OP_DREX4 (int, int);
 122 static void OP_DREX3 (int, int);
 123 static void OP_DREX_ICMP (int, int);
 124 static void OP_DREX_FCMP (int, int);
 125 static void MOVBE_Fixup (int, int);
 126
 127 struct dis_private {
 128   /* Points to first byte not fetched.  */
 129   bfd_byte *max_fetched;
 130   bfd_byte the_buffer[MAX_MNEM_SIZE];
 131   bfd_vma insn_start;
 132   int orig_sizeflag;
 133   jmp_buf bailout;
 134 };
 135
 136 enum address_mode
 137 {
 138   mode_16bit,
 139   mode_32bit,
 140   mode_64bit
 141 };
 142
 143 enum address_mode address_mode;
 144
 145 /* Flags for the prefixes for the current instruction.  See below.  */
 146 static int prefixes;
 147
 148 /* REX prefix the current instruction.  See below.  */
 149 static int rex;
 150 /* Bits of REX we've already used.  */
 151 static int rex_used;
 152 /* Original REX prefix.  */
 153 static int rex_original;
 154 /* REX bits in original REX prefix ignored.  It may not be the same
 155    as rex_original since some bits may not be ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Special 'registers' for DREX handling */
 173 #define DREX_REG_UNKNOWN        1000    /* not initialized */
 174 #define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */
 175
 176 /* The DREX byte has the following fields:
 177    Bits 7-4 -- DREX.Dest, xmm destination register
 178    Bit 3    -- DREX.OC0, operand config bit defines operand order
 179    Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register
 180    Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field
 181    Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
 182                SIB base field, or opcode reg field.  */
 183 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
 184 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
 185
 186 /* Flags for prefixes which we somehow handled when printing the
 187    current instruction.  */
 188 static int used_prefixes;
 189
 190 /* Flags stored in PREFIXES.  */
 191 #define PREFIX_REPZ 1
 192 #define PREFIX_REPNZ 2
 193 #define PREFIX_LOCK 4
 194 #define PREFIX_CS 8
 195 #define PREFIX_SS 0x10
 196 #define PREFIX_DS 0x20
 197 #define PREFIX_ES 0x40
 198 #define PREFIX_FS 0x80
 199 #define PREFIX_GS 0x100
 200 #define PREFIX_DATA 0x200
 201 #define PREFIX_ADDR 0x400
 202 #define PREFIX_FWAIT 0x800
 203
 204 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 205    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 206    on error.  */
 207 #define FETCH_DATA(info, addr) \
 208   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 209    ? 1 : fetch_data ((info), (addr)))
 210
 211 static int
 212 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 213 {
 214   int status;
 215   struct dis_private *priv = (struct dis_private *) info->private_data;
 216   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 217
 218   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 219     status = (*info->read_memory_func) (start,
 220                                         priv->max_fetched,
 221                                         addr - priv->max_fetched,
 222                                         info);
 223   else
 224     status = -1;
 225   if (status != 0)
 226     {
 227       /* If we did manage to read at least one byte, then
 228          print_insn_i386 will do something sensible.  Otherwise, print
 229          an error.  We do that here because this is where we know
 230          STATUS.  */
 231       if (priv->max_fetched == priv->the_buffer)
 232         (*info->memory_error_func) (status, start, info);
 233       longjmp (priv->bailout, 1);
 234     }
 235   else
 236     priv->max_fetched = addr;
 237   return 1;
 238 }
 239
 240 #define XX { NULL, 0 }
 241
 242 #define Eb { OP_E, b_mode }
 243 #define EbS { OP_E, b_swap_mode }
 244 #define Ev { OP_E, v_mode }
 245 #define EvS { OP_E, v_swap_mode }
 246 #define Ed { OP_E, d_mode }
 247 #define Edq { OP_E, dq_mode }
 248 #define Edqw { OP_E, dqw_mode }
 249 #define Edqb { OP_E, dqb_mode }
 250 #define Edqd { OP_E, dqd_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, stack_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mx { OP_M, x_mode }
 265 #define Mxmm { OP_M, xmm_mode }
 266 #define Gb { OP_G, b_mode }
 267 #define Gv { OP_G, v_mode }
 268 #define Gd { OP_G, d_mode }
 269 #define Gdq { OP_G, dq_mode }
 270 #define Gm { OP_G, m_mode }
 271 #define Gw { OP_G, w_mode }
 272 #define Rd { OP_R, d_mode }
 273 #define Rm { OP_R, m_mode }
 274 #define Ib { OP_I, b_mode }
 275 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 276 #define Iv { OP_I, v_mode }
 277 #define Iq { OP_I, q_mode }
 278 #define Iv64 { OP_I64, v_mode }
 279 #define Iw { OP_I, w_mode }
 280 #define I1 { OP_I, const_1_mode }
 281 #define Jb { OP_J, b_mode }
 282 #define Jv { OP_J, v_mode }
 283 #define Cm { OP_C, m_mode }
 284 #define Dm { OP_D, m_mode }
 285 #define Td { OP_T, d_mode }
 286 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 287
 288 #define RMeAX { OP_REG, eAX_reg }
 289 #define RMeBX { OP_REG, eBX_reg }
 290 #define RMeCX { OP_REG, eCX_reg }
 291 #define RMeDX { OP_REG, eDX_reg }
 292 #define RMeSP { OP_REG, eSP_reg }
 293 #define RMeBP { OP_REG, eBP_reg }
 294 #define RMeSI { OP_REG, eSI_reg }
 295 #define RMeDI { OP_REG, eDI_reg }
 296 #define RMrAX { OP_REG, rAX_reg }
 297 #define RMrBX { OP_REG, rBX_reg }
 298 #define RMrCX { OP_REG, rCX_reg }
 299 #define RMrDX { OP_REG, rDX_reg }
 300 #define RMrSP { OP_REG, rSP_reg }
 301 #define RMrBP { OP_REG, rBP_reg }
 302 #define RMrSI { OP_REG, rSI_reg }
 303 #define RMrDI { OP_REG, rDI_reg }
 304 #define RMAL { OP_REG, al_reg }
 305 #define RMAL { OP_REG, al_reg }
 306 #define RMCL { OP_REG, cl_reg }
 307 #define RMDL { OP_REG, dl_reg }
 308 #define RMBL { OP_REG, bl_reg }
 309 #define RMAH { OP_REG, ah_reg }
 310 #define RMCH { OP_REG, ch_reg }
 311 #define RMDH { OP_REG, dh_reg }
 312 #define RMBH { OP_REG, bh_reg }
 313 #define RMAX { OP_REG, ax_reg }
 314 #define RMDX { OP_REG, dx_reg }
 315
 316 #define eAX { OP_IMREG, eAX_reg }
 317 #define eBX { OP_IMREG, eBX_reg }
 318 #define eCX { OP_IMREG, eCX_reg }
 319 #define eDX { OP_IMREG, eDX_reg }
 320 #define eSP { OP_IMREG, eSP_reg }
 321 #define eBP { OP_IMREG, eBP_reg }
 322 #define eSI { OP_IMREG, eSI_reg }
 323 #define eDI { OP_IMREG, eDI_reg }
 324 #define AL { OP_IMREG, al_reg }
 325 #define CL { OP_IMREG, cl_reg }
 326 #define DL { OP_IMREG, dl_reg }
 327 #define BL { OP_IMREG, bl_reg }
 328 #define AH { OP_IMREG, ah_reg }
 329 #define CH { OP_IMREG, ch_reg }
 330 #define DH { OP_IMREG, dh_reg }
 331 #define BH { OP_IMREG, bh_reg }
 332 #define AX { OP_IMREG, ax_reg }
 333 #define DX { OP_IMREG, dx_reg }
 334 #define zAX { OP_IMREG, z_mode_ax_reg }
 335 #define indirDX { OP_IMREG, indir_dx_reg }
 336
 337 #define Sw { OP_SEG, w_mode }
 338 #define Sv { OP_SEG, v_mode }
 339 #define Ap { OP_DIR, 0 }
 340 #define Ob { OP_OFF64, b_mode }
 341 #define Ov { OP_OFF64, v_mode }
 342 #define Xb { OP_DSreg, eSI_reg }
 343 #define Xv { OP_DSreg, eSI_reg }
 344 #define Xz { OP_DSreg, eSI_reg }
 345 #define Yb { OP_ESreg, eDI_reg }
 346 #define Yv { OP_ESreg, eDI_reg }
 347 #define DSBX { OP_DSreg, eBX_reg }
 348
 349 #define es { OP_REG, es_reg }
 350 #define ss { OP_REG, ss_reg }
 351 #define cs { OP_REG, cs_reg }
 352 #define ds { OP_REG, ds_reg }
 353 #define fs { OP_REG, fs_reg }
 354 #define gs { OP_REG, gs_reg }
 355
 356 #define MX { OP_MMX, 0 }
 357 #define XM { OP_XMM, 0 }
 358 #define XMM { OP_XMM, xmm_mode }
 359 #define EM { OP_EM, v_mode }
 360 #define EMS { OP_EM, v_swap_mode }
 361 #define EMd { OP_EM, d_mode }
 362 #define EMx { OP_EM, x_mode }
 363 #define EXw { OP_EX, w_mode }
 364 #define EXd { OP_EX, d_mode }
 365 #define EXq { OP_EX, q_mode }
 366 #define EXqS { OP_EX, q_swap_mode }
 367 #define EXx { OP_EX, x_mode }
 368 #define EXxS { OP_EX, x_swap_mode }
 369 #define EXxmm { OP_EX, xmm_mode }
 370 #define EXxmmq { OP_EX, xmmq_mode }
 371 #define EXymmq { OP_EX, ymmq_mode }
 372 #define MS { OP_MS, v_mode }
 373 #define XS { OP_XS, v_mode }
 374 #define EMCq { OP_EMC, q_mode }
 375 #define MXC { OP_MXC, 0 }
 376 #define OPSUF { OP_3DNowSuffix, 0 }
 377 #define CMP { CMP_Fixup, 0 }
 378 #define XMM0 { XMM_Fixup, 0 }
 379
 380 #define Vex { OP_VEX, vex_mode }
 381 #define Vex128 { OP_VEX, vex128_mode }
 382 #define Vex256 { OP_VEX, vex256_mode }
 383 #define VexI4 { VEXI4_Fixup, 0}
 384 #define VexFMA { OP_VEX_FMA, vex_mode }
 385 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
 386 #define EXdVex { OP_EX_Vex, d_mode }
 387 #define EXqVex { OP_EX_Vex, q_mode }
 388 #define EXVexW { OP_EX_VexW, x_mode }
 389 #define EXdVexW { OP_EX_VexW, d_mode }
 390 #define EXqVexW { OP_EX_VexW, q_mode }
 391 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 392 #define XMVex { OP_XMM_Vex, 0 }
 393 #define XMVexW { OP_XMM_VexW, 0 }
 394 #define XMVexI4 { OP_REG_VexI4, x_mode }
 395 #define PCLMUL { PCLMUL_Fixup, 0 }
 396 #define VZERO { VZERO_Fixup, 0 }
 397 #define VCMP { VCMP_Fixup, 0 }
 398 #define VPERMIL2 { VPERMIL2_Fixup, 0 }
 399
 400 /* Used handle "rep" prefix for string instructions.  */
 401 #define Xbr { REP_Fixup, eSI_reg }
 402 #define Xvr { REP_Fixup, eSI_reg }
 403 #define Ybr { REP_Fixup, eDI_reg }
 404 #define Yvr { REP_Fixup, eDI_reg }
 405 #define Yzr { REP_Fixup, eDI_reg }
 406 #define indirDXr { REP_Fixup, indir_dx_reg }
 407 #define ALr { REP_Fixup, al_reg }
 408 #define eAXr { REP_Fixup, eAX_reg }
 409
 410 #define cond_jump_flag { NULL, cond_jump_mode }
 411 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 412
 413 /* bits in sizeflag */
 414 #define SUFFIX_ALWAYS 4
 415 #define AFLAG 2
 416 #define DFLAG 1
 417
 418 /* byte operand */
 419 #define b_mode                  1
 420 /* byte operand with operand swapped */
 421 #define b_swap_mode             (b_mode + 1)
 422 /* operand size depends on prefixes */
 423 #define v_mode                  (b_swap_mode + 1)
 424 /* operand size depends on prefixes with operand swapped */
 425 #define v_swap_mode             (v_mode + 1)
 426 /* word operand */
 427 #define w_mode                  (v_swap_mode + 1)
 428 /* double word operand  */
 429 #define d_mode                  (w_mode + 1)
 430 /* quad word operand */
 431 #define q_mode                  (d_mode + 1)
 432 /* quad word operand with operand swapped */
 433 #define q_swap_mode             (q_mode + 1)
 434 /* ten-byte operand */
 435 #define t_mode                  (q_swap_mode + 1)
 436 /* 16-byte XMM or 32-byte YMM operand */
 437 #define x_mode                  (t_mode + 1)
 438 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 439 #define x_swap_mode             (x_mode + 1)
 440 /* 16-byte XMM operand */
 441 #define xmm_mode                (x_swap_mode + 1)
 442 /* 16-byte XMM or quad word operand */
 443 #define xmmq_mode               (xmm_mode + 1)
 444 /* 32-byte YMM or quad word operand */
 445 #define ymmq_mode               (xmmq_mode + 1)
 446 /* d_mode in 32bit, q_mode in 64bit mode.  */
 447 #define m_mode                  (ymmq_mode + 1)
 448 /* pair of v_mode operands */
 449 #define a_mode                  (m_mode + 1)
 450 #define cond_jump_mode          (a_mode + 1)
 451 #define loop_jcxz_mode          (cond_jump_mode + 1)
 452 /* operand size depends on REX prefixes.  */
 453 #define dq_mode                 (loop_jcxz_mode + 1)
 454 /* registers like dq_mode, memory like w_mode.  */
 455 #define dqw_mode                (dq_mode + 1)
 456 /* 4- or 6-byte pointer operand */
 457 #define f_mode                  (dqw_mode + 1)
 458 #define const_1_mode            (f_mode + 1)
 459 /* v_mode for stack-related opcodes.  */
 460 #define stack_v_mode            (const_1_mode + 1)
 461 /* non-quad operand size depends on prefixes */
 462 #define z_mode                  (stack_v_mode + 1)
 463 /* 16-byte operand */
 464 #define o_mode                  (z_mode + 1)
 465 /* registers like dq_mode, memory like b_mode.  */
 466 #define dqb_mode                (o_mode + 1)
 467 /* registers like dq_mode, memory like d_mode.  */
 468 #define dqd_mode                (dqb_mode + 1)
 469 /* normal vex mode */
 470 #define vex_mode                (dqd_mode + 1)
 471 /* 128bit vex mode */
 472 #define vex128_mode             (vex_mode + 1)
 473 /* 256bit vex mode */
 474 #define vex256_mode             (vex128_mode + 1)
 475
 476 #define es_reg                  (vex256_mode + 1)
 477 #define cs_reg                  (es_reg + 1)
 478 #define ss_reg                  (cs_reg + 1)
 479 #define ds_reg                  (ss_reg + 1)
 480 #define fs_reg                  (ds_reg + 1)
 481 #define gs_reg                  (fs_reg + 1)
 482
 483 #define eAX_reg                 (gs_reg + 1)
 484 #define eCX_reg                 (eAX_reg + 1)
 485 #define eDX_reg                 (eCX_reg + 1)
 486 #define eBX_reg                 (eDX_reg + 1)
 487 #define eSP_reg                 (eBX_reg + 1)
 488 #define eBP_reg                 (eSP_reg + 1)
 489 #define eSI_reg                 (eBP_reg + 1)
 490 #define eDI_reg                 (eSI_reg + 1)
 491
 492 #define al_reg                  (eDI_reg + 1)
 493 #define cl_reg                  (al_reg + 1)
 494 #define dl_reg                  (cl_reg + 1)
 495 #define bl_reg                  (dl_reg + 1)
 496 #define ah_reg                  (bl_reg + 1)
 497 #define ch_reg                  (ah_reg + 1)
 498 #define dh_reg                  (ch_reg + 1)
 499 #define bh_reg                  (dh_reg + 1)
 500
 501 #define ax_reg                  (bh_reg + 1)
 502 #define cx_reg                  (ax_reg + 1)
 503 #define dx_reg                  (cx_reg + 1)
 504 #define bx_reg                  (dx_reg + 1)
 505 #define sp_reg                  (bx_reg + 1)
 506 #define bp_reg                  (sp_reg + 1)
 507 #define si_reg                  (bp_reg + 1)
 508 #define di_reg                  (si_reg + 1)
 509
 510 #define rAX_reg                 (di_reg + 1)
 511 #define rCX_reg                 (rAX_reg + 1)
 512 #define rDX_reg                 (rCX_reg + 1)
 513 #define rBX_reg                 (rDX_reg + 1)
 514 #define rSP_reg                 (rBX_reg + 1)
 515 #define rBP_reg                 (rSP_reg + 1)
 516 #define rSI_reg                 (rBP_reg + 1)
 517 #define rDI_reg                 (rSI_reg + 1)
 518
 519 #define z_mode_ax_reg           (rDI_reg + 1)
 520 #define indir_dx_reg            (z_mode_ax_reg + 1)
 521
 522 #define MAX_BYTEMODE    indir_dx_reg
 523
 524 /* Flags that are OR'ed into the bytemode field to pass extra
 525    information.  */
 526 #define DREX_OC1                0x10000 /* OC1 bit set */
 527 #define DREX_NO_OC0             0x20000 /* OC0 bit not used */
 528 #define DREX_MASK               0x40000 /* mask to delete */
 529
 530 #if MAX_BYTEMODE >= DREX_OC1
 531 #error MAX_BYTEMODE must be less than DREX_OC1
 532 #endif
 533
 534 #define FLOATCODE               1
 535 #define USE_REG_TABLE           (FLOATCODE + 1)
 536 #define USE_MOD_TABLE           (USE_REG_TABLE + 1)
 537 #define USE_RM_TABLE            (USE_MOD_TABLE + 1)
 538 #define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)
 539 #define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)
 540 #define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)
 541 #define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)
 542 #define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)
 543 #define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)
 544
 545 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 546
 547 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 548 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 549 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 550 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 551 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 552 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 553 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 554 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 555 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 556 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 557
 558 #define REG_80                  0
 559 #define REG_81                  (REG_80 + 1)
 560 #define REG_82                  (REG_81 + 1)
 561 #define REG_8F                  (REG_82 + 1)
 562 #define REG_C0                  (REG_8F + 1)
 563 #define REG_C1                  (REG_C0 + 1)
 564 #define REG_C6                  (REG_C1 + 1)
 565 #define REG_C7                  (REG_C6 + 1)
 566 #define REG_D0                  (REG_C7 + 1)
 567 #define REG_D1                  (REG_D0 + 1)
 568 #define REG_D2                  (REG_D1 + 1)
 569 #define REG_D3                  (REG_D2 + 1)
 570 #define REG_F6                  (REG_D3 + 1)
 571 #define REG_F7                  (REG_F6 + 1)
 572 #define REG_FE                  (REG_F7 + 1)
 573 #define REG_FF                  (REG_FE + 1)
 574 #define REG_0F00                (REG_FF + 1)
 575 #define REG_0F01                (REG_0F00 + 1)
 576 #define REG_0F0D                (REG_0F01 + 1)
 577 #define REG_0F18                (REG_0F0D + 1)
 578 #define REG_0F71                (REG_0F18 + 1)
 579 #define REG_0F72                (REG_0F71 + 1)
 580 #define REG_0F73                (REG_0F72 + 1)
 581 #define REG_0FA6                (REG_0F73 + 1)
 582 #define REG_0FA7                (REG_0FA6 + 1)
 583 #define REG_0FAE                (REG_0FA7 + 1)
 584 #define REG_0FBA                (REG_0FAE + 1)
 585 #define REG_0FC7                (REG_0FBA + 1)
 586 #define REG_VEX_71              (REG_0FC7 + 1)
 587 #define REG_VEX_72              (REG_VEX_71 + 1)
 588 #define REG_VEX_73              (REG_VEX_72 + 1)
 589 #define REG_VEX_AE              (REG_VEX_73 + 1)
 590
 591 #define MOD_8D                  0
 592 #define MOD_0F01_REG_0          (MOD_8D + 1)
 593 #define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)
 594 #define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)
 595 #define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)
 596 #define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)
 597 #define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)
 598 #define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)
 599 #define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)
 600 #define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)
 601 #define MOD_0F18_REG_0          (MOD_0F17 + 1)
 602 #define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)
 603 #define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)
 604 #define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)
 605 #define MOD_0F20                (MOD_0F18_REG_3 + 1)
 606 #define MOD_0F21                (MOD_0F20 + 1)
 607 #define MOD_0F22                (MOD_0F21 + 1)
 608 #define MOD_0F23                (MOD_0F22 + 1)
 609 #define MOD_0F24                (MOD_0F23 + 1)
 610 #define MOD_0F26                (MOD_0F24 + 1)
 611 #define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)
 612 #define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)
 613 #define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)
 614 #define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)
 615 #define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)
 616 #define MOD_0F71_REG_2          (MOD_0F51 + 1)
 617 #define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)
 618 #define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)
 619 #define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)
 620 #define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)
 621 #define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)
 622 #define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)
 623 #define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)
 624 #define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)
 625 #define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)
 626 #define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)
 627 #define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)
 628 #define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)
 629 #define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)
 630 #define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)
 631 #define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)
 632 #define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)
 633 #define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)
 634 #define MOD_0FB2                (MOD_0FAE_REG_7 + 1)
 635 #define MOD_0FB4                (MOD_0FB2 + 1)
 636 #define MOD_0FB5                (MOD_0FB4 + 1)
 637 #define MOD_0FC7_REG_6          (MOD_0FB5 + 1)
 638 #define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)
 639 #define MOD_0FD7                (MOD_0FC7_REG_7 + 1)
 640 #define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)
 641 #define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)
 642 #define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)
 643 #define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)
 644 #define MOD_C4_32BIT            (MOD_62_32BIT + 1)
 645 #define MOD_C5_32BIT            (MOD_C4_32BIT + 1)
 646 #define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)
 647 #define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)
 648 #define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)
 649 #define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)
 650 #define MOD_VEX_2B              (MOD_VEX_17 + 1)
 651 #define MOD_VEX_51              (MOD_VEX_2B + 1)
 652 #define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)
 653 #define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)
 654 #define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)
 655 #define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)
 656 #define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)
 657 #define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)
 658 #define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)
 659 #define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)
 660 #define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)
 661 #define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)
 662 #define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)
 663 #define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)
 664 #define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)
 665 #define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)
 666 #define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)
 667 #define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)
 668 #define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)
 669 #define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)
 670 #define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)
 671 #define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)
 672 #define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)
 673 #define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)
 674 #define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)
 675
 676 #define RM_0F01_REG_0           0
 677 #define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)
 678 #define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)
 679 #define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)
 680 #define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)
 681 #define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)
 682 #define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)
 683 #define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)
 684
 685 #define PREFIX_90               0
 686 #define PREFIX_0F10             (PREFIX_90 + 1)
 687 #define PREFIX_0F11             (PREFIX_0F10 + 1)
 688 #define PREFIX_0F12             (PREFIX_0F11 + 1)
 689 #define PREFIX_0F16             (PREFIX_0F12 + 1)
 690 #define PREFIX_0F2A             (PREFIX_0F16 + 1)
 691 #define PREFIX_0F2B             (PREFIX_0F2A + 1)
 692 #define PREFIX_0F2C             (PREFIX_0F2B + 1)
 693 #define PREFIX_0F2D             (PREFIX_0F2C + 1)
 694 #define PREFIX_0F2E             (PREFIX_0F2D + 1)
 695 #define PREFIX_0F2F             (PREFIX_0F2E + 1)
 696 #define PREFIX_0F51             (PREFIX_0F2F + 1)
 697 #define PREFIX_0F52             (PREFIX_0F51 + 1)
 698 #define PREFIX_0F53             (PREFIX_0F52 + 1)
 699 #define PREFIX_0F58             (PREFIX_0F53 + 1)
 700 #define PREFIX_0F59             (PREFIX_0F58 + 1)
 701 #define PREFIX_0F5A             (PREFIX_0F59 + 1)
 702 #define PREFIX_0F5B             (PREFIX_0F5A + 1)
 703 #define PREFIX_0F5C             (PREFIX_0F5B + 1)
 704 #define PREFIX_0F5D             (PREFIX_0F5C + 1)
 705 #define PREFIX_0F5E             (PREFIX_0F5D + 1)
 706 #define PREFIX_0F5F             (PREFIX_0F5E + 1)
 707 #define PREFIX_0F60             (PREFIX_0F5F + 1)
 708 #define PREFIX_0F61             (PREFIX_0F60 + 1)
 709 #define PREFIX_0F62             (PREFIX_0F61 + 1)
 710 #define PREFIX_0F6C             (PREFIX_0F62 + 1)
 711 #define PREFIX_0F6D             (PREFIX_0F6C + 1)
 712 #define PREFIX_0F6F             (PREFIX_0F6D + 1)
 713 #define PREFIX_0F70             (PREFIX_0F6F + 1)
 714 #define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)
 715 #define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)
 716 #define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)
 717 #define PREFIX_0F79             (PREFIX_0F78 + 1)
 718 #define PREFIX_0F7C             (PREFIX_0F79 + 1)
 719 #define PREFIX_0F7D             (PREFIX_0F7C + 1)
 720 #define PREFIX_0F7E             (PREFIX_0F7D + 1)
 721 #define PREFIX_0F7F             (PREFIX_0F7E + 1)
 722 #define PREFIX_0FB8             (PREFIX_0F7F + 1)
 723 #define PREFIX_0FBD             (PREFIX_0FB8 + 1)
 724 #define PREFIX_0FC2             (PREFIX_0FBD + 1)
 725 #define PREFIX_0FC3             (PREFIX_0FC2 + 1)
 726 #define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)
 727 #define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)
 728 #define PREFIX_0FD6             (PREFIX_0FD0 + 1)
 729 #define PREFIX_0FE6             (PREFIX_0FD6 + 1)
 730 #define PREFIX_0FE7             (PREFIX_0FE6 + 1)
 731 #define PREFIX_0FF0             (PREFIX_0FE7 + 1)
 732 #define PREFIX_0FF7             (PREFIX_0FF0 + 1)
 733 #define PREFIX_0F3810           (PREFIX_0FF7 + 1)
 734 #define PREFIX_0F3814           (PREFIX_0F3810 + 1)
 735 #define PREFIX_0F3815           (PREFIX_0F3814 + 1)
 736 #define PREFIX_0F3817           (PREFIX_0F3815 + 1)
 737 #define PREFIX_0F3820           (PREFIX_0F3817 + 1)
 738 #define PREFIX_0F3821           (PREFIX_0F3820 + 1)
 739 #define PREFIX_0F3822           (PREFIX_0F3821 + 1)
 740 #define PREFIX_0F3823           (PREFIX_0F3822 + 1)
 741 #define PREFIX_0F3824           (PREFIX_0F3823 + 1)
 742 #define PREFIX_0F3825           (PREFIX_0F3824 + 1)
 743 #define PREFIX_0F3828           (PREFIX_0F3825 + 1)
 744 #define PREFIX_0F3829           (PREFIX_0F3828 + 1)
 745 #define PREFIX_0F382A           (PREFIX_0F3829 + 1)
 746 #define PREFIX_0F382B           (PREFIX_0F382A + 1)
 747 #define PREFIX_0F3830           (PREFIX_0F382B + 1)
 748 #define PREFIX_0F3831           (PREFIX_0F3830 + 1)
 749 #define PREFIX_0F3832           (PREFIX_0F3831 + 1)
 750 #define PREFIX_0F3833           (PREFIX_0F3832 + 1)
 751 #define PREFIX_0F3834           (PREFIX_0F3833 + 1)
 752 #define PREFIX_0F3835           (PREFIX_0F3834 + 1)
 753 #define PREFIX_0F3837           (PREFIX_0F3835 + 1)
 754 #define PREFIX_0F3838           (PREFIX_0F3837 + 1)
 755 #define PREFIX_0F3839           (PREFIX_0F3838 + 1)
 756 #define PREFIX_0F383A           (PREFIX_0F3839 + 1)
 757 #define PREFIX_0F383B           (PREFIX_0F383A + 1)
 758 #define PREFIX_0F383C           (PREFIX_0F383B + 1)
 759 #define PREFIX_0F383D           (PREFIX_0F383C + 1)
 760 #define PREFIX_0F383E           (PREFIX_0F383D + 1)
 761 #define PREFIX_0F383F           (PREFIX_0F383E + 1)
 762 #define PREFIX_0F3840           (PREFIX_0F383F + 1)
 763 #define PREFIX_0F3841           (PREFIX_0F3840 + 1)
 764 #define PREFIX_0F3880           (PREFIX_0F3841 + 1)
 765 #define PREFIX_0F3881           (PREFIX_0F3880 + 1)
 766 #define PREFIX_0F38DB           (PREFIX_0F3881 + 1)
 767 #define PREFIX_0F38DC           (PREFIX_0F38DB + 1)
 768 #define PREFIX_0F38DD           (PREFIX_0F38DC + 1)
 769 #define PREFIX_0F38DE           (PREFIX_0F38DD + 1)
 770 #define PREFIX_0F38DF           (PREFIX_0F38DE + 1)
 771 #define PREFIX_0F38F0           (PREFIX_0F38DF + 1)
 772 #define PREFIX_0F38F1           (PREFIX_0F38F0 + 1)
 773 #define PREFIX_0F3A08           (PREFIX_0F38F1 + 1)
 774 #define PREFIX_0F3A09           (PREFIX_0F3A08 + 1)
 775 #define PREFIX_0F3A0A           (PREFIX_0F3A09 + 1)
 776 #define PREFIX_0F3A0B           (PREFIX_0F3A0A + 1)
 777 #define PREFIX_0F3A0C           (PREFIX_0F3A0B + 1)
 778 #define PREFIX_0F3A0D           (PREFIX_0F3A0C + 1)
 779 #define PREFIX_0F3A0E           (PREFIX_0F3A0D + 1)
 780 #define PREFIX_0F3A14           (PREFIX_0F3A0E + 1)
 781 #define PREFIX_0F3A15           (PREFIX_0F3A14 + 1)
 782 #define PREFIX_0F3A16           (PREFIX_0F3A15 + 1)
 783 #define PREFIX_0F3A17           (PREFIX_0F3A16 + 1)
 784 #define PREFIX_0F3A20           (PREFIX_0F3A17 + 1)
 785 #define PREFIX_0F3A21           (PREFIX_0F3A20 + 1)
 786 #define PREFIX_0F3A22           (PREFIX_0F3A21 + 1)
 787 #define PREFIX_0F3A40           (PREFIX_0F3A22 + 1)
 788 #define PREFIX_0F3A41           (PREFIX_0F3A40 + 1)
 789 #define PREFIX_0F3A42           (PREFIX_0F3A41 + 1)
 790 #define PREFIX_0F3A44           (PREFIX_0F3A42 + 1)
 791 #define PREFIX_0F3A60           (PREFIX_0F3A44 + 1)
 792 #define PREFIX_0F3A61           (PREFIX_0F3A60 + 1)
 793 #define PREFIX_0F3A62           (PREFIX_0F3A61 + 1)
 794 #define PREFIX_0F3A63           (PREFIX_0F3A62 + 1)
 795 #define PREFIX_0F3ADF           (PREFIX_0F3A63 + 1)
 796 #define PREFIX_VEX_10           (PREFIX_0F3ADF + 1)
 797 #define PREFIX_VEX_11           (PREFIX_VEX_10 + 1)
 798 #define PREFIX_VEX_12           (PREFIX_VEX_11 + 1)
 799 #define PREFIX_VEX_16           (PREFIX_VEX_12 + 1)
 800 #define PREFIX_VEX_2A           (PREFIX_VEX_16 + 1)
 801 #define PREFIX_VEX_2C           (PREFIX_VEX_2A + 1)
 802 #define PREFIX_VEX_2D           (PREFIX_VEX_2C + 1)
 803 #define PREFIX_VEX_2E           (PREFIX_VEX_2D + 1)
 804 #define PREFIX_VEX_2F           (PREFIX_VEX_2E + 1)
 805 #define PREFIX_VEX_51           (PREFIX_VEX_2F + 1)
 806 #define PREFIX_VEX_52           (PREFIX_VEX_51 + 1)
 807 #define PREFIX_VEX_53           (PREFIX_VEX_52 + 1)
 808 #define PREFIX_VEX_58           (PREFIX_VEX_53 + 1)
 809 #define PREFIX_VEX_59           (PREFIX_VEX_58 + 1)
 810 #define PREFIX_VEX_5A           (PREFIX_VEX_59 + 1)
 811 #define PREFIX_VEX_5B           (PREFIX_VEX_5A + 1)
 812 #define PREFIX_VEX_5C           (PREFIX_VEX_5B + 1)
 813 #define PREFIX_VEX_5D           (PREFIX_VEX_5C + 1)
 814 #define PREFIX_VEX_5E           (PREFIX_VEX_5D + 1)
 815 #define PREFIX_VEX_5F           (PREFIX_VEX_5E + 1)
 816 #define PREFIX_VEX_60           (PREFIX_VEX_5F + 1)
 817 #define PREFIX_VEX_61           (PREFIX_VEX_60 + 1)
 818 #define PREFIX_VEX_62           (PREFIX_VEX_61 + 1)
 819 #define PREFIX_VEX_63           (PREFIX_VEX_62 + 1)
 820 #define PREFIX_VEX_64           (PREFIX_VEX_63 + 1)
 821 #define PREFIX_VEX_65           (PREFIX_VEX_64 + 1)
 822 #define PREFIX_VEX_66           (PREFIX_VEX_65 + 1)
 823 #define PREFIX_VEX_67           (PREFIX_VEX_66 + 1)
 824 #define PREFIX_VEX_68           (PREFIX_VEX_67 + 1)
 825 #define PREFIX_VEX_69           (PREFIX_VEX_68 + 1)
 826 #define PREFIX_VEX_6A           (PREFIX_VEX_69 + 1)
 827 #define PREFIX_VEX_6B           (PREFIX_VEX_6A + 1)
 828 #define PREFIX_VEX_6C           (PREFIX_VEX_6B + 1)
 829 #define PREFIX_VEX_6D           (PREFIX_VEX_6C + 1)
 830 #define PREFIX_VEX_6E           (PREFIX_VEX_6D + 1)
 831 #define PREFIX_VEX_6F           (PREFIX_VEX_6E + 1)
 832 #define PREFIX_VEX_70           (PREFIX_VEX_6F + 1)
 833 #define PREFIX_VEX_71_REG_2     (PREFIX_VEX_70 + 1)
 834 #define PREFIX_VEX_71_REG_4     (PREFIX_VEX_71_REG_2 + 1)
 835 #define PREFIX_VEX_71_REG_6     (PREFIX_VEX_71_REG_4 + 1)
 836 #define PREFIX_VEX_72_REG_2     (PREFIX_VEX_71_REG_6 + 1)
 837 #define PREFIX_VEX_72_REG_4     (PREFIX_VEX_72_REG_2 + 1)
 838 #define PREFIX_VEX_72_REG_6     (PREFIX_VEX_72_REG_4 + 1)
 839 #define PREFIX_VEX_73_REG_2     (PREFIX_VEX_72_REG_6 + 1)
 840 #define PREFIX_VEX_73_REG_3     (PREFIX_VEX_73_REG_2 + 1)
 841 #define PREFIX_VEX_73_REG_6     (PREFIX_VEX_73_REG_3 + 1)
 842 #define PREFIX_VEX_73_REG_7     (PREFIX_VEX_73_REG_6 + 1)
 843 #define PREFIX_VEX_74           (PREFIX_VEX_73_REG_7 + 1)
 844 #define PREFIX_VEX_75           (PREFIX_VEX_74 + 1)
 845 #define PREFIX_VEX_76           (PREFIX_VEX_75 + 1)
 846 #define PREFIX_VEX_77           (PREFIX_VEX_76 + 1)
 847 #define PREFIX_VEX_7C           (PREFIX_VEX_77 + 1)
 848 #define PREFIX_VEX_7D           (PREFIX_VEX_7C + 1)
 849 #define PREFIX_VEX_7E           (PREFIX_VEX_7D + 1)
 850 #define PREFIX_VEX_7F           (PREFIX_VEX_7E + 1)
 851 #define PREFIX_VEX_C2           (PREFIX_VEX_7F + 1)
 852 #define PREFIX_VEX_C4           (PREFIX_VEX_C2 + 1)
 853 #define PREFIX_VEX_C5           (PREFIX_VEX_C4 + 1)
 854 #define PREFIX_VEX_D0           (PREFIX_VEX_C5 + 1)
 855 #define PREFIX_VEX_D1           (PREFIX_VEX_D0 + 1)
 856 #define PREFIX_VEX_D2           (PREFIX_VEX_D1 + 1)
 857 #define PREFIX_VEX_D3           (PREFIX_VEX_D2 + 1)
 858 #define PREFIX_VEX_D4           (PREFIX_VEX_D3 + 1)
 859 #define PREFIX_VEX_D5           (PREFIX_VEX_D4 + 1)
 860 #define PREFIX_VEX_D6           (PREFIX_VEX_D5 + 1)
 861 #define PREFIX_VEX_D7           (PREFIX_VEX_D6 + 1)
 862 #define PREFIX_VEX_D8           (PREFIX_VEX_D7 + 1)
 863 #define PREFIX_VEX_D9           (PREFIX_VEX_D8 + 1)
 864 #define PREFIX_VEX_DA           (PREFIX_VEX_D9 + 1)
 865 #define PREFIX_VEX_DB           (PREFIX_VEX_DA + 1)
 866 #define PREFIX_VEX_DC           (PREFIX_VEX_DB + 1)
 867 #define PREFIX_VEX_DD           (PREFIX_VEX_DC + 1)
 868 #define PREFIX_VEX_DE           (PREFIX_VEX_DD + 1)
 869 #define PREFIX_VEX_DF           (PREFIX_VEX_DE + 1)
 870 #define PREFIX_VEX_E0           (PREFIX_VEX_DF + 1)
 871 #define PREFIX_VEX_E1           (PREFIX_VEX_E0 + 1)
 872 #define PREFIX_VEX_E2           (PREFIX_VEX_E1 + 1)
 873 #define PREFIX_VEX_E3           (PREFIX_VEX_E2 + 1)
 874 #define PREFIX_VEX_E4           (PREFIX_VEX_E3 + 1)
 875 #define PREFIX_VEX_E5           (PREFIX_VEX_E4 + 1)
 876 #define PREFIX_VEX_E6           (PREFIX_VEX_E5 + 1)
 877 #define PREFIX_VEX_E7           (PREFIX_VEX_E6 + 1)
 878 #define PREFIX_VEX_E8           (PREFIX_VEX_E7 + 1)
 879 #define PREFIX_VEX_E9           (PREFIX_VEX_E8 + 1)
 880 #define PREFIX_VEX_EA           (PREFIX_VEX_E9 + 1)
 881 #define PREFIX_VEX_EB           (PREFIX_VEX_EA + 1)
 882 #define PREFIX_VEX_EC           (PREFIX_VEX_EB + 1)
 883 #define PREFIX_VEX_ED           (PREFIX_VEX_EC + 1)
 884 #define PREFIX_VEX_EE           (PREFIX_VEX_ED + 1)
 885 #define PREFIX_VEX_EF           (PREFIX_VEX_EE + 1)
 886 #define PREFIX_VEX_F0           (PREFIX_VEX_EF + 1)
 887 #define PREFIX_VEX_F1           (PREFIX_VEX_F0 + 1)
 888 #define PREFIX_VEX_F2           (PREFIX_VEX_F1 + 1)
 889 #define PREFIX_VEX_F3           (PREFIX_VEX_F2 + 1)
 890 #define PREFIX_VEX_F4           (PREFIX_VEX_F3 + 1)
 891 #define PREFIX_VEX_F5           (PREFIX_VEX_F4 + 1)
 892 #define PREFIX_VEX_F6           (PREFIX_VEX_F5 + 1)
 893 #define PREFIX_VEX_F7           (PREFIX_VEX_F6 + 1)
 894 #define PREFIX_VEX_F8           (PREFIX_VEX_F7 + 1)
 895 #define PREFIX_VEX_F9           (PREFIX_VEX_F8 + 1)
 896 #define PREFIX_VEX_FA           (PREFIX_VEX_F9 + 1)
 897 #define PREFIX_VEX_FB           (PREFIX_VEX_FA + 1)
 898 #define PREFIX_VEX_FC           (PREFIX_VEX_FB + 1)
 899 #define PREFIX_VEX_FD           (PREFIX_VEX_FC + 1)
 900 #define PREFIX_VEX_FE           (PREFIX_VEX_FD + 1)
 901 #define PREFIX_VEX_3800         (PREFIX_VEX_FE + 1)
 902 #define PREFIX_VEX_3801         (PREFIX_VEX_3800 + 1)
 903 #define PREFIX_VEX_3802         (PREFIX_VEX_3801 + 1)
 904 #define PREFIX_VEX_3803         (PREFIX_VEX_3802 + 1)
 905 #define PREFIX_VEX_3804         (PREFIX_VEX_3803 + 1)
 906 #define PREFIX_VEX_3805         (PREFIX_VEX_3804 + 1)
 907 #define PREFIX_VEX_3806         (PREFIX_VEX_3805 + 1)
 908 #define PREFIX_VEX_3807         (PREFIX_VEX_3806 + 1)
 909 #define PREFIX_VEX_3808         (PREFIX_VEX_3807 + 1)
 910 #define PREFIX_VEX_3809         (PREFIX_VEX_3808 + 1)
 911 #define PREFIX_VEX_380A         (PREFIX_VEX_3809 + 1)
 912 #define PREFIX_VEX_380B         (PREFIX_VEX_380A + 1)
 913 #define PREFIX_VEX_380C         (PREFIX_VEX_380B + 1)
 914 #define PREFIX_VEX_380D         (PREFIX_VEX_380C + 1)
 915 #define PREFIX_VEX_380E         (PREFIX_VEX_380D + 1)
 916 #define PREFIX_VEX_380F         (PREFIX_VEX_380E + 1)
 917 #define PREFIX_VEX_3817         (PREFIX_VEX_380F + 1)
 918 #define PREFIX_VEX_3818         (PREFIX_VEX_3817 + 1)
 919 #define PREFIX_VEX_3819         (PREFIX_VEX_3818 + 1)
 920 #define PREFIX_VEX_381A         (PREFIX_VEX_3819 + 1)
 921 #define PREFIX_VEX_381C         (PREFIX_VEX_381A + 1)
 922 #define PREFIX_VEX_381D         (PREFIX_VEX_381C + 1)
 923 #define PREFIX_VEX_381E         (PREFIX_VEX_381D + 1)
 924 #define PREFIX_VEX_3820         (PREFIX_VEX_381E + 1)
 925 #define PREFIX_VEX_3821         (PREFIX_VEX_3820 + 1)
 926 #define PREFIX_VEX_3822         (PREFIX_VEX_3821 + 1)
 927 #define PREFIX_VEX_3823         (PREFIX_VEX_3822 + 1)
 928 #define PREFIX_VEX_3824         (PREFIX_VEX_3823 + 1)
 929 #define PREFIX_VEX_3825         (PREFIX_VEX_3824 + 1)
 930 #define PREFIX_VEX_3828         (PREFIX_VEX_3825 + 1)
 931 #define PREFIX_VEX_3829         (PREFIX_VEX_3828 + 1)
 932 #define PREFIX_VEX_382A         (PREFIX_VEX_3829 + 1)
 933 #define PREFIX_VEX_382B         (PREFIX_VEX_382A + 1)
 934 #define PREFIX_VEX_382C         (PREFIX_VEX_382B + 1)
 935 #define PREFIX_VEX_382D         (PREFIX_VEX_382C + 1)
 936 #define PREFIX_VEX_382E         (PREFIX_VEX_382D + 1)
 937 #define PREFIX_VEX_382F         (PREFIX_VEX_382E + 1)
 938 #define PREFIX_VEX_3830         (PREFIX_VEX_382F + 1)
 939 #define PREFIX_VEX_3831         (PREFIX_VEX_3830 + 1)
 940 #define PREFIX_VEX_3832         (PREFIX_VEX_3831 + 1)
 941 #define PREFIX_VEX_3833         (PREFIX_VEX_3832 + 1)
 942 #define PREFIX_VEX_3834         (PREFIX_VEX_3833 + 1)
 943 #define PREFIX_VEX_3835         (PREFIX_VEX_3834 + 1)
 944 #define PREFIX_VEX_3837         (PREFIX_VEX_3835 + 1)
 945 #define PREFIX_VEX_3838         (PREFIX_VEX_3837 + 1)
 946 #define PREFIX_VEX_3839         (PREFIX_VEX_3838 + 1)
 947 #define PREFIX_VEX_383A         (PREFIX_VEX_3839 + 1)
 948 #define PREFIX_VEX_383B         (PREFIX_VEX_383A + 1)
 949 #define PREFIX_VEX_383C         (PREFIX_VEX_383B + 1)
 950 #define PREFIX_VEX_383D         (PREFIX_VEX_383C + 1)
 951 #define PREFIX_VEX_383E         (PREFIX_VEX_383D + 1)
 952 #define PREFIX_VEX_383F         (PREFIX_VEX_383E + 1)
 953 #define PREFIX_VEX_3840         (PREFIX_VEX_383F + 1)
 954 #define PREFIX_VEX_3841         (PREFIX_VEX_3840 + 1)
 955 #define PREFIX_VEX_38DB         (PREFIX_VEX_3841 + 1)
 956 #define PREFIX_VEX_38DC         (PREFIX_VEX_38DB + 1)
 957 #define PREFIX_VEX_38DD         (PREFIX_VEX_38DC + 1)
 958 #define PREFIX_VEX_38DE         (PREFIX_VEX_38DD + 1)
 959 #define PREFIX_VEX_38DF         (PREFIX_VEX_38DE + 1)
 960 #define PREFIX_VEX_3A04         (PREFIX_VEX_38DF + 1)
 961 #define PREFIX_VEX_3A05         (PREFIX_VEX_3A04 + 1)
 962 #define PREFIX_VEX_3A06         (PREFIX_VEX_3A05 + 1)
 963 #define PREFIX_VEX_3A08         (PREFIX_VEX_3A06 + 1)
 964 #define PREFIX_VEX_3A09         (PREFIX_VEX_3A08 + 1)
 965 #define PREFIX_VEX_3A0A         (PREFIX_VEX_3A09 + 1)
 966 #define PREFIX_VEX_3A0B         (PREFIX_VEX_3A0A + 1)
 967 #define PREFIX_VEX_3A0C         (PREFIX_VEX_3A0B + 1)
 968 #define PREFIX_VEX_3A0D         (PREFIX_VEX_3A0C + 1)
 969 #define PREFIX_VEX_3A0E         (PREFIX_VEX_3A0D + 1)
 970 #define PREFIX_VEX_3A0F         (PREFIX_VEX_3A0E + 1)
 971 #define PREFIX_VEX_3A14         (PREFIX_VEX_3A0F + 1)
 972 #define PREFIX_VEX_3A15         (PREFIX_VEX_3A14 + 1)
 973 #define PREFIX_VEX_3A16         (PREFIX_VEX_3A15 + 1)
 974 #define PREFIX_VEX_3A17         (PREFIX_VEX_3A16 + 1)
 975 #define PREFIX_VEX_3A18         (PREFIX_VEX_3A17 + 1)
 976 #define PREFIX_VEX_3A19         (PREFIX_VEX_3A18 + 1)
 977 #define PREFIX_VEX_3A20         (PREFIX_VEX_3A19 + 1)
 978 #define PREFIX_VEX_3A21         (PREFIX_VEX_3A20 + 1)
 979 #define PREFIX_VEX_3A22         (PREFIX_VEX_3A21 + 1)
 980 #define PREFIX_VEX_3A40         (PREFIX_VEX_3A22 + 1)
 981 #define PREFIX_VEX_3A41         (PREFIX_VEX_3A40 + 1)
 982 #define PREFIX_VEX_3A42         (PREFIX_VEX_3A41 + 1)
 983 #define PREFIX_VEX_3A48         (PREFIX_VEX_3A42 + 1)
 984 #define PREFIX_VEX_3A49         (PREFIX_VEX_3A48 + 1)
 985 #define PREFIX_VEX_3A4A         (PREFIX_VEX_3A49 + 1)
 986 #define PREFIX_VEX_3A4B         (PREFIX_VEX_3A4A + 1)
 987 #define PREFIX_VEX_3A4C         (PREFIX_VEX_3A4B + 1)
 988 #define PREFIX_VEX_3A5C         (PREFIX_VEX_3A4C + 1)
 989 #define PREFIX_VEX_3A5D         (PREFIX_VEX_3A5C + 1)
 990 #define PREFIX_VEX_3A5E         (PREFIX_VEX_3A5D + 1)
 991 #define PREFIX_VEX_3A5F         (PREFIX_VEX_3A5E + 1)
 992 #define PREFIX_VEX_3A60         (PREFIX_VEX_3A5F + 1)
 993 #define PREFIX_VEX_3A61         (PREFIX_VEX_3A60 + 1)
 994 #define PREFIX_VEX_3A62         (PREFIX_VEX_3A61 + 1)
 995 #define PREFIX_VEX_3A63         (PREFIX_VEX_3A62 + 1)
 996 #define PREFIX_VEX_3A68         (PREFIX_VEX_3A63 + 1)
 997 #define PREFIX_VEX_3A69         (PREFIX_VEX_3A68 + 1)
 998 #define PREFIX_VEX_3A6A         (PREFIX_VEX_3A69 + 1)
 999 #define PREFIX_VEX_3A6B         (PREFIX_VEX_3A6A + 1)
1000 #define PREFIX_VEX_3A6C         (PREFIX_VEX_3A6B + 1)
1001 #define PREFIX_VEX_3A6D         (PREFIX_VEX_3A6C + 1)
1002 #define PREFIX_VEX_3A6E         (PREFIX_VEX_3A6D + 1)
1003 #define PREFIX_VEX_3A6F         (PREFIX_VEX_3A6E + 1)
1004 #define PREFIX_VEX_3A78         (PREFIX_VEX_3A6F + 1)
1005 #define PREFIX_VEX_3A79         (PREFIX_VEX_3A78 + 1)
1006 #define PREFIX_VEX_3A7A         (PREFIX_VEX_3A79 + 1)
1007 #define PREFIX_VEX_3A7B         (PREFIX_VEX_3A7A + 1)
1008 #define PREFIX_VEX_3A7C         (PREFIX_VEX_3A7B + 1)
1009 #define PREFIX_VEX_3A7D         (PREFIX_VEX_3A7C + 1)
1010 #define PREFIX_VEX_3A7E         (PREFIX_VEX_3A7D + 1)
1011 #define PREFIX_VEX_3A7F         (PREFIX_VEX_3A7E + 1)
1012 #define PREFIX_VEX_3ADF         (PREFIX_VEX_3A7F + 1)
1013
1014 #define X86_64_06               0
1015 #define X86_64_07               (X86_64_06 + 1)
1016 #define X86_64_0D               (X86_64_07 + 1)
1017 #define X86_64_16               (X86_64_0D + 1)
1018 #define X86_64_17               (X86_64_16 + 1)
1019 #define X86_64_1E               (X86_64_17 + 1)
1020 #define X86_64_1F               (X86_64_1E + 1)
1021 #define X86_64_27               (X86_64_1F + 1)
1022 #define X86_64_2F               (X86_64_27 + 1)
1023 #define X86_64_37               (X86_64_2F + 1)
1024 #define X86_64_3F               (X86_64_37 + 1)
1025 #define X86_64_60               (X86_64_3F + 1)
1026 #define X86_64_61               (X86_64_60 + 1)
1027 #define X86_64_62               (X86_64_61 + 1)
1028 #define X86_64_63               (X86_64_62 + 1)
1029 #define X86_64_6D               (X86_64_63 + 1)
1030 #define X86_64_6F               (X86_64_6D + 1)
1031 #define X86_64_9A               (X86_64_6F + 1)
1032 #define X86_64_C4               (X86_64_9A + 1)
1033 #define X86_64_C5               (X86_64_C4 + 1)
1034 #define X86_64_CE               (X86_64_C5 + 1)
1035 #define X86_64_D4               (X86_64_CE + 1)
1036 #define X86_64_D5               (X86_64_D4 + 1)
1037 #define X86_64_EA               (X86_64_D5 + 1)
1038 #define X86_64_0F01_REG_0       (X86_64_EA + 1)
1039 #define X86_64_0F01_REG_1       (X86_64_0F01_REG_0 + 1)
1040 #define X86_64_0F01_REG_2       (X86_64_0F01_REG_1 + 1)
1041 #define X86_64_0F01_REG_3       (X86_64_0F01_REG_2 + 1)
1042
1043 #define THREE_BYTE_0F24         0
1044 #define THREE_BYTE_0F25         (THREE_BYTE_0F24 + 1)
1045 #define THREE_BYTE_0F38         (THREE_BYTE_0F25 + 1)
1046 #define THREE_BYTE_0F3A         (THREE_BYTE_0F38 + 1)
1047 #define THREE_BYTE_0F7A         (THREE_BYTE_0F3A + 1)
1048 #define THREE_BYTE_0F7B         (THREE_BYTE_0F7A + 1)
1049
1050 #define VEX_0F                  0
1051 #define VEX_0F38                (VEX_0F + 1)
1052 #define VEX_0F3A                (VEX_0F38 + 1)
1053
1054 #define VEX_LEN_10_P_1  0
1055 #define VEX_LEN_10_P_3  (VEX_LEN_10_P_1 + 1)
1056 #define VEX_LEN_11_P_1  (VEX_LEN_10_P_3 + 1)
1057 #define VEX_LEN_11_P_3  (VEX_LEN_11_P_1 + 1)
1058 #define VEX_LEN_12_P_0_M_0      (VEX_LEN_11_P_3 + 1)
1059 #define VEX_LEN_12_P_0_M_1      (VEX_LEN_12_P_0_M_0 + 1)
1060 #define VEX_LEN_12_P_2  (VEX_LEN_12_P_0_M_1 + 1)
1061 #define VEX_LEN_13_M_0  (VEX_LEN_12_P_2 + 1)
1062 #define VEX_LEN_16_P_0_M_0      (VEX_LEN_13_M_0 + 1)
1063 #define VEX_LEN_16_P_0_M_1      (VEX_LEN_16_P_0_M_0 + 1)
1064 #define VEX_LEN_16_P_2  (VEX_LEN_16_P_0_M_1 + 1)
1065 #define VEX_LEN_17_M_0  (VEX_LEN_16_P_2 + 1)
1066 #define VEX_LEN_2A_P_1  (VEX_LEN_17_M_0 + 1)
1067 #define VEX_LEN_2A_P_3  (VEX_LEN_2A_P_1 + 1)
1068 #define VEX_LEN_2B_M_0  (VEX_LEN_2A_P_3 + 1)
1069 #define VEX_LEN_2C_P_1  (VEX_LEN_2B_M_0 + 1)
1070 #define VEX_LEN_2C_P_3  (VEX_LEN_2C_P_1 + 1)
1071 #define VEX_LEN_2D_P_1  (VEX_LEN_2C_P_3 + 1)
1072 #define VEX_LEN_2D_P_3  (VEX_LEN_2D_P_1 + 1)
1073 #define VEX_LEN_2E_P_0  (VEX_LEN_2D_P_3 + 1)
1074 #define VEX_LEN_2E_P_2  (VEX_LEN_2E_P_0 + 1)
1075 #define VEX_LEN_2F_P_0  (VEX_LEN_2E_P_2 + 1)
1076 #define VEX_LEN_2F_P_2  (VEX_LEN_2F_P_0 + 1)
1077 #define VEX_LEN_51_P_1  (VEX_LEN_2F_P_2 + 1)
1078 #define VEX_LEN_51_P_3  (VEX_LEN_51_P_1 + 1)
1079 #define VEX_LEN_52_P_1  (VEX_LEN_51_P_3 + 1)
1080 #define VEX_LEN_53_P_1  (VEX_LEN_52_P_1 + 1)
1081 #define VEX_LEN_58_P_1  (VEX_LEN_53_P_1 + 1)
1082 #define VEX_LEN_58_P_3  (VEX_LEN_58_P_1 + 1)
1083 #define VEX_LEN_59_P_1  (VEX_LEN_58_P_3 + 1)
1084 #define VEX_LEN_59_P_3  (VEX_LEN_59_P_1 + 1)
1085 #define VEX_LEN_5A_P_1  (VEX_LEN_59_P_3 + 1)
1086 #define VEX_LEN_5A_P_3  (VEX_LEN_5A_P_1 + 1)
1087 #define VEX_LEN_5C_P_1  (VEX_LEN_5A_P_3 + 1)
1088 #define VEX_LEN_5C_P_3  (VEX_LEN_5C_P_1 + 1)
1089 #define VEX_LEN_5D_P_1  (VEX_LEN_5C_P_3 + 1)
1090 #define VEX_LEN_5D_P_3  (VEX_LEN_5D_P_1 + 1)
1091 #define VEX_LEN_5E_P_1  (VEX_LEN_5D_P_3 + 1)
1092 #define VEX_LEN_5E_P_3  (VEX_LEN_5E_P_1 + 1)
1093 #define VEX_LEN_5F_P_1  (VEX_LEN_5E_P_3 + 1)
1094 #define VEX_LEN_5F_P_3  (VEX_LEN_5F_P_1 + 1)
1095 #define VEX_LEN_60_P_2  (VEX_LEN_5F_P_3 + 1)
1096 #define VEX_LEN_61_P_2  (VEX_LEN_60_P_2 + 1)
1097 #define VEX_LEN_62_P_2  (VEX_LEN_61_P_2 + 1)
1098 #define VEX_LEN_63_P_2  (VEX_LEN_62_P_2 + 1)
1099 #define VEX_LEN_64_P_2  (VEX_LEN_63_P_2 + 1)
1100 #define VEX_LEN_65_P_2  (VEX_LEN_64_P_2 + 1)
1101 #define VEX_LEN_66_P_2  (VEX_LEN_65_P_2 + 1)
1102 #define VEX_LEN_67_P_2  (VEX_LEN_66_P_2 + 1)
1103 #define VEX_LEN_68_P_2  (VEX_LEN_67_P_2 + 1)
1104 #define VEX_LEN_69_P_2  (VEX_LEN_68_P_2 + 1)
1105 #define VEX_LEN_6A_P_2  (VEX_LEN_69_P_2 + 1)
1106 #define VEX_LEN_6B_P_2  (VEX_LEN_6A_P_2 + 1)
1107 #define VEX_LEN_6C_P_2  (VEX_LEN_6B_P_2 + 1)
1108 #define VEX_LEN_6D_P_2  (VEX_LEN_6C_P_2 + 1)
1109 #define VEX_LEN_6E_P_2  (VEX_LEN_6D_P_2 + 1)
1110 #define VEX_LEN_70_P_1  (VEX_LEN_6E_P_2 + 1)
1111 #define VEX_LEN_70_P_2  (VEX_LEN_70_P_1 + 1)
1112 #define VEX_LEN_70_P_3  (VEX_LEN_70_P_2 + 1)
1113 #define VEX_LEN_71_R_2_P_2      (VEX_LEN_70_P_3 + 1)
1114 #define VEX_LEN_71_R_4_P_2      (VEX_LEN_71_R_2_P_2 + 1)
1115 #define VEX_LEN_71_R_6_P_2      (VEX_LEN_71_R_4_P_2 + 1)
1116 #define VEX_LEN_72_R_2_P_2      (VEX_LEN_71_R_6_P_2 + 1)
1117 #define VEX_LEN_72_R_4_P_2      (VEX_LEN_72_R_2_P_2 + 1)
1118 #define VEX_LEN_72_R_6_P_2      (VEX_LEN_72_R_4_P_2 + 1)
1119 #define VEX_LEN_73_R_2_P_2      (VEX_LEN_72_R_6_P_2 + 1)
1120 #define VEX_LEN_73_R_3_P_2      (VEX_LEN_73_R_2_P_2 + 1)
1121 #define VEX_LEN_73_R_6_P_2      (VEX_LEN_73_R_3_P_2 + 1)
1122 #define VEX_LEN_73_R_7_P_2      (VEX_LEN_73_R_6_P_2 + 1)
1123 #define VEX_LEN_74_P_2  (VEX_LEN_73_R_7_P_2 + 1)
1124 #define VEX_LEN_75_P_2  (VEX_LEN_74_P_2 + 1)
1125 #define VEX_LEN_76_P_2  (VEX_LEN_75_P_2 + 1)
1126 #define VEX_LEN_7E_P_1  (VEX_LEN_76_P_2 + 1)
1127 #define VEX_LEN_7E_P_2  (VEX_LEN_7E_P_1 + 1)
1128 #define VEX_LEN_AE_R_2_M_0      (VEX_LEN_7E_P_2 + 1)
1129 #define VEX_LEN_AE_R_3_M_0      (VEX_LEN_AE_R_2_M_0 + 1)
1130 #define VEX_LEN_C2_P_1  (VEX_LEN_AE_R_3_M_0 + 1)
1131 #define VEX_LEN_C2_P_3  (VEX_LEN_C2_P_1 + 1)
1132 #define VEX_LEN_C4_P_2  (VEX_LEN_C2_P_3 + 1)
1133 #define VEX_LEN_C5_P_2  (VEX_LEN_C4_P_2 + 1)
1134 #define VEX_LEN_D1_P_2  (VEX_LEN_C5_P_2 + 1)
1135 #define VEX_LEN_D2_P_2  (VEX_LEN_D1_P_2 + 1)
1136 #define VEX_LEN_D3_P_2  (VEX_LEN_D2_P_2 + 1)
1137 #define VEX_LEN_D4_P_2  (VEX_LEN_D3_P_2 + 1)
1138 #define VEX_LEN_D5_P_2  (VEX_LEN_D4_P_2 + 1)
1139 #define VEX_LEN_D6_P_2  (VEX_LEN_D5_P_2 + 1)
1140 #define VEX_LEN_D7_P_2_M_1      (VEX_LEN_D6_P_2 + 1)
1141 #define VEX_LEN_D8_P_2  (VEX_LEN_D7_P_2_M_1 + 1)
1142 #define VEX_LEN_D9_P_2  (VEX_LEN_D8_P_2 + 1)
1143 #define VEX_LEN_DA_P_2  (VEX_LEN_D9_P_2 + 1)
1144 #define VEX_LEN_DB_P_2  (VEX_LEN_DA_P_2 + 1)
1145 #define VEX_LEN_DC_P_2  (VEX_LEN_DB_P_2 + 1)
1146 #define VEX_LEN_DD_P_2  (VEX_LEN_DC_P_2 + 1)
1147 #define VEX_LEN_DE_P_2  (VEX_LEN_DD_P_2 + 1)
1148 #define VEX_LEN_DF_P_2  (VEX_LEN_DE_P_2 + 1)
1149 #define VEX_LEN_E0_P_2  (VEX_LEN_DF_P_2 + 1)
1150 #define VEX_LEN_E1_P_2  (VEX_LEN_E0_P_2 + 1)
1151 #define VEX_LEN_E2_P_2  (VEX_LEN_E1_P_2 + 1)
1152 #define VEX_LEN_E3_P_2  (VEX_LEN_E2_P_2 + 1)
1153 #define VEX_LEN_E4_P_2  (VEX_LEN_E3_P_2 + 1)
1154 #define VEX_LEN_E5_P_2  (VEX_LEN_E4_P_2 + 1)
1155 #define VEX_LEN_E7_P_2_M_0      (VEX_LEN_E5_P_2 + 1)
1156 #define VEX_LEN_E8_P_2  (VEX_LEN_E7_P_2_M_0 + 1)
1157 #define VEX_LEN_E9_P_2  (VEX_LEN_E8_P_2 + 1)
1158 #define VEX_LEN_EA_P_2  (VEX_LEN_E9_P_2 + 1)
1159 #define VEX_LEN_EB_P_2  (VEX_LEN_EA_P_2 + 1)
1160 #define VEX_LEN_EC_P_2  (VEX_LEN_EB_P_2 + 1)
1161 #define VEX_LEN_ED_P_2  (VEX_LEN_EC_P_2 + 1)
1162 #define VEX_LEN_EE_P_2  (VEX_LEN_ED_P_2 + 1)
1163 #define VEX_LEN_EF_P_2  (VEX_LEN_EE_P_2 + 1)
1164 #define VEX_LEN_F1_P_2  (VEX_LEN_EF_P_2 + 1)
1165 #define VEX_LEN_F2_P_2  (VEX_LEN_F1_P_2 + 1)
1166 #define VEX_LEN_F3_P_2  (VEX_LEN_F2_P_2 + 1)
1167 #define VEX_LEN_F4_P_2  (VEX_LEN_F3_P_2 + 1)
1168 #define VEX_LEN_F5_P_2  (VEX_LEN_F4_P_2 + 1)
1169 #define VEX_LEN_F6_P_2  (VEX_LEN_F5_P_2 + 1)
1170 #define VEX_LEN_F7_P_2  (VEX_LEN_F6_P_2 + 1)
1171 #define VEX_LEN_F8_P_2  (VEX_LEN_F7_P_2 + 1)
1172 #define VEX_LEN_F9_P_2  (VEX_LEN_F8_P_2 + 1)
1173 #define VEX_LEN_FA_P_2  (VEX_LEN_F9_P_2 + 1)
1174 #define VEX_LEN_FB_P_2  (VEX_LEN_FA_P_2 + 1)
1175 #define VEX_LEN_FC_P_2  (VEX_LEN_FB_P_2 + 1)
1176 #define VEX_LEN_FD_P_2  (VEX_LEN_FC_P_2 + 1)
1177 #define VEX_LEN_FE_P_2  (VEX_LEN_FD_P_2 + 1)
1178 #define VEX_LEN_3800_P_2        (VEX_LEN_FE_P_2 + 1)
1179 #define VEX_LEN_3801_P_2        (VEX_LEN_3800_P_2 + 1)
1180 #define VEX_LEN_3802_P_2        (VEX_LEN_3801_P_2 + 1)
1181 #define VEX_LEN_3803_P_2        (VEX_LEN_3802_P_2 + 1)
1182 #define VEX_LEN_3804_P_2        (VEX_LEN_3803_P_2 + 1)
1183 #define VEX_LEN_3805_P_2        (VEX_LEN_3804_P_2 + 1)
1184 #define VEX_LEN_3806_P_2        (VEX_LEN_3805_P_2 + 1)
1185 #define VEX_LEN_3807_P_2        (VEX_LEN_3806_P_2 + 1)
1186 #define VEX_LEN_3808_P_2        (VEX_LEN_3807_P_2 + 1)
1187 #define VEX_LEN_3809_P_2        (VEX_LEN_3808_P_2 + 1)
1188 #define VEX_LEN_380A_P_2        (VEX_LEN_3809_P_2 + 1)
1189 #define VEX_LEN_380B_P_2        (VEX_LEN_380A_P_2 + 1)
1190 #define VEX_LEN_3819_P_2_M_0    (VEX_LEN_380B_P_2 + 1)
1191 #define VEX_LEN_381A_P_2_M_0    (VEX_LEN_3819_P_2_M_0 + 1)
1192 #define VEX_LEN_381C_P_2        (VEX_LEN_381A_P_2_M_0 + 1)
1193 #define VEX_LEN_381D_P_2        (VEX_LEN_381C_P_2 + 1)
1194 #define VEX_LEN_381E_P_2        (VEX_LEN_381D_P_2 + 1)
1195 #define VEX_LEN_3820_P_2        (VEX_LEN_381E_P_2 + 1)
1196 #define VEX_LEN_3821_P_2        (VEX_LEN_3820_P_2 + 1)
1197 #define VEX_LEN_3822_P_2        (VEX_LEN_3821_P_2 + 1)
1198 #define VEX_LEN_3823_P_2        (VEX_LEN_3822_P_2 + 1)
1199 #define VEX_LEN_3824_P_2        (VEX_LEN_3823_P_2 + 1)
1200 #define VEX_LEN_3825_P_2        (VEX_LEN_3824_P_2 + 1)
1201 #define VEX_LEN_3828_P_2        (VEX_LEN_3825_P_2 + 1)
1202 #define VEX_LEN_3829_P_2        (VEX_LEN_3828_P_2 + 1)
1203 #define VEX_LEN_382A_P_2_M_0    (VEX_LEN_3829_P_2 + 1)
1204 #define VEX_LEN_382B_P_2        (VEX_LEN_382A_P_2_M_0 + 1)
1205 #define VEX_LEN_3830_P_2        (VEX_LEN_382B_P_2 + 1)
1206 #define VEX_LEN_3831_P_2        (VEX_LEN_3830_P_2 + 1)
1207 #define VEX_LEN_3832_P_2        (VEX_LEN_3831_P_2 + 1)
1208 #define VEX_LEN_3833_P_2        (VEX_LEN_3832_P_2 + 1)
1209 #define VEX_LEN_3834_P_2        (VEX_LEN_3833_P_2 + 1)
1210 #define VEX_LEN_3835_P_2        (VEX_LEN_3834_P_2 + 1)
1211 #define VEX_LEN_3837_P_2        (VEX_LEN_3835_P_2 + 1)
1212 #define VEX_LEN_3838_P_2        (VEX_LEN_3837_P_2 + 1)
1213 #define VEX_LEN_3839_P_2        (VEX_LEN_3838_P_2 + 1)
1214 #define VEX_LEN_383A_P_2        (VEX_LEN_3839_P_2 + 1)
1215 #define VEX_LEN_383B_P_2        (VEX_LEN_383A_P_2 + 1)
1216 #define VEX_LEN_383C_P_2        (VEX_LEN_383B_P_2 + 1)
1217 #define VEX_LEN_383D_P_2        (VEX_LEN_383C_P_2 + 1)
1218 #define VEX_LEN_383E_P_2        (VEX_LEN_383D_P_2 + 1)
1219 #define VEX_LEN_383F_P_2        (VEX_LEN_383E_P_2 + 1)
1220 #define VEX_LEN_3840_P_2        (VEX_LEN_383F_P_2 + 1)
1221 #define VEX_LEN_3841_P_2        (VEX_LEN_3840_P_2 + 1)
1222 #define VEX_LEN_38DB_P_2        (VEX_LEN_3841_P_2 + 1)
1223 #define VEX_LEN_38DC_P_2        (VEX_LEN_38DB_P_2 + 1)
1224 #define VEX_LEN_38DD_P_2        (VEX_LEN_38DC_P_2 + 1)
1225 #define VEX_LEN_38DE_P_2        (VEX_LEN_38DD_P_2 + 1)
1226 #define VEX_LEN_38DF_P_2        (VEX_LEN_38DE_P_2 + 1)
1227 #define VEX_LEN_3A06_P_2        (VEX_LEN_38DF_P_2 + 1)
1228 #define VEX_LEN_3A0A_P_2        (VEX_LEN_3A06_P_2 + 1)
1229 #define VEX_LEN_3A0B_P_2        (VEX_LEN_3A0A_P_2 + 1)
1230 #define VEX_LEN_3A0E_P_2        (VEX_LEN_3A0B_P_2 + 1)
1231 #define VEX_LEN_3A0F_P_2        (VEX_LEN_3A0E_P_2 + 1)
1232 #define VEX_LEN_3A14_P_2        (VEX_LEN_3A0F_P_2 + 1)
1233 #define VEX_LEN_3A15_P_2        (VEX_LEN_3A14_P_2 + 1)
1234 #define VEX_LEN_3A16_P_2        (VEX_LEN_3A15_P_2 + 1)
1235 #define VEX_LEN_3A17_P_2        (VEX_LEN_3A16_P_2 + 1)
1236 #define VEX_LEN_3A18_P_2        (VEX_LEN_3A17_P_2 + 1)
1237 #define VEX_LEN_3A19_P_2        (VEX_LEN_3A18_P_2 + 1)
1238 #define VEX_LEN_3A20_P_2        (VEX_LEN_3A19_P_2 + 1)
1239 #define VEX_LEN_3A21_P_2        (VEX_LEN_3A20_P_2 + 1)
1240 #define VEX_LEN_3A22_P_2        (VEX_LEN_3A21_P_2 + 1)
1241 #define VEX_LEN_3A41_P_2        (VEX_LEN_3A22_P_2 + 1)
1242 #define VEX_LEN_3A42_P_2        (VEX_LEN_3A41_P_2 + 1)
1243 #define VEX_LEN_3A4C_P_2        (VEX_LEN_3A42_P_2 + 1)
1244 #define VEX_LEN_3A60_P_2        (VEX_LEN_3A4C_P_2 + 1)
1245 #define VEX_LEN_3A61_P_2        (VEX_LEN_3A60_P_2 + 1)
1246 #define VEX_LEN_3A62_P_2        (VEX_LEN_3A61_P_2 + 1)
1247 #define VEX_LEN_3A63_P_2        (VEX_LEN_3A62_P_2 + 1)
1248 #define VEX_LEN_3A6A_P_2        (VEX_LEN_3A63_P_2 + 1)
1249 #define VEX_LEN_3A6B_P_2        (VEX_LEN_3A6A_P_2 + 1)
1250 #define VEX_LEN_3A6E_P_2        (VEX_LEN_3A6B_P_2 + 1)
1251 #define VEX_LEN_3A6F_P_2        (VEX_LEN_3A6E_P_2 + 1)
1252 #define VEX_LEN_3A7A_P_2        (VEX_LEN_3A6F_P_2 + 1)
1253 #define VEX_LEN_3A7B_P_2        (VEX_LEN_3A7A_P_2 + 1)
1254 #define VEX_LEN_3A7E_P_2        (VEX_LEN_3A7B_P_2 + 1)
1255 #define VEX_LEN_3A7F_P_2        (VEX_LEN_3A7E_P_2 + 1)
1256 #define VEX_LEN_3ADF_P_2        (VEX_LEN_3A7F_P_2 + 1)
1257
1258 typedef void (*op_rtn) (int bytemode, int sizeflag);
1259
1260 struct dis386 {
1261   const char *name;
1262   struct
1263     {
1264       op_rtn rtn;
1265       int bytemode;
1266     } op[MAX_OPERANDS];
1267 };
1268
1269 /* Upper case letters in the instruction names here are macros.
1270    'A' => print 'b' if no register operands or suffix_always is true
1271    'B' => print 'b' if suffix_always is true
1272    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1273           size prefix
1274    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1275           suffix_always is true
1276    'E' => print 'e' if 32-bit form of jcxz
1277    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1278    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1279    'H' => print ",pt" or ",pn" branch hint
1280    'I' => honor following macro letter even in Intel mode (implemented only
1281           for some of the macro letters)
1282    'J' => print 'l'
1283    'K' => print 'd' or 'q' if rex prefix is present.
1284    'L' => print 'l' if suffix_always is true
1285    'M' => print 'r' if intel_mnemonic is false.
1286    'N' => print 'n' if instruction has no wait "prefix"
1287    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1288    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1289           or suffix_always is true.  print 'q' if rex prefix is present.
1290    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1291           is true
1292    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1293    'S' => print 'w', 'l' or 'q' if suffix_always is true
1294    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1295    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1296    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1297    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1298    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1299    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1300           suffix_always is true.
1301    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1302    '!' => change condition from true to false or from false to true.
1303    '%' => add 1 upper case letter to the macro.
1304
1305    2 upper case letter macros:
1306    "XY" => print 'x' or 'y' if no register operands or suffix_always
1307            is true.
1308    'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1309            or suffix_always is true
1310
1311    Many of the above letters print nothing in Intel mode.  See "putop"
1312    for the details.
1313
1314    Braces '{' and '}', and vertical bars '|', indicate alternative
1315    mnemonic strings for AT&T and Intel.  */
1316
1317 static const struct dis386 dis386[] = {
1318   /* 00 */
1319   { "addB",             { Eb, Gb } },
1320   { "addS",             { Ev, Gv } },
1321   { "addB",             { Gb, Eb } },
1322   { "addS",             { Gv, Ev } },
1323   { "addB",             { AL, Ib } },
1324   { "addS",             { eAX, Iv } },
1325   { X86_64_TABLE (X86_64_06) },
1326   { X86_64_TABLE (X86_64_07) },
1327   /* 08 */
1328   { "orB",              { Eb, Gb } },
1329   { "orS",              { Ev, Gv } },
1330   { "orB",              { Gb, Eb } },
1331   { "orS",              { Gv, Ev } },
1332   { "orB",              { AL, Ib } },
1333   { "orS",              { eAX, Iv } },
1334   { X86_64_TABLE (X86_64_0D) },
1335   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1336   /* 10 */
1337   { "adcB",             { Eb, Gb } },
1338   { "adcS",             { Ev, Gv } },
1339   { "adcB",             { Gb, Eb } },
1340   { "adcS",             { Gv, Ev } },
1341   { "adcB",             { AL, Ib } },
1342   { "adcS",             { eAX, Iv } },
1343   { X86_64_TABLE (X86_64_16) },
1344   { X86_64_TABLE (X86_64_17) },
1345   /* 18 */
1346   { "sbbB",             { Eb, Gb } },
1347   { "sbbS",             { Ev, Gv } },
1348   { "sbbB",             { Gb, Eb } },
1349   { "sbbS",             { Gv, Ev } },
1350   { "sbbB",             { AL, Ib } },
1351   { "sbbS",             { eAX, Iv } },
1352   { X86_64_TABLE (X86_64_1E) },
1353   { X86_64_TABLE (X86_64_1F) },
1354   /* 20 */
1355   { "andB",             { Eb, Gb } },
1356   { "andS",             { Ev, Gv } },
1357   { "andB",             { Gb, Eb } },
1358   { "andS",             { Gv, Ev } },
1359   { "andB",             { AL, Ib } },
1360   { "andS",             { eAX, Iv } },
1361   { "(bad)",            { XX } },       /* SEG ES prefix */
1362   { X86_64_TABLE (X86_64_27) },
1363   /* 28 */
1364   { "subB",             { Eb, Gb } },
1365   { "subS",             { Ev, Gv } },
1366   { "subB",             { Gb, Eb } },
1367   { "subS",             { Gv, Ev } },
1368   { "subB",             { AL, Ib } },
1369   { "subS",             { eAX, Iv } },
1370   { "(bad)",            { XX } },       /* SEG CS prefix */
1371   { X86_64_TABLE (X86_64_2F) },
1372   /* 30 */
1373   { "xorB",             { Eb, Gb } },
1374   { "xorS",             { Ev, Gv } },
1375   { "xorB",             { Gb, Eb } },
1376   { "xorS",             { Gv, Ev } },
1377   { "xorB",             { AL, Ib } },
1378   { "xorS",             { eAX, Iv } },
1379   { "(bad)",            { XX } },       /* SEG SS prefix */
1380   { X86_64_TABLE (X86_64_37) },
1381   /* 38 */
1382   { "cmpB",             { Eb, Gb } },
1383   { "cmpS",             { Ev, Gv } },
1384   { "cmpB",             { Gb, Eb } },
1385   { "cmpS",             { Gv, Ev } },
1386   { "cmpB",             { AL, Ib } },
1387   { "cmpS",             { eAX, Iv } },
1388   { "(bad)",            { XX } },       /* SEG DS prefix */
1389   { X86_64_TABLE (X86_64_3F) },
1390   /* 40 */
1391   { "inc{S|}",          { RMeAX } },
1392   { "inc{S|}",          { RMeCX } },
1393   { "inc{S|}",          { RMeDX } },
1394   { "inc{S|}",          { RMeBX } },
1395   { "inc{S|}",          { RMeSP } },
1396   { "inc{S|}",          { RMeBP } },
1397   { "inc{S|}",          { RMeSI } },
1398   { "inc{S|}",          { RMeDI } },
1399   /* 48 */
1400   { "dec{S|}",          { RMeAX } },
1401   { "dec{S|}",          { RMeCX } },
1402   { "dec{S|}",          { RMeDX } },
1403   { "dec{S|}",          { RMeBX } },
1404   { "dec{S|}",          { RMeSP } },
1405   { "dec{S|}",          { RMeBP } },
1406   { "dec{S|}",          { RMeSI } },
1407   { "dec{S|}",          { RMeDI } },
1408   /* 50 */
1409   { "pushV",            { RMrAX } },
1410   { "pushV",            { RMrCX } },
1411   { "pushV",            { RMrDX } },
1412   { "pushV",            { RMrBX } },
1413   { "pushV",            { RMrSP } },
1414   { "pushV",            { RMrBP } },
1415   { "pushV",            { RMrSI } },
1416   { "pushV",            { RMrDI } },
1417   /* 58 */
1418   { "popV",             { RMrAX } },
1419   { "popV",             { RMrCX } },
1420   { "popV",             { RMrDX } },
1421   { "popV",             { RMrBX } },
1422   { "popV",             { RMrSP } },
1423   { "popV",             { RMrBP } },
1424   { "popV",             { RMrSI } },
1425   { "popV",             { RMrDI } },
1426   /* 60 */
1427   { X86_64_TABLE (X86_64_60) },
1428   { X86_64_TABLE (X86_64_61) },
1429   { X86_64_TABLE (X86_64_62) },
1430   { X86_64_TABLE (X86_64_63) },
1431   { "(bad)",            { XX } },       /* seg fs */
1432   { "(bad)",            { XX } },       /* seg gs */
1433   { "(bad)",            { XX } },       /* op size prefix */
1434   { "(bad)",            { XX } },       /* adr size prefix */
1435   /* 68 */
1436   { "pushT",            { Iq } },
1437   { "imulS",            { Gv, Ev, Iv } },
1438   { "pushT",            { sIb } },
1439   { "imulS",            { Gv, Ev, sIb } },
1440   { "ins{b|}",          { Ybr, indirDX } },
1441   { X86_64_TABLE (X86_64_6D) },
1442   { "outs{b|}",         { indirDXr, Xb } },
1443   { X86_64_TABLE (X86_64_6F) },
1444   /* 70 */
1445   { "joH",              { Jb, XX, cond_jump_flag } },
1446   { "jnoH",             { Jb, XX, cond_jump_flag } },
1447   { "jbH",              { Jb, XX, cond_jump_flag } },
1448   { "jaeH",             { Jb, XX, cond_jump_flag } },
1449   { "jeH",              { Jb, XX, cond_jump_flag } },
1450   { "jneH",             { Jb, XX, cond_jump_flag } },
1451   { "jbeH",             { Jb, XX, cond_jump_flag } },
1452   { "jaH",              { Jb, XX, cond_jump_flag } },
1453   /* 78 */
1454   { "jsH",              { Jb, XX, cond_jump_flag } },
1455   { "jnsH",             { Jb, XX, cond_jump_flag } },
1456   { "jpH",              { Jb, XX, cond_jump_flag } },
1457   { "jnpH",             { Jb, XX, cond_jump_flag } },
1458   { "jlH",              { Jb, XX, cond_jump_flag } },
1459   { "jgeH",             { Jb, XX, cond_jump_flag } },
1460   { "jleH",             { Jb, XX, cond_jump_flag } },
1461   { "jgH",              { Jb, XX, cond_jump_flag } },
1462   /* 80 */
1463   { REG_TABLE (REG_80) },
1464   { REG_TABLE (REG_81) },
1465   { "(bad)",            { XX } },
1466   { REG_TABLE (REG_82) },
1467   { "testB",            { Eb, Gb } },
1468   { "testS",            { Ev, Gv } },
1469   { "xchgB",            { Eb, Gb } },
1470   { "xchgS",            { Ev, Gv } },
1471   /* 88 */
1472   { "movB",             { Eb, Gb } },
1473   { "movS",             { Ev, Gv } },
1474   { "movB",             { Gb, EbS } },
1475   { "movS",             { Gv, EvS } },
1476   { "movD",             { Sv, Sw } },
1477   { MOD_TABLE (MOD_8D) },
1478   { "movD",             { Sw, Sv } },
1479   { REG_TABLE (REG_8F) },
1480   /* 90 */
1481   { PREFIX_TABLE (PREFIX_90) },
1482   { "xchgS",            { RMeCX, eAX } },
1483   { "xchgS",            { RMeDX, eAX } },
1484   { "xchgS",            { RMeBX, eAX } },
1485   { "xchgS",            { RMeSP, eAX } },
1486   { "xchgS",            { RMeBP, eAX } },
1487   { "xchgS",            { RMeSI, eAX } },
1488   { "xchgS",            { RMeDI, eAX } },
1489   /* 98 */
1490   { "cW{t|}R",          { XX } },
1491   { "cR{t|}O",          { XX } },
1492   { X86_64_TABLE (X86_64_9A) },
1493   { "(bad)",            { XX } },       /* fwait */
1494   { "pushfT",           { XX } },
1495   { "popfT",            { XX } },
1496   { "sahf",             { XX } },
1497   { "lahf",             { XX } },
1498   /* a0 */
1499   { "movB",             { AL, Ob } },
1500   { "movS",             { eAX, Ov } },
1501   { "movB",             { Ob, AL } },
1502   { "movS",             { Ov, eAX } },
1503   { "movs{b|}",         { Ybr, Xb } },
1504   { "movs{R|}",         { Yvr, Xv } },
1505   { "cmps{b|}",         { Xb, Yb } },
1506   { "cmps{R|}",         { Xv, Yv } },
1507   /* a8 */
1508   { "testB",            { AL, Ib } },
1509   { "testS",            { eAX, Iv } },
1510   { "stosB",            { Ybr, AL } },
1511   { "stosS",            { Yvr, eAX } },
1512   { "lodsB",            { ALr, Xb } },
1513   { "lodsS",            { eAXr, Xv } },
1514   { "scasB",            { AL, Yb } },
1515   { "scasS",            { eAX, Yv } },
1516   /* b0 */
1517   { "movB",             { RMAL, Ib } },
1518   { "movB",             { RMCL, Ib } },
1519   { "movB",             { RMDL, Ib } },
1520   { "movB",             { RMBL, Ib } },
1521   { "movB",             { RMAH, Ib } },
1522   { "movB",             { RMCH, Ib } },
1523   { "movB",             { RMDH, Ib } },
1524   { "movB",             { RMBH, Ib } },
1525   /* b8 */
1526   { "movS",             { RMeAX, Iv64 } },
1527   { "movS",             { RMeCX, Iv64 } },
1528   { "movS",             { RMeDX, Iv64 } },
1529   { "movS",             { RMeBX, Iv64 } },
1530   { "movS",             { RMeSP, Iv64 } },
1531   { "movS",             { RMeBP, Iv64 } },
1532   { "movS",             { RMeSI, Iv64 } },
1533   { "movS",             { RMeDI, Iv64 } },
1534   /* c0 */
1535   { REG_TABLE (REG_C0) },
1536   { REG_TABLE (REG_C1) },
1537   { "retT",             { Iw } },
1538   { "retT",             { XX } },
1539   { X86_64_TABLE (X86_64_C4) },
1540   { X86_64_TABLE (X86_64_C5) },
1541   { REG_TABLE (REG_C6) },
1542   { REG_TABLE (REG_C7) },
1543   /* c8 */
1544   { "enterT",           { Iw, Ib } },
1545   { "leaveT",           { XX } },
1546   { "Jret{|f}P",        { Iw } },
1547   { "Jret{|f}P",        { XX } },
1548   { "int3",             { XX } },
1549   { "int",              { Ib } },
1550   { X86_64_TABLE (X86_64_CE) },
1551   { "iretP",            { XX } },
1552   /* d0 */
1553   { REG_TABLE (REG_D0) },
1554   { REG_TABLE (REG_D1) },
1555   { REG_TABLE (REG_D2) },
1556   { REG_TABLE (REG_D3) },
1557   { X86_64_TABLE (X86_64_D4) },
1558   { X86_64_TABLE (X86_64_D5) },
1559   { "(bad)",            { XX } },
1560   { "xlat",             { DSBX } },
1561   /* d8 */
1562   { FLOAT },
1563   { FLOAT },
1564   { FLOAT },
1565   { FLOAT },
1566   { FLOAT },
1567   { FLOAT },
1568   { FLOAT },
1569   { FLOAT },
1570   /* e0 */
1571   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1572   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1573   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1574   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1575   { "inB",              { AL, Ib } },
1576   { "inG",              { zAX, Ib } },
1577   { "outB",             { Ib, AL } },
1578   { "outG",             { Ib, zAX } },
1579   /* e8 */
1580   { "callT",            { Jv } },
1581   { "jmpT",             { Jv } },
1582   { X86_64_TABLE (X86_64_EA) },
1583   { "jmp",              { Jb } },
1584   { "inB",              { AL, indirDX } },
1585   { "inG",              { zAX, indirDX } },
1586   { "outB",             { indirDX, AL } },
1587   { "outG",             { indirDX, zAX } },
1588   /* f0 */
1589   { "(bad)",            { XX } },       /* lock prefix */
1590   { "icebp",            { XX } },
1591   { "(bad)",            { XX } },       /* repne */
1592   { "(bad)",            { XX } },       /* repz */
1593   { "hlt",              { XX } },
1594   { "cmc",              { XX } },
1595   { REG_TABLE (REG_F6) },
1596   { REG_TABLE (REG_F7) },
1597   /* f8 */
1598   { "clc",              { XX } },
1599   { "stc",              { XX } },
1600   { "cli",              { XX } },
1601   { "sti",              { XX } },
1602   { "cld",              { XX } },
1603   { "std",              { XX } },
1604   { REG_TABLE (REG_FE) },
1605   { REG_TABLE (REG_FF) },
1606 };
1607
1608 static const struct dis386 dis386_twobyte[] = {
1609   /* 00 */
1610   { REG_TABLE (REG_0F00 ) },
1611   { REG_TABLE (REG_0F01 ) },
1612   { "larS",             { Gv, Ew } },
1613   { "lslS",             { Gv, Ew } },
1614   { "(bad)",            { XX } },
1615   { "syscall",          { XX } },
1616   { "clts",             { XX } },
1617   { "sysretP",          { XX } },
1618   /* 08 */
1619   { "invd",             { XX } },
1620   { "wbinvd",           { XX } },
1621   { "(bad)",            { XX } },
1622   { "ud2a",             { XX } },
1623   { "(bad)",            { XX } },
1624   { REG_TABLE (REG_0F0D) },
1625   { "femms",            { XX } },
1626   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1627   /* 10 */
1628   { PREFIX_TABLE (PREFIX_0F10) },
1629   { PREFIX_TABLE (PREFIX_0F11) },
1630   { PREFIX_TABLE (PREFIX_0F12) },
1631   { MOD_TABLE (MOD_0F13) },
1632   { "unpcklpX",         { XM, EXx } },
1633   { "unpckhpX",         { XM, EXx } },
1634   { PREFIX_TABLE (PREFIX_0F16) },
1635   { MOD_TABLE (MOD_0F17) },
1636   /* 18 */
1637   { REG_TABLE (REG_0F18) },
1638   { "nopQ",             { Ev } },
1639   { "nopQ",             { Ev } },
1640   { "nopQ",             { Ev } },
1641   { "nopQ",             { Ev } },
1642   { "nopQ",             { Ev } },
1643   { "nopQ",             { Ev } },
1644   { "nopQ",             { Ev } },
1645   /* 20 */
1646   { MOD_TABLE (MOD_0F20) },
1647   { MOD_TABLE (MOD_0F21) },
1648   { MOD_TABLE (MOD_0F22) },
1649   { MOD_TABLE (MOD_0F23) },
1650   { MOD_TABLE (MOD_0F24) },
1651   { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1652   { MOD_TABLE (MOD_0F26) },
1653   { "(bad)",            { XX } },
1654   /* 28 */
1655   { "movapX",           { XM, EXx } },
1656   { "movapX",           { EXxS, XM } },
1657   { PREFIX_TABLE (PREFIX_0F2A) },
1658   { PREFIX_TABLE (PREFIX_0F2B) },
1659   { PREFIX_TABLE (PREFIX_0F2C) },
1660   { PREFIX_TABLE (PREFIX_0F2D) },
1661   { PREFIX_TABLE (PREFIX_0F2E) },
1662   { PREFIX_TABLE (PREFIX_0F2F) },
1663   /* 30 */
1664   { "wrmsr",            { XX } },
1665   { "rdtsc",            { XX } },
1666   { "rdmsr",            { XX } },
1667   { "rdpmc",            { XX } },
1668   { "sysenter",         { XX } },
1669   { "sysexit",          { XX } },
1670   { "(bad)",            { XX } },
1671   { "getsec",           { XX } },
1672   /* 38 */
1673   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1674   { "(bad)",            { XX } },
1675   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1676   { "(bad)",            { XX } },
1677   { "(bad)",            { XX } },
1678   { "(bad)",            { XX } },
1679   { "(bad)",            { XX } },
1680   { "(bad)",            { XX } },
1681   /* 40 */
1682   { "cmovoS",           { Gv, Ev } },
1683   { "cmovnoS",          { Gv, Ev } },
1684   { "cmovbS",           { Gv, Ev } },
1685   { "cmovaeS",          { Gv, Ev } },
1686   { "cmoveS",           { Gv, Ev } },
1687   { "cmovneS",          { Gv, Ev } },
1688   { "cmovbeS",          { Gv, Ev } },
1689   { "cmovaS",           { Gv, Ev } },
1690   /* 48 */
1691   { "cmovsS",           { Gv, Ev } },
1692   { "cmovnsS",          { Gv, Ev } },
1693   { "cmovpS",           { Gv, Ev } },
1694   { "cmovnpS",          { Gv, Ev } },
1695   { "cmovlS",           { Gv, Ev } },
1696   { "cmovgeS",          { Gv, Ev } },
1697   { "cmovleS",          { Gv, Ev } },
1698   { "cmovgS",           { Gv, Ev } },
1699   /* 50 */
1700   { MOD_TABLE (MOD_0F51) },
1701   { PREFIX_TABLE (PREFIX_0F51) },
1702   { PREFIX_TABLE (PREFIX_0F52) },
1703   { PREFIX_TABLE (PREFIX_0F53) },
1704   { "andpX",            { XM, EXx } },
1705   { "andnpX",           { XM, EXx } },
1706   { "orpX",             { XM, EXx } },
1707   { "xorpX",            { XM, EXx } },
1708   /* 58 */
1709   { PREFIX_TABLE (PREFIX_0F58) },
1710   { PREFIX_TABLE (PREFIX_0F59) },
1711   { PREFIX_TABLE (PREFIX_0F5A) },
1712   { PREFIX_TABLE (PREFIX_0F5B) },
1713   { PREFIX_TABLE (PREFIX_0F5C) },
1714   { PREFIX_TABLE (PREFIX_0F5D) },
1715   { PREFIX_TABLE (PREFIX_0F5E) },
1716   { PREFIX_TABLE (PREFIX_0F5F) },
1717   /* 60 */
1718   { PREFIX_TABLE (PREFIX_0F60) },
1719   { PREFIX_TABLE (PREFIX_0F61) },
1720   { PREFIX_TABLE (PREFIX_0F62) },
1721   { "packsswb",         { MX, EM } },
1722   { "pcmpgtb",          { MX, EM } },
1723   { "pcmpgtw",          { MX, EM } },
1724   { "pcmpgtd",          { MX, EM } },
1725   { "packuswb",         { MX, EM } },
1726   /* 68 */
1727   { "punpckhbw",        { MX, EM } },
1728   { "punpckhwd",        { MX, EM } },
1729   { "punpckhdq",        { MX, EM } },
1730   { "packssdw",         { MX, EM } },
1731   { PREFIX_TABLE (PREFIX_0F6C) },
1732   { PREFIX_TABLE (PREFIX_0F6D) },
1733   { "movK",             { MX, Edq } },
1734   { PREFIX_TABLE (PREFIX_0F6F) },
1735   /* 70 */
1736   { PREFIX_TABLE (PREFIX_0F70) },
1737   { REG_TABLE (REG_0F71) },
1738   { REG_TABLE (REG_0F72) },
1739   { REG_TABLE (REG_0F73) },
1740   { "pcmpeqb",          { MX, EM } },
1741   { "pcmpeqw",          { MX, EM } },
1742   { "pcmpeqd",          { MX, EM } },
1743   { "emms",             { XX } },
1744   /* 78 */
1745   { PREFIX_TABLE (PREFIX_0F78) },
1746   { PREFIX_TABLE (PREFIX_0F79) },
1747   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1748   { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1749   { PREFIX_TABLE (PREFIX_0F7C) },
1750   { PREFIX_TABLE (PREFIX_0F7D) },
1751   { PREFIX_TABLE (PREFIX_0F7E) },
1752   { PREFIX_TABLE (PREFIX_0F7F) },
1753   /* 80 */
1754   { "joH",              { Jv, XX, cond_jump_flag } },
1755   { "jnoH",             { Jv, XX, cond_jump_flag } },
1756   { "jbH",              { Jv, XX, cond_jump_flag } },
1757   { "jaeH",             { Jv, XX, cond_jump_flag } },
1758   { "jeH",              { Jv, XX, cond_jump_flag } },
1759   { "jneH",             { Jv, XX, cond_jump_flag } },
1760   { "jbeH",             { Jv, XX, cond_jump_flag } },
1761   { "jaH",              { Jv, XX, cond_jump_flag } },
1762   /* 88 */
1763   { "jsH",              { Jv, XX, cond_jump_flag } },
1764   { "jnsH",             { Jv, XX, cond_jump_flag } },
1765   { "jpH",              { Jv, XX, cond_jump_flag } },
1766   { "jnpH",             { Jv, XX, cond_jump_flag } },
1767   { "jlH",              { Jv, XX, cond_jump_flag } },
1768   { "jgeH",             { Jv, XX, cond_jump_flag } },
1769   { "jleH",             { Jv, XX, cond_jump_flag } },
1770   { "jgH",              { Jv, XX, cond_jump_flag } },
1771   /* 90 */
1772   { "seto",             { Eb } },
1773   { "setno",            { Eb } },
1774   { "setb",             { Eb } },
1775   { "setae",            { Eb } },
1776   { "sete",             { Eb } },
1777   { "setne",            { Eb } },
1778   { "setbe",            { Eb } },
1779   { "seta",             { Eb } },
1780   /* 98 */
1781   { "sets",             { Eb } },
1782   { "setns",            { Eb } },
1783   { "setp",             { Eb } },
1784   { "setnp",            { Eb } },
1785   { "setl",             { Eb } },
1786   { "setge",            { Eb } },
1787   { "setle",            { Eb } },
1788   { "setg",             { Eb } },
1789   /* a0 */
1790   { "pushT",            { fs } },
1791   { "popT",             { fs } },
1792   { "cpuid",            { XX } },
1793   { "btS",              { Ev, Gv } },
1794   { "shldS",            { Ev, Gv, Ib } },
1795   { "shldS",            { Ev, Gv, CL } },
1796   { REG_TABLE (REG_0FA6) },
1797   { REG_TABLE (REG_0FA7) },
1798   /* a8 */
1799   { "pushT",            { gs } },
1800   { "popT",             { gs } },
1801   { "rsm",              { XX } },
1802   { "btsS",             { Ev, Gv } },
1803   { "shrdS",            { Ev, Gv, Ib } },
1804   { "shrdS",            { Ev, Gv, CL } },
1805   { REG_TABLE (REG_0FAE) },
1806   { "imulS",            { Gv, Ev } },
1807   /* b0 */
1808   { "cmpxchgB",         { Eb, Gb } },
1809   { "cmpxchgS",         { Ev, Gv } },
1810   { MOD_TABLE (MOD_0FB2) },
1811   { "btrS",             { Ev, Gv } },
1812   { MOD_TABLE (MOD_0FB4) },
1813   { MOD_TABLE (MOD_0FB5) },
1814   { "movz{bR|x}",       { Gv, Eb } },
1815   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1816   /* b8 */
1817   { PREFIX_TABLE (PREFIX_0FB8) },
1818   { "ud2b",             { XX } },
1819   { REG_TABLE (REG_0FBA) },
1820   { "btcS",             { Ev, Gv } },
1821   { "bsfS",             { Gv, Ev } },
1822   { PREFIX_TABLE (PREFIX_0FBD) },
1823   { "movs{bR|x}",       { Gv, Eb } },
1824   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1825   /* c0 */
1826   { "xaddB",            { Eb, Gb } },
1827   { "xaddS",            { Ev, Gv } },
1828   { PREFIX_TABLE (PREFIX_0FC2) },
1829   { PREFIX_TABLE (PREFIX_0FC3) },
1830   { "pinsrw",           { MX, Edqw, Ib } },
1831   { "pextrw",           { Gdq, MS, Ib } },
1832   { "shufpX",           { XM, EXx, Ib } },
1833   { REG_TABLE (REG_0FC7) },
1834   /* c8 */
1835   { "bswap",            { RMeAX } },
1836   { "bswap",            { RMeCX } },
1837   { "bswap",            { RMeDX } },
1838   { "bswap",            { RMeBX } },
1839   { "bswap",            { RMeSP } },
1840   { "bswap",            { RMeBP } },
1841   { "bswap",            { RMeSI } },
1842   { "bswap",            { RMeDI } },
1843   /* d0 */
1844   { PREFIX_TABLE (PREFIX_0FD0) },
1845   { "psrlw",            { MX, EM } },
1846   { "psrld",            { MX, EM } },
1847   { "psrlq",            { MX, EM } },
1848   { "paddq",            { MX, EM } },
1849   { "pmullw",           { MX, EM } },
1850   { PREFIX_TABLE (PREFIX_0FD6) },
1851   { MOD_TABLE (MOD_0FD7) },
1852   /* d8 */
1853   { "psubusb",          { MX, EM } },
1854   { "psubusw",          { MX, EM } },
1855   { "pminub",           { MX, EM } },
1856   { "pand",             { MX, EM } },
1857   { "paddusb",          { MX, EM } },
1858   { "paddusw",          { MX, EM } },
1859   { "pmaxub",           { MX, EM } },
1860   { "pandn",            { MX, EM } },
1861   /* e0 */
1862   { "pavgb",            { MX, EM } },
1863   { "psraw",            { MX, EM } },
1864   { "psrad",            { MX, EM } },
1865   { "pavgw",            { MX, EM } },
1866   { "pmulhuw",          { MX, EM } },
1867   { "pmulhw",           { MX, EM } },
1868   { PREFIX_TABLE (PREFIX_0FE6) },
1869   { PREFIX_TABLE (PREFIX_0FE7) },
1870   /* e8 */
1871   { "psubsb",           { MX, EM } },
1872   { "psubsw",           { MX, EM } },
1873   { "pminsw",           { MX, EM } },
1874   { "por",              { MX, EM } },
1875   { "paddsb",           { MX, EM } },
1876   { "paddsw",           { MX, EM } },
1877   { "pmaxsw",           { MX, EM } },
1878   { "pxor",             { MX, EM } },
1879   /* f0 */
1880   { PREFIX_TABLE (PREFIX_0FF0) },
1881   { "psllw",            { MX, EM } },
1882   { "pslld",            { MX, EM } },
1883   { "psllq",            { MX, EM } },
1884   { "pmuludq",          { MX, EM } },
1885   { "pmaddwd",          { MX, EM } },
1886   { "psadbw",           { MX, EM } },
1887   { PREFIX_TABLE (PREFIX_0FF7) },
1888   /* f8 */
1889   { "psubb",            { MX, EM } },
1890   { "psubw",            { MX, EM } },
1891   { "psubd",            { MX, EM } },
1892   { "psubq",            { MX, EM } },
1893   { "paddb",            { MX, EM } },
1894   { "paddw",            { MX, EM } },
1895   { "paddd",            { MX, EM } },
1896   { "(bad)",            { XX } },
1897 };
1898
1899 static const unsigned char onebyte_has_modrm[256] = {
1900   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1901   /*       -------------------------------        */
1902   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1903   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1904   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1905   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1906   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1907   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1908   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1909   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1910   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1911   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1912   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1913   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1914   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1915   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1916   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1917   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1918   /*       -------------------------------        */
1919   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1920 };
1921
1922 static const unsigned char twobyte_has_modrm[256] = {
1923   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1924   /*       -------------------------------        */
1925   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1926   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1927   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1928   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1929   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1930   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1931   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1932   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1933   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1934   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1935   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1936   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1937   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1938   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1939   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1940   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1941   /*       -------------------------------        */
1942   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1943 };
1944
1945 static char obuf[100];
1946 static char *obufp;
1947 static char *mnemonicendp;
1948 static char scratchbuf[100];
1949 static unsigned char *start_codep;
1950 static unsigned char *insn_codep;
1951 static unsigned char *codep;
1952 static const char *lock_prefix;
1953 static const char *data_prefix;
1954 static const char *addr_prefix;
1955 static const char *repz_prefix;
1956 static const char *repnz_prefix;
1957 static disassemble_info *the_info;
1958 static struct
1959   {
1960     int mod;
1961     int reg;
1962     int rm;
1963   }
1964 modrm;
1965 static unsigned char need_modrm;
1966 static struct
1967   {
1968     int register_specifier;
1969     int length;
1970     int prefix;
1971     int w;
1972   }
1973 vex;
1974 static unsigned char need_vex;
1975 static unsigned char need_vex_reg;
1976 static unsigned char vex_w_done;
1977
1978 struct op
1979   {
1980     const char *name;
1981     unsigned int len;
1982   };
1983
1984 /* If we are accessing mod/rm/reg without need_modrm set, then the
1985    values are stale.  Hitting this abort likely indicates that you
1986    need to update onebyte_has_modrm or twobyte_has_modrm.  */
1987 #define MODRM_CHECK  if (!need_modrm) abort ()
1988
1989 static const char **names64;
1990 static const char **names32;
1991 static const char **names16;
1992 static const char **names8;
1993 static const char **names8rex;
1994 static const char **names_seg;
1995 static const char *index64;
1996 static const char *index32;
1997 static const char **index16;
1998
1999 static const char *intel_names64[] = {
2000   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2001   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2002 };
2003 static const char *intel_names32[] = {
2004   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2005   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2006 };
2007 static const char *intel_names16[] = {
2008   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2009   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2010 };
2011 static const char *intel_names8[] = {
2012   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2013 };
2014 static const char *intel_names8rex[] = {
2015   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2016   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2017 };
2018 static const char *intel_names_seg[] = {
2019   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2020 };
2021 static const char *intel_index64 = "riz";
2022 static const char *intel_index32 = "eiz";
2023 static const char *intel_index16[] = {
2024   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2025 };
2026
2027 static const char *att_names64[] = {
2028   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2029   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2030 };
2031 static const char *att_names32[] = {
2032   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2033   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2034 };
2035 static const char *att_names16[] = {
2036   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2037   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2038 };
2039 static const char *att_names8[] = {
2040   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2041 };
2042 static const char *att_names8rex[] = {
2043   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2044   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2045 };
2046 static const char *att_names_seg[] = {
2047   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2048 };
2049 static const char *att_index64 = "%riz";
2050 static const char *att_index32 = "%eiz";
2051 static const char *att_index16[] = {
2052   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2053 };
2054
2055 static const struct dis386 reg_table[][8] = {
2056   /* REG_80 */
2057   {
2058     { "addA",   { Eb, Ib } },
2059     { "orA",    { Eb, Ib } },
2060     { "adcA",   { Eb, Ib } },
2061     { "sbbA",   { Eb, Ib } },
2062     { "andA",   { Eb, Ib } },
2063     { "subA",   { Eb, Ib } },
2064     { "xorA",   { Eb, Ib } },
2065     { "cmpA",   { Eb, Ib } },
2066   },
2067   /* REG_81 */
2068   {
2069     { "addQ",   { Ev, Iv } },
2070     { "orQ",    { Ev, Iv } },
2071     { "adcQ",   { Ev, Iv } },
2072     { "sbbQ",   { Ev, Iv } },
2073     { "andQ",   { Ev, Iv } },
2074     { "subQ",   { Ev, Iv } },
2075     { "xorQ",   { Ev, Iv } },
2076     { "cmpQ",   { Ev, Iv } },
2077   },
2078   /* REG_82 */
2079   {
2080     { "addQ",   { Ev, sIb } },
2081     { "orQ",    { Ev, sIb } },
2082     { "adcQ",   { Ev, sIb } },
2083     { "sbbQ",   { Ev, sIb } },
2084     { "andQ",   { Ev, sIb } },
2085     { "subQ",   { Ev, sIb } },
2086     { "xorQ",   { Ev, sIb } },
2087     { "cmpQ",   { Ev, sIb } },
2088   },
2089   /* REG_8F */
2090   {
2091     { "popU",   { stackEv } },
2092     { "(bad)",  { XX } },
2093     { "(bad)",  { XX } },
2094     { "(bad)",  { XX } },
2095     { "(bad)",  { XX } },
2096     { "(bad)",  { XX } },
2097     { "(bad)",  { XX } },
2098     { "(bad)",  { XX } },
2099   },
2100   /* REG_C0 */
2101   {
2102     { "rolA",   { Eb, Ib } },
2103     { "rorA",   { Eb, Ib } },
2104     { "rclA",   { Eb, Ib } },
2105     { "rcrA",   { Eb, Ib } },
2106     { "shlA",   { Eb, Ib } },
2107     { "shrA",   { Eb, Ib } },
2108     { "(bad)",  { XX } },
2109     { "sarA",   { Eb, Ib } },
2110   },
2111   /* REG_C1 */
2112   {
2113     { "rolQ",   { Ev, Ib } },
2114     { "rorQ",   { Ev, Ib } },
2115     { "rclQ",   { Ev, Ib } },
2116     { "rcrQ",   { Ev, Ib } },
2117     { "shlQ",   { Ev, Ib } },
2118     { "shrQ",   { Ev, Ib } },
2119     { "(bad)",  { XX } },
2120     { "sarQ",   { Ev, Ib } },
2121   },
2122   /* REG_C6 */
2123   {
2124     { "movA",   { Eb, Ib } },
2125     { "(bad)",  { XX } },
2126     { "(bad)",  { XX } },
2127     { "(bad)",  { XX } },
2128     { "(bad)",  { XX } },
2129     { "(bad)",  { XX } },
2130     { "(bad)",  { XX } },
2131     { "(bad)",  { XX } },
2132   },
2133   /* REG_C7 */
2134   {
2135     { "movQ",   { Ev, Iv } },
2136     { "(bad)",  { XX } },
2137     { "(bad)",  { XX } },
2138     { "(bad)",  { XX } },
2139     { "(bad)",  { XX } },
2140     { "(bad)",  { XX } },
2141     { "(bad)",  { XX } },
2142     { "(bad)",  { XX } },
2143   },
2144   /* REG_D0 */
2145   {
2146     { "rolA",   { Eb, I1 } },
2147     { "rorA",   { Eb, I1 } },
2148     { "rclA",   { Eb, I1 } },
2149     { "rcrA",   { Eb, I1 } },
2150     { "shlA",   { Eb, I1 } },
2151     { "shrA",   { Eb, I1 } },
2152     { "(bad)",  { XX } },
2153     { "sarA",   { Eb, I1 } },
2154   },
2155   /* REG_D1 */
2156   {
2157     { "rolQ",   { Ev, I1 } },
2158     { "rorQ",   { Ev, I1 } },
2159     { "rclQ",   { Ev, I1 } },
2160     { "rcrQ",   { Ev, I1 } },
2161     { "shlQ",   { Ev, I1 } },
2162     { "shrQ",   { Ev, I1 } },
2163     { "(bad)",  { XX } },
2164     { "sarQ",   { Ev, I1 } },
2165   },
2166   /* REG_D2 */
2167   {
2168     { "rolA",   { Eb, CL } },
2169     { "rorA",   { Eb, CL } },
2170     { "rclA",   { Eb, CL } },
2171     { "rcrA",   { Eb, CL } },
2172     { "shlA",   { Eb, CL } },
2173     { "shrA",   { Eb, CL } },
2174     { "(bad)",  { XX } },
2175     { "sarA",   { Eb, CL } },
2176   },
2177   /* REG_D3 */
2178   {
2179     { "rolQ",   { Ev, CL } },
2180     { "rorQ",   { Ev, CL } },
2181     { "rclQ",   { Ev, CL } },
2182     { "rcrQ",   { Ev, CL } },
2183     { "shlQ",   { Ev, CL } },
2184     { "shrQ",   { Ev, CL } },
2185     { "(bad)",  { XX } },
2186     { "sarQ",   { Ev, CL } },
2187   },
2188   /* REG_F6 */
2189   {
2190     { "testA",  { Eb, Ib } },
2191     { "(bad)",  { XX } },
2192     { "notA",   { Eb } },
2193     { "negA",   { Eb } },
2194     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2195     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2196     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2197     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2198   },
2199   /* REG_F7 */
2200   {
2201     { "testQ",  { Ev, Iv } },
2202     { "(bad)",  { XX } },
2203     { "notQ",   { Ev } },
2204     { "negQ",   { Ev } },
2205     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2206     { "imulQ",  { Ev } },
2207     { "divQ",   { Ev } },
2208     { "idivQ",  { Ev } },
2209   },
2210   /* REG_FE */
2211   {
2212     { "incA",   { Eb } },
2213     { "decA",   { Eb } },
2214     { "(bad)",  { XX } },
2215     { "(bad)",  { XX } },
2216     { "(bad)",  { XX } },
2217     { "(bad)",  { XX } },
2218     { "(bad)",  { XX } },
2219     { "(bad)",  { XX } },
2220   },
2221   /* REG_FF */
2222   {
2223     { "incQ",   { Ev } },
2224     { "decQ",   { Ev } },
2225     { "callT",  { indirEv } },
2226     { "JcallT", { indirEp } },
2227     { "jmpT",   { indirEv } },
2228     { "JjmpT",  { indirEp } },
2229     { "pushU",  { stackEv } },
2230     { "(bad)",  { XX } },
2231   },
2232   /* REG_0F00 */
2233   {
2234     { "sldtD",  { Sv } },
2235     { "strD",   { Sv } },
2236     { "lldt",   { Ew } },
2237     { "ltr",    { Ew } },
2238     { "verr",   { Ew } },
2239     { "verw",   { Ew } },
2240     { "(bad)",  { XX } },
2241     { "(bad)",  { XX } },
2242   },
2243   /* REG_0F01 */
2244   {
2245     { MOD_TABLE (MOD_0F01_REG_0) },
2246     { MOD_TABLE (MOD_0F01_REG_1) },
2247     { MOD_TABLE (MOD_0F01_REG_2) },
2248     { MOD_TABLE (MOD_0F01_REG_3) },
2249     { "smswD",  { Sv } },
2250     { "(bad)",  { XX } },
2251     { "lmsw",   { Ew } },
2252     { MOD_TABLE (MOD_0F01_REG_7) },
2253   },
2254   /* REG_0F0D */
2255   {
2256     { "prefetch",       { Eb } },
2257     { "prefetchw",      { Eb } },
2258     { "(bad)",          { XX } },
2259     { "(bad)",          { XX } },
2260     { "(bad)",          { XX } },
2261     { "(bad)",          { XX } },
2262     { "(bad)",          { XX } },
2263     { "(bad)",          { XX } },
2264   },
2265   /* REG_0F18 */
2266   {
2267     { MOD_TABLE (MOD_0F18_REG_0) },
2268     { MOD_TABLE (MOD_0F18_REG_1) },
2269     { MOD_TABLE (MOD_0F18_REG_2) },
2270     { MOD_TABLE (MOD_0F18_REG_3) },
2271     { "(bad)",  { XX } },
2272     { "(bad)",  { XX } },
2273     { "(bad)",  { XX } },
2274     { "(bad)",  { XX } },
2275   },
2276   /* REG_0F71 */
2277   {
2278     { "(bad)",  { XX } },
2279     { "(bad)",  { XX } },
2280     { MOD_TABLE (MOD_0F71_REG_2) },
2281     { "(bad)",  { XX } },
2282     { MOD_TABLE (MOD_0F71_REG_4) },
2283     { "(bad)",  { XX } },
2284     { MOD_TABLE (MOD_0F71_REG_6) },
2285     { "(bad)",  { XX } },
2286   },
2287   /* REG_0F72 */
2288   {
2289     { "(bad)",  { XX } },
2290     { "(bad)",  { XX } },
2291     { MOD_TABLE (MOD_0F72_REG_2) },
2292     { "(bad)",  { XX } },
2293     { MOD_TABLE (MOD_0F72_REG_4) },
2294     { "(bad)",  { XX } },
2295     { MOD_TABLE (MOD_0F72_REG_6) },
2296     { "(bad)",  { XX } },
2297   },
2298   /* REG_0F73 */
2299   {
2300     { "(bad)",  { XX } },
2301     { "(bad)",  { XX } },
2302     { MOD_TABLE (MOD_0F73_REG_2) },
2303     { MOD_TABLE (MOD_0F73_REG_3) },
2304     { "(bad)",  { XX } },
2305     { "(bad)",  { XX } },
2306     { MOD_TABLE (MOD_0F73_REG_6) },
2307     { MOD_TABLE (MOD_0F73_REG_7) },
2308   },
2309   /* REG_0FA6 */
2310   {
2311     { "montmul",        { { OP_0f07, 0 } } },
2312     { "xsha1",          { { OP_0f07, 0 } } },
2313     { "xsha256",        { { OP_0f07, 0 } } },
2314     { "(bad)",          { { OP_0f07, 0 } } },
2315     { "(bad)",          { { OP_0f07, 0 } } },
2316     { "(bad)",          { { OP_0f07, 0 } } },
2317     { "(bad)",          { { OP_0f07, 0 } } },
2318     { "(bad)",          { { OP_0f07, 0 } } },
2319   },
2320   /* REG_0FA7 */
2321   {
2322     { "xstore-rng",     { { OP_0f07, 0 } } },
2323     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2324     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2325     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2326     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2327     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2328     { "(bad)",          { { OP_0f07, 0 } } },
2329     { "(bad)",          { { OP_0f07, 0 } } },
2330   },
2331   /* REG_0FAE */
2332   {
2333     { MOD_TABLE (MOD_0FAE_REG_0) },
2334     { MOD_TABLE (MOD_0FAE_REG_1) },
2335     { MOD_TABLE (MOD_0FAE_REG_2) },
2336     { MOD_TABLE (MOD_0FAE_REG_3) },
2337     { MOD_TABLE (MOD_0FAE_REG_4) },
2338     { MOD_TABLE (MOD_0FAE_REG_5) },
2339     { MOD_TABLE (MOD_0FAE_REG_6) },
2340     { MOD_TABLE (MOD_0FAE_REG_7) },
2341   },
2342   /* REG_0FBA */
2343   {
2344     { "(bad)",  { XX } },
2345     { "(bad)",  { XX } },
2346     { "(bad)",  { XX } },
2347     { "(bad)",  { XX } },
2348     { "btQ",    { Ev, Ib } },
2349     { "btsQ",   { Ev, Ib } },
2350     { "btrQ",   { Ev, Ib } },
2351     { "btcQ",   { Ev, Ib } },
2352   },
2353   /* REG_0FC7 */
2354   {
2355     { "(bad)",  { XX } },
2356     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2357     { "(bad)",  { XX } },
2358     { "(bad)",  { XX } },
2359     { "(bad)",  { XX } },
2360     { "(bad)",  { XX } },
2361     { MOD_TABLE (MOD_0FC7_REG_6) },
2362     { MOD_TABLE (MOD_0FC7_REG_7) },
2363   },
2364   /* REG_VEX_71 */
2365   {
2366     { "(bad)",  { XX } },
2367     { "(bad)",  { XX } },
2368     { MOD_TABLE (MOD_VEX_71_REG_2) },
2369     { "(bad)",  { XX } },
2370     { MOD_TABLE (MOD_VEX_71_REG_4) },
2371     { "(bad)",  { XX } },
2372     { MOD_TABLE (MOD_VEX_71_REG_6) },
2373     { "(bad)",  { XX } },
2374   },
2375   /* REG_VEX_72 */
2376   {
2377     { "(bad)",  { XX } },
2378     { "(bad)",  { XX } },
2379     { MOD_TABLE (MOD_VEX_72_REG_2) },
2380     { "(bad)",  { XX } },
2381     { MOD_TABLE (MOD_VEX_72_REG_4) },
2382     { "(bad)",  { XX } },
2383     { MOD_TABLE (MOD_VEX_72_REG_6) },
2384     { "(bad)",  { XX } },
2385   },
2386   /* REG_VEX_73 */
2387   {
2388     { "(bad)",  { XX } },
2389     { "(bad)",  { XX } },
2390     { MOD_TABLE (MOD_VEX_73_REG_2) },
2391     { MOD_TABLE (MOD_VEX_73_REG_3) },
2392     { "(bad)",  { XX } },
2393     { "(bad)",  { XX } },
2394     { MOD_TABLE (MOD_VEX_73_REG_6) },
2395     { MOD_TABLE (MOD_VEX_73_REG_7) },
2396   },
2397   /* REG_VEX_AE */
2398   {
2399     { "(bad)",  { XX } },
2400     { "(bad)",  { XX } },
2401     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2402     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2403     { "(bad)",  { XX } },
2404     { "(bad)",  { XX } },
2405     { "(bad)",  { XX } },
2406     { "(bad)",  { XX } },
2407   },
2408 };
2409
2410 static const struct dis386 prefix_table[][4] = {
2411   /* PREFIX_90 */
2412   {
2413     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2414     { "pause", { XX } },
2415     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2416     { "(bad)", { XX } },
2417   },
2418
2419   /* PREFIX_0F10 */
2420   {
2421     { "movups", { XM, EXx } },
2422     { "movss",  { XM, EXd } },
2423     { "movupd", { XM, EXx } },
2424     { "movsd",  { XM, EXq } },
2425   },
2426
2427   /* PREFIX_0F11 */
2428   {
2429     { "movups", { EXxS, XM } },
2430     { "movss",  { EXd, XM } },
2431     { "movupd", { EXxS, XM } },
2432     { "movsd",  { EXq, XM } },
2433   },
2434
2435   /* PREFIX_0F12 */
2436   {
2437     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2438     { "movsldup", { XM, EXx } },
2439     { "movlpd", { XM, EXq } },
2440     { "movddup", { XM, EXq } },
2441   },
2442
2443   /* PREFIX_0F16 */
2444   {
2445     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2446     { "movshdup", { XM, EXx } },
2447     { "movhpd", { XM, EXq } },
2448     { "(bad)",  { XX } },
2449   },
2450
2451   /* PREFIX_0F2A */
2452   {
2453     { "cvtpi2ps", { XM, EMCq } },
2454     { "cvtsi2ss%LQ", { XM, Ev } },
2455     { "cvtpi2pd", { XM, EMCq } },
2456     { "cvtsi2sd%LQ", { XM, Ev } },
2457   },
2458
2459   /* PREFIX_0F2B */
2460   {
2461     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2462     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2463     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2464     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2465   },
2466
2467   /* PREFIX_0F2C */
2468   {
2469     { "cvttps2pi", { MXC, EXq } },
2470     { "cvttss2siY", { Gv, EXd } },
2471     { "cvttpd2pi", { MXC, EXx } },
2472     { "cvttsd2siY", { Gv, EXq } },
2473   },
2474
2475   /* PREFIX_0F2D */
2476   {
2477     { "cvtps2pi", { MXC, EXq } },
2478     { "cvtss2siY", { Gv, EXd } },
2479     { "cvtpd2pi", { MXC, EXx } },
2480     { "cvtsd2siY", { Gv, EXq } },
2481   },
2482
2483   /* PREFIX_0F2E */
2484   {
2485     { "ucomiss",{ XM, EXd } },
2486     { "(bad)",  { XX } },
2487     { "ucomisd",{ XM, EXq } },
2488     { "(bad)",  { XX } },
2489   },
2490
2491   /* PREFIX_0F2F */
2492   {
2493     { "comiss", { XM, EXd } },
2494     { "(bad)",  { XX } },
2495     { "comisd", { XM, EXq } },
2496     { "(bad)",  { XX } },
2497   },
2498
2499   /* PREFIX_0F51 */
2500   {
2501     { "sqrtps", { XM, EXx } },
2502     { "sqrtss", { XM, EXd } },
2503     { "sqrtpd", { XM, EXx } },
2504     { "sqrtsd", { XM, EXq } },
2505   },
2506
2507   /* PREFIX_0F52 */
2508   {
2509     { "rsqrtps",{ XM, EXx } },
2510     { "rsqrtss",{ XM, EXd } },
2511     { "(bad)",  { XX } },
2512     { "(bad)",  { XX } },
2513   },
2514
2515   /* PREFIX_0F53 */
2516   {
2517     { "rcpps",  { XM, EXx } },
2518     { "rcpss",  { XM, EXd } },
2519     { "(bad)",  { XX } },
2520     { "(bad)",  { XX } },
2521   },
2522
2523   /* PREFIX_0F58 */
2524   {
2525     { "addps", { XM, EXx } },
2526     { "addss", { XM, EXd } },
2527     { "addpd", { XM, EXx } },
2528     { "addsd", { XM, EXq } },
2529   },
2530
2531   /* PREFIX_0F59 */
2532   {
2533     { "mulps",  { XM, EXx } },
2534     { "mulss",  { XM, EXd } },
2535     { "mulpd",  { XM, EXx } },
2536     { "mulsd",  { XM, EXq } },
2537   },
2538
2539   /* PREFIX_0F5A */
2540   {
2541     { "cvtps2pd", { XM, EXq } },
2542     { "cvtss2sd", { XM, EXd } },
2543     { "cvtpd2ps", { XM, EXx } },
2544     { "cvtsd2ss", { XM, EXq } },
2545   },
2546
2547   /* PREFIX_0F5B */
2548   {
2549     { "cvtdq2ps", { XM, EXx } },
2550     { "cvttps2dq", { XM, EXx } },
2551     { "cvtps2dq", { XM, EXx } },
2552     { "(bad)",  { XX } },
2553   },
2554
2555   /* PREFIX_0F5C */
2556   {
2557     { "subps",  { XM, EXx } },
2558     { "subss",  { XM, EXd } },
2559     { "subpd",  { XM, EXx } },
2560     { "subsd",  { XM, EXq } },
2561   },
2562
2563   /* PREFIX_0F5D */
2564   {
2565     { "minps",  { XM, EXx } },
2566     { "minss",  { XM, EXd } },
2567     { "minpd",  { XM, EXx } },
2568     { "minsd",  { XM, EXq } },
2569   },
2570
2571   /* PREFIX_0F5E */
2572   {
2573     { "divps",  { XM, EXx } },
2574     { "divss",  { XM, EXd } },
2575     { "divpd",  { XM, EXx } },
2576     { "divsd",  { XM, EXq } },
2577   },
2578
2579   /* PREFIX_0F5F */
2580   {
2581     { "maxps",  { XM, EXx } },
2582     { "maxss",  { XM, EXd } },
2583     { "maxpd",  { XM, EXx } },
2584     { "maxsd",  { XM, EXq } },
2585   },
2586
2587   /* PREFIX_0F60 */
2588   {
2589     { "punpcklbw",{ MX, EMd } },
2590     { "(bad)",  { XX } },
2591     { "punpcklbw",{ MX, EMx } },
2592     { "(bad)",  { XX } },
2593   },
2594
2595   /* PREFIX_0F61 */
2596   {
2597     { "punpcklwd",{ MX, EMd } },
2598     { "(bad)",  { XX } },
2599     { "punpcklwd",{ MX, EMx } },
2600     { "(bad)",  { XX } },
2601   },
2602
2603   /* PREFIX_0F62 */
2604   {
2605     { "punpckldq",{ MX, EMd } },
2606     { "(bad)",  { XX } },
2607     { "punpckldq",{ MX, EMx } },
2608     { "(bad)",  { XX } },
2609   },
2610
2611   /* PREFIX_0F6C */
2612   {
2613     { "(bad)",  { XX } },
2614     { "(bad)",  { XX } },
2615     { "punpcklqdq", { XM, EXx } },
2616     { "(bad)",  { XX } },
2617   },
2618
2619   /* PREFIX_0F6D */
2620   {
2621     { "(bad)",  { XX } },
2622     { "(bad)",  { XX } },
2623     { "punpckhqdq", { XM, EXx } },
2624     { "(bad)",  { XX } },
2625   },
2626
2627   /* PREFIX_0F6F */
2628   {
2629     { "movq",   { MX, EM } },
2630     { "movdqu", { XM, EXx } },
2631     { "movdqa", { XM, EXx } },
2632     { "(bad)",  { XX } },
2633   },
2634
2635   /* PREFIX_0F70 */
2636   {
2637     { "pshufw", { MX, EM, Ib } },
2638     { "pshufhw",{ XM, EXx, Ib } },
2639     { "pshufd", { XM, EXx, Ib } },
2640     { "pshuflw",{ XM, EXx, Ib } },
2641   },
2642
2643   /* PREFIX_0F73_REG_3 */
2644   {
2645     { "(bad)",  { XX } },
2646     { "(bad)",  { XX } },
2647     { "psrldq", { XS, Ib } },
2648     { "(bad)",  { XX } },
2649   },
2650
2651   /* PREFIX_0F73_REG_7 */
2652   {
2653     { "(bad)",  { XX } },
2654     { "(bad)",  { XX } },
2655     { "pslldq", { XS, Ib } },
2656     { "(bad)",  { XX } },
2657   },
2658
2659   /* PREFIX_0F78 */
2660   {
2661     {"vmread",  { Em, Gm } },
2662     {"(bad)",   { XX } },
2663     {"extrq",   { XS, Ib, Ib } },
2664     {"insertq", { XM, XS, Ib, Ib } },
2665   },
2666
2667   /* PREFIX_0F79 */
2668   {
2669     {"vmwrite", { Gm, Em } },
2670     {"(bad)",   { XX } },
2671     {"extrq",   { XM, XS } },
2672     {"insertq", { XM, XS } },
2673   },
2674
2675   /* PREFIX_0F7C */
2676   {
2677     { "(bad)",  { XX } },
2678     { "(bad)",  { XX } },
2679     { "haddpd", { XM, EXx } },
2680     { "haddps", { XM, EXx } },
2681   },
2682
2683   /* PREFIX_0F7D */
2684   {
2685     { "(bad)",  { XX } },
2686     { "(bad)",  { XX } },
2687     { "hsubpd", { XM, EXx } },
2688     { "hsubps", { XM, EXx } },
2689   },
2690
2691   /* PREFIX_0F7E */
2692   {
2693     { "movK",   { Edq, MX } },
2694     { "movq",   { XM, EXq } },
2695     { "movK",   { Edq, XM } },
2696     { "(bad)",  { XX } },
2697   },
2698
2699   /* PREFIX_0F7F */
2700   {
2701     { "movq",   { EMS, MX } },
2702     { "movdqu", { EXxS, XM } },
2703     { "movdqa", { EXxS, XM } },
2704     { "(bad)",  { XX } },
2705   },
2706
2707   /* PREFIX_0FB8 */
2708   {
2709     { "(bad)", { XX } },
2710     { "popcntS", { Gv, Ev } },
2711     { "(bad)", { XX } },
2712     { "(bad)", { XX } },
2713   },
2714
2715   /* PREFIX_0FBD */
2716   {
2717     { "bsrS",   { Gv, Ev } },
2718     { "lzcntS", { Gv, Ev } },
2719     { "bsrS",   { Gv, Ev } },
2720     { "(bad)",  { XX } },
2721   },
2722
2723   /* PREFIX_0FC2 */
2724   {
2725     { "cmpps",  { XM, EXx, CMP } },
2726     { "cmpss",  { XM, EXd, CMP } },
2727     { "cmppd",  { XM, EXx, CMP } },
2728     { "cmpsd",  { XM, EXq, CMP } },
2729   },
2730
2731   /* PREFIX_0FC3 */
2732   {
2733     { "movntiS", { Ma, Gv } },
2734     { "(bad)",  { XX } },
2735     { "(bad)",  { XX } },
2736     { "(bad)",  { XX } },
2737   },
2738
2739   /* PREFIX_0FC7_REG_6 */
2740   {
2741     { "vmptrld",{ Mq } },
2742     { "vmxon",  { Mq } },
2743     { "vmclear",{ Mq } },
2744     { "(bad)",  { XX } },
2745   },
2746
2747   /* PREFIX_0FD0 */
2748   {
2749     { "(bad)",  { XX } },
2750     { "(bad)",  { XX } },
2751     { "addsubpd", { XM, EXx } },
2752     { "addsubps", { XM, EXx } },
2753   },
2754
2755   /* PREFIX_0FD6 */
2756   {
2757     { "(bad)",  { XX } },
2758     { "movq2dq",{ XM, MS } },
2759     { "movq",   { EXqS, XM } },
2760     { "movdq2q",{ MX, XS } },
2761   },
2762
2763   /* PREFIX_0FE6 */
2764   {
2765     { "(bad)",  { XX } },
2766     { "cvtdq2pd", { XM, EXq } },
2767     { "cvttpd2dq", { XM, EXx } },
2768     { "cvtpd2dq", { XM, EXx } },
2769   },
2770
2771   /* PREFIX_0FE7 */
2772   {
2773     { "movntq", { Mq, MX } },
2774     { "(bad)",  { XX } },
2775     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2776     { "(bad)",  { XX } },
2777   },
2778
2779   /* PREFIX_0FF0 */
2780   {
2781     { "(bad)",  { XX } },
2782     { "(bad)",  { XX } },
2783     { "(bad)",  { XX } },
2784     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2785   },
2786
2787   /* PREFIX_0FF7 */
2788   {
2789     { "maskmovq", { MX, MS } },
2790     { "(bad)",  { XX } },
2791     { "maskmovdqu", { XM, XS } },
2792     { "(bad)",  { XX } },
2793   },
2794
2795   /* PREFIX_0F3810 */
2796   {
2797     { "(bad)",  { XX } },
2798     { "(bad)",  { XX } },
2799     { "pblendvb", { XM, EXx, XMM0 } },
2800     { "(bad)",  { XX } },
2801   },
2802
2803   /* PREFIX_0F3814 */
2804   {
2805     { "(bad)",  { XX } },
2806     { "(bad)",  { XX } },
2807     { "blendvps", { XM, EXx, XMM0 } },
2808     { "(bad)",  { XX } },
2809   },
2810
2811   /* PREFIX_0F3815 */
2812   {
2813     { "(bad)",  { XX } },
2814     { "(bad)",  { XX } },
2815     { "blendvpd", { XM, EXx, XMM0 } },
2816     { "(bad)",  { XX } },
2817   },
2818
2819   /* PREFIX_0F3817 */
2820   {
2821     { "(bad)",  { XX } },
2822     { "(bad)",  { XX } },
2823     { "ptest",  { XM, EXx } },
2824     { "(bad)",  { XX } },
2825   },
2826
2827   /* PREFIX_0F3820 */
2828   {
2829     { "(bad)",  { XX } },
2830     { "(bad)",  { XX } },
2831     { "pmovsxbw", { XM, EXq } },
2832     { "(bad)",  { XX } },
2833   },
2834
2835   /* PREFIX_0F3821 */
2836   {
2837     { "(bad)",  { XX } },
2838     { "(bad)",  { XX } },
2839     { "pmovsxbd", { XM, EXd } },
2840     { "(bad)",  { XX } },
2841   },
2842
2843   /* PREFIX_0F3822 */
2844   {
2845     { "(bad)",  { XX } },
2846     { "(bad)",  { XX } },
2847     { "pmovsxbq", { XM, EXw } },
2848     { "(bad)",  { XX } },
2849   },
2850
2851   /* PREFIX_0F3823 */
2852   {
2853     { "(bad)",  { XX } },
2854     { "(bad)",  { XX } },
2855     { "pmovsxwd", { XM, EXq } },
2856     { "(bad)",  { XX } },
2857   },
2858
2859   /* PREFIX_0F3824 */
2860   {
2861     { "(bad)",  { XX } },
2862     { "(bad)",  { XX } },
2863     { "pmovsxwq", { XM, EXd } },
2864     { "(bad)",  { XX } },
2865   },
2866
2867   /* PREFIX_0F3825 */
2868   {
2869     { "(bad)",  { XX } },
2870     { "(bad)",  { XX } },
2871     { "pmovsxdq", { XM, EXq } },
2872     { "(bad)",  { XX } },
2873   },
2874
2875   /* PREFIX_0F3828 */
2876   {
2877     { "(bad)",  { XX } },
2878     { "(bad)",  { XX } },
2879     { "pmuldq", { XM, EXx } },
2880     { "(bad)",  { XX } },
2881   },
2882
2883   /* PREFIX_0F3829 */
2884   {
2885     { "(bad)",  { XX } },
2886     { "(bad)",  { XX } },
2887     { "pcmpeqq", { XM, EXx } },
2888     { "(bad)",  { XX } },
2889   },
2890
2891   /* PREFIX_0F382A */
2892   {
2893     { "(bad)",  { XX } },
2894     { "(bad)",  { XX } },
2895     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2896     { "(bad)",  { XX } },
2897   },
2898
2899   /* PREFIX_0F382B */
2900   {
2901     { "(bad)",  { XX } },
2902     { "(bad)",  { XX } },
2903     { "packusdw", { XM, EXx } },
2904     { "(bad)",  { XX } },
2905   },
2906
2907   /* PREFIX_0F3830 */
2908   {
2909     { "(bad)",  { XX } },
2910     { "(bad)",  { XX } },
2911     { "pmovzxbw", { XM, EXq } },
2912     { "(bad)",  { XX } },
2913   },
2914
2915   /* PREFIX_0F3831 */
2916   {
2917     { "(bad)",  { XX } },
2918     { "(bad)",  { XX } },
2919     { "pmovzxbd", { XM, EXd } },
2920     { "(bad)",  { XX } },
2921   },
2922
2923   /* PREFIX_0F3832 */
2924   {
2925     { "(bad)",  { XX } },
2926     { "(bad)",  { XX } },
2927     { "pmovzxbq", { XM, EXw } },
2928     { "(bad)",  { XX } },
2929   },
2930
2931   /* PREFIX_0F3833 */
2932   {
2933     { "(bad)",  { XX } },
2934     { "(bad)",  { XX } },
2935     { "pmovzxwd", { XM, EXq } },
2936     { "(bad)",  { XX } },
2937   },
2938
2939   /* PREFIX_0F3834 */
2940   {
2941     { "(bad)",  { XX } },
2942     { "(bad)",  { XX } },
2943     { "pmovzxwq", { XM, EXd } },
2944     { "(bad)",  { XX } },
2945   },
2946
2947   /* PREFIX_0F3835 */
2948   {
2949     { "(bad)",  { XX } },
2950     { "(bad)",  { XX } },
2951     { "pmovzxdq", { XM, EXq } },
2952     { "(bad)",  { XX } },
2953   },
2954
2955   /* PREFIX_0F3837 */
2956   {
2957     { "(bad)",  { XX } },
2958     { "(bad)",  { XX } },
2959     { "pcmpgtq", { XM, EXx } },
2960     { "(bad)",  { XX } },
2961   },
2962
2963   /* PREFIX_0F3838 */
2964   {
2965     { "(bad)",  { XX } },
2966     { "(bad)",  { XX } },
2967     { "pminsb", { XM, EXx } },
2968     { "(bad)",  { XX } },
2969   },
2970
2971   /* PREFIX_0F3839 */
2972   {
2973     { "(bad)",  { XX } },
2974     { "(bad)",  { XX } },
2975     { "pminsd", { XM, EXx } },
2976     { "(bad)",  { XX } },
2977   },
2978
2979   /* PREFIX_0F383A */
2980   {
2981     { "(bad)",  { XX } },
2982     { "(bad)",  { XX } },
2983     { "pminuw", { XM, EXx } },
2984     { "(bad)",  { XX } },
2985   },
2986
2987   /* PREFIX_0F383B */
2988   {
2989     { "(bad)",  { XX } },
2990     { "(bad)",  { XX } },
2991     { "pminud", { XM, EXx } },
2992     { "(bad)",  { XX } },
2993   },
2994
2995   /* PREFIX_0F383C */
2996   {
2997     { "(bad)",  { XX } },
2998     { "(bad)",  { XX } },
2999     { "pmaxsb", { XM, EXx } },
3000     { "(bad)",  { XX } },
3001   },
3002
3003   /* PREFIX_0F383D */
3004   {
3005     { "(bad)",  { XX } },
3006     { "(bad)",  { XX } },
3007     { "pmaxsd", { XM, EXx } },
3008     { "(bad)",  { XX } },
3009   },
3010
3011   /* PREFIX_0F383E */
3012   {
3013     { "(bad)",  { XX } },
3014     { "(bad)",  { XX } },
3015     { "pmaxuw", { XM, EXx } },
3016     { "(bad)",  { XX } },
3017   },
3018
3019   /* PREFIX_0F383F */
3020   {
3021     { "(bad)",  { XX } },
3022     { "(bad)",  { XX } },
3023     { "pmaxud", { XM, EXx } },
3024     { "(bad)",  { XX } },
3025   },
3026
3027   /* PREFIX_0F3840 */
3028   {
3029     { "(bad)",  { XX } },
3030     { "(bad)",  { XX } },
3031     { "pmulld", { XM, EXx } },
3032     { "(bad)",  { XX } },
3033   },
3034
3035   /* PREFIX_0F3841 */
3036   {
3037     { "(bad)",  { XX } },
3038     { "(bad)",  { XX } },
3039     { "phminposuw", { XM, EXx } },
3040     { "(bad)",  { XX } },
3041   },
3042
3043   /* PREFIX_0F3880 */
3044   {
3045     { "(bad)",  { XX } },
3046     { "(bad)",  { XX } },
3047     { "invept", { Gm, Mo } },
3048     { "(bad)",  { XX } },
3049   },
3050
3051   /* PREFIX_0F3881 */
3052   {
3053     { "(bad)",  { XX } },
3054     { "(bad)",  { XX } },
3055     { "invvpid", { Gm, Mo } },
3056     { "(bad)",  { XX } },
3057   },
3058
3059   /* PREFIX_0F38DB */
3060   {
3061     { "(bad)",  { XX } },
3062     { "(bad)",  { XX } },
3063     { "aesimc", { XM, EXx } },
3064     { "(bad)",  { XX } },
3065   },
3066
3067   /* PREFIX_0F38DC */
3068   {
3069     { "(bad)",  { XX } },
3070     { "(bad)",  { XX } },
3071     { "aesenc", { XM, EXx } },
3072     { "(bad)",  { XX } },
3073   },
3074
3075   /* PREFIX_0F38DD */
3076   {
3077     { "(bad)",  { XX } },
3078     { "(bad)",  { XX } },
3079     { "aesenclast", { XM, EXx } },
3080     { "(bad)",  { XX } },
3081   },
3082
3083   /* PREFIX_0F38DE */
3084   {
3085     { "(bad)",  { XX } },
3086     { "(bad)",  { XX } },
3087     { "aesdec", { XM, EXx } },
3088     { "(bad)",  { XX } },
3089   },
3090
3091   /* PREFIX_0F38DF */
3092   {
3093     { "(bad)",  { XX } },
3094     { "(bad)",  { XX } },
3095     { "aesdeclast", { XM, EXx } },
3096     { "(bad)",  { XX } },
3097   },
3098
3099   /* PREFIX_0F38F0 */
3100   {
3101     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3102     { "(bad)",  { XX } },
3103     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3104     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3105   },
3106
3107   /* PREFIX_0F38F1 */
3108   {
3109     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3110     { "(bad)",  { XX } },
3111     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3112     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3113   },
3114
3115   /* PREFIX_0F3A08 */
3116   {
3117     { "(bad)",  { XX } },
3118     { "(bad)",  { XX } },
3119     { "roundps", { XM, EXx, Ib } },
3120     { "(bad)",  { XX } },
3121   },
3122
3123   /* PREFIX_0F3A09 */
3124   {
3125     { "(bad)",  { XX } },
3126     { "(bad)",  { XX } },
3127     { "roundpd", { XM, EXx, Ib } },
3128     { "(bad)",  { XX } },
3129   },
3130
3131   /* PREFIX_0F3A0A */
3132   {
3133     { "(bad)",  { XX } },
3134     { "(bad)",  { XX } },
3135     { "roundss", { XM, EXd, Ib } },
3136     { "(bad)",  { XX } },
3137   },
3138
3139   /* PREFIX_0F3A0B */
3140   {
3141     { "(bad)",  { XX } },
3142     { "(bad)",  { XX } },
3143     { "roundsd", { XM, EXq, Ib } },
3144     { "(bad)",  { XX } },
3145   },
3146
3147   /* PREFIX_0F3A0C */
3148   {
3149     { "(bad)",  { XX } },
3150     { "(bad)",  { XX } },
3151     { "blendps", { XM, EXx, Ib } },
3152     { "(bad)",  { XX } },
3153   },
3154
3155   /* PREFIX_0F3A0D */
3156   {
3157     { "(bad)",  { XX } },
3158     { "(bad)",  { XX } },
3159     { "blendpd", { XM, EXx, Ib } },
3160     { "(bad)",  { XX } },
3161   },
3162
3163   /* PREFIX_0F3A0E */
3164   {
3165     { "(bad)",  { XX } },
3166     { "(bad)",  { XX } },
3167     { "pblendw", { XM, EXx, Ib } },
3168     { "(bad)",  { XX } },
3169   },
3170
3171   /* PREFIX_0F3A14 */
3172   {
3173     { "(bad)",  { XX } },
3174     { "(bad)",  { XX } },
3175     { "pextrb", { Edqb, XM, Ib } },
3176     { "(bad)",  { XX } },
3177   },
3178
3179   /* PREFIX_0F3A15 */
3180   {
3181     { "(bad)",  { XX } },
3182     { "(bad)",  { XX } },
3183     { "pextrw", { Edqw, XM, Ib } },
3184     { "(bad)",  { XX } },
3185   },
3186
3187   /* PREFIX_0F3A16 */
3188   {
3189     { "(bad)",  { XX } },
3190     { "(bad)",  { XX } },
3191     { "pextrK", { Edq, XM, Ib } },
3192     { "(bad)",  { XX } },
3193   },
3194
3195   /* PREFIX_0F3A17 */
3196   {
3197     { "(bad)",  { XX } },
3198     { "(bad)",  { XX } },
3199     { "extractps", { Edqd, XM, Ib } },
3200     { "(bad)",  { XX } },
3201   },
3202
3203   /* PREFIX_0F3A20 */
3204   {
3205     { "(bad)",  { XX } },
3206     { "(bad)",  { XX } },
3207     { "pinsrb", { XM, Edqb, Ib } },
3208     { "(bad)",  { XX } },
3209   },
3210
3211   /* PREFIX_0F3A21 */
3212   {
3213     { "(bad)",  { XX } },
3214     { "(bad)",  { XX } },
3215     { "insertps", { XM, EXd, Ib } },
3216     { "(bad)",  { XX } },
3217   },
3218
3219   /* PREFIX_0F3A22 */
3220   {
3221     { "(bad)",  { XX } },
3222     { "(bad)",  { XX } },
3223     { "pinsrK", { XM, Edq, Ib } },
3224     { "(bad)",  { XX } },
3225   },
3226
3227   /* PREFIX_0F3A40 */
3228   {
3229     { "(bad)",  { XX } },
3230     { "(bad)",  { XX } },
3231     { "dpps",   { XM, EXx, Ib } },
3232     { "(bad)",  { XX } },
3233   },
3234
3235   /* PREFIX_0F3A41 */
3236   {
3237     { "(bad)",  { XX } },
3238     { "(bad)",  { XX } },
3239     { "dppd",   { XM, EXx, Ib } },
3240     { "(bad)",  { XX } },
3241   },
3242
3243   /* PREFIX_0F3A42 */
3244   {
3245     { "(bad)",  { XX } },
3246     { "(bad)",  { XX } },
3247     { "mpsadbw", { XM, EXx, Ib } },
3248     { "(bad)",  { XX } },
3249   },
3250
3251   /* PREFIX_0F3A44 */
3252   {
3253     { "(bad)",  { XX } },
3254     { "(bad)",  { XX } },
3255     { "pclmulqdq", { XM, EXx, PCLMUL } },
3256     { "(bad)",  { XX } },
3257   },
3258
3259   /* PREFIX_0F3A60 */
3260   {
3261     { "(bad)",  { XX } },
3262     { "(bad)",  { XX } },
3263     { "pcmpestrm", { XM, EXx, Ib } },
3264     { "(bad)",  { XX } },
3265   },
3266
3267   /* PREFIX_0F3A61 */
3268   {
3269     { "(bad)",  { XX } },
3270     { "(bad)",  { XX } },
3271     { "pcmpestri", { XM, EXx, Ib } },
3272     { "(bad)",  { XX } },
3273   },
3274
3275   /* PREFIX_0F3A62 */
3276   {
3277     { "(bad)",  { XX } },
3278     { "(bad)",  { XX } },
3279     { "pcmpistrm", { XM, EXx, Ib } },
3280     { "(bad)",  { XX } },
3281   },
3282
3283   /* PREFIX_0F3A63 */
3284   {
3285     { "(bad)",  { XX } },
3286     { "(bad)",  { XX } },
3287     { "pcmpistri", { XM, EXx, Ib } },
3288     { "(bad)",  { XX } },
3289   },
3290
3291   /* PREFIX_0F3ADF */
3292   {
3293     { "(bad)",  { XX } },
3294     { "(bad)",  { XX } },
3295     { "aeskeygenassist", { XM, EXx, Ib } },
3296     { "(bad)",  { XX } },
3297   },
3298
3299   /* PREFIX_VEX_10 */
3300   {
3301     { "vmovups", { XM, EXx } },
3302     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3303     { "vmovupd", { XM, EXx } },
3304     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3305   },
3306
3307   /* PREFIX_VEX_11 */
3308   {
3309     { "vmovups", { EXxS, XM } },
3310     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3311     { "vmovupd", { EXxS, XM } },
3312     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3313   },
3314
3315   /* PREFIX_VEX_12 */
3316   {
3317     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3318     { "vmovsldup", { XM, EXx } },
3319     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3320     { "vmovddup", { XM, EXymmq } },
3321   },
3322
3323   /* PREFIX_VEX_16 */
3324   {
3325     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3326     { "vmovshdup", { XM, EXx } },
3327     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3328     { "(bad)",  { XX } },
3329   },
3330
3331   /* PREFIX_VEX_2A */
3332   {
3333     { "(bad)",  { XX } },
3334     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3335     { "(bad)",  { XX } },
3336     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3337   },
3338
3339   /* PREFIX_VEX_2C */
3340   {
3341     { "(bad)",  { XX } },
3342     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3343     { "(bad)",  { XX } },
3344     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3345   },
3346
3347   /* PREFIX_VEX_2D */
3348   {
3349     { "(bad)",  { XX } },
3350     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3351     { "(bad)",  { XX } },
3352     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3353   },
3354
3355   /* PREFIX_VEX_2E */
3356   {
3357     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3358     { "(bad)",  { XX } },
3359     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3360     { "(bad)",  { XX } },
3361   },
3362
3363   /* PREFIX_VEX_2F */
3364   {
3365     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3366     { "(bad)",  { XX } },
3367     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3368     { "(bad)",  { XX } },
3369   },
3370
3371   /* PREFIX_VEX_51 */
3372   {
3373     { "vsqrtps", { XM, EXx } },
3374     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3375     { "vsqrtpd", { XM, EXx } },
3376     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3377   },
3378
3379   /* PREFIX_VEX_52 */
3380   {
3381     { "vrsqrtps", { XM, EXx } },
3382     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3383     { "(bad)",  { XX } },
3384     { "(bad)",  { XX } },
3385   },
3386
3387   /* PREFIX_VEX_53 */
3388   {
3389     { "vrcpps", { XM, EXx } },
3390     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3391     { "(bad)",  { XX } },
3392     { "(bad)",  { XX } },
3393   },
3394
3395   /* PREFIX_VEX_58 */
3396   {
3397     { "vaddps", { XM, Vex, EXx } },
3398     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3399     { "vaddpd", { XM, Vex, EXx } },
3400     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3401   },
3402
3403   /* PREFIX_VEX_59 */
3404   {
3405     { "vmulps", { XM, Vex, EXx } },
3406     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3407     { "vmulpd", { XM, Vex, EXx } },
3408     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3409   },
3410
3411   /* PREFIX_VEX_5A */
3412   {
3413     { "vcvtps2pd", { XM, EXxmmq } },
3414     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3415     { "vcvtpd2ps%XY", { XMM, EXx } },
3416     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3417   },
3418
3419   /* PREFIX_VEX_5B */
3420   {
3421     { "vcvtdq2ps", { XM, EXx } },
3422     { "vcvttps2dq", { XM, EXx } },
3423     { "vcvtps2dq", { XM, EXx } },
3424     { "(bad)",  { XX } },
3425   },
3426
3427   /* PREFIX_VEX_5C */
3428   {
3429     { "vsubps", { XM, Vex, EXx } },
3430     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3431     { "vsubpd", { XM, Vex, EXx } },
3432     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3433   },
3434
3435   /* PREFIX_VEX_5D */
3436   {
3437     { "vminps", { XM, Vex, EXx } },
3438     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3439     { "vminpd", { XM, Vex, EXx } },
3440     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3441   },
3442
3443   /* PREFIX_VEX_5E */
3444   {
3445     { "vdivps", { XM, Vex, EXx } },
3446     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3447     { "vdivpd", { XM, Vex, EXx } },
3448     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3449   },
3450
3451   /* PREFIX_VEX_5F */
3452   {
3453     { "vmaxps", { XM, Vex, EXx } },
3454     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3455     { "vmaxpd", { XM, Vex, EXx } },
3456     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3457   },
3458
3459   /* PREFIX_VEX_60 */
3460   {
3461     { "(bad)",  { XX } },
3462     { "(bad)",  { XX } },
3463     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3464     { "(bad)",  { XX } },
3465   },
3466
3467   /* PREFIX_VEX_61 */
3468   {
3469     { "(bad)",  { XX } },
3470     { "(bad)",  { XX } },
3471     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3472     { "(bad)",  { XX } },
3473   },
3474
3475   /* PREFIX_VEX_62 */
3476   {
3477     { "(bad)",  { XX } },
3478     { "(bad)",  { XX } },
3479     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3480     { "(bad)",  { XX } },
3481   },
3482
3483   /* PREFIX_VEX_63 */
3484   {
3485     { "(bad)",  { XX } },
3486     { "(bad)",  { XX } },
3487     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3488     { "(bad)",  { XX } },
3489   },
3490
3491   /* PREFIX_VEX_64 */
3492   {
3493     { "(bad)",  { XX } },
3494     { "(bad)",  { XX } },
3495     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3496     { "(bad)",  { XX } },
3497   },
3498
3499   /* PREFIX_VEX_65 */
3500   {
3501     { "(bad)",  { XX } },
3502     { "(bad)",  { XX } },
3503     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3504     { "(bad)",  { XX } },
3505   },
3506
3507   /* PREFIX_VEX_66 */
3508   {
3509     { "(bad)",  { XX } },
3510     { "(bad)",  { XX } },
3511     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3512     { "(bad)",  { XX } },
3513   },
3514
3515   /* PREFIX_VEX_67 */
3516   {
3517     { "(bad)",  { XX } },
3518     { "(bad)",  { XX } },
3519     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3520     { "(bad)",  { XX } },
3521   },
3522
3523   /* PREFIX_VEX_68 */
3524   {
3525     { "(bad)",  { XX } },
3526     { "(bad)",  { XX } },
3527     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3528     { "(bad)",  { XX } },
3529   },
3530
3531   /* PREFIX_VEX_69 */
3532   {
3533     { "(bad)",  { XX } },
3534     { "(bad)",  { XX } },
3535     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3536     { "(bad)",  { XX } },
3537   },
3538
3539   /* PREFIX_VEX_6A */
3540   {
3541     { "(bad)",  { XX } },
3542     { "(bad)",  { XX } },
3543     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3544     { "(bad)",  { XX } },
3545   },
3546
3547   /* PREFIX_VEX_6B */
3548   {
3549     { "(bad)",  { XX } },
3550     { "(bad)",  { XX } },
3551     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3552     { "(bad)",  { XX } },
3553   },
3554
3555   /* PREFIX_VEX_6C */
3556   {
3557     { "(bad)",  { XX } },
3558     { "(bad)",  { XX } },
3559     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3560     { "(bad)",  { XX } },
3561   },
3562
3563   /* PREFIX_VEX_6D */
3564   {
3565     { "(bad)",  { XX } },
3566     { "(bad)",  { XX } },
3567     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3568     { "(bad)",  { XX } },
3569   },
3570
3571   /* PREFIX_VEX_6E */
3572   {
3573     { "(bad)",  { XX } },
3574     { "(bad)",  { XX } },
3575     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3576     { "(bad)",  { XX } },
3577   },
3578
3579   /* PREFIX_VEX_6F */
3580   {
3581     { "(bad)",  { XX } },
3582     { "vmovdqu", { XM, EXx } },
3583     { "vmovdqa", { XM, EXx } },
3584     { "(bad)",  { XX } },
3585   },
3586
3587   /* PREFIX_VEX_70 */
3588   {
3589     { "(bad)",  { XX } },
3590     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3591     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3592     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3593   },
3594
3595   /* PREFIX_VEX_71_REG_2 */
3596   {
3597     { "(bad)",  { XX } },
3598     { "(bad)",  { XX } },
3599     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3600     { "(bad)",  { XX } },
3601   },
3602
3603   /* PREFIX_VEX_71_REG_4 */
3604   {
3605     { "(bad)",  { XX } },
3606     { "(bad)",  { XX } },
3607     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3608     { "(bad)",  { XX } },
3609   },
3610
3611   /* PREFIX_VEX_71_REG_6 */
3612   {
3613     { "(bad)",  { XX } },
3614     { "(bad)",  { XX } },
3615     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3616     { "(bad)",  { XX } },
3617   },
3618
3619   /* PREFIX_VEX_72_REG_2 */
3620   {
3621     { "(bad)",  { XX } },
3622     { "(bad)",  { XX } },
3623     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3624     { "(bad)",  { XX } },
3625   },
3626
3627   /* PREFIX_VEX_72_REG_4 */
3628   {
3629     { "(bad)",  { XX } },
3630     { "(bad)",  { XX } },
3631     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3632     { "(bad)",  { XX } },
3633   },
3634
3635   /* PREFIX_VEX_72_REG_6 */
3636   {
3637     { "(bad)",  { XX } },
3638     { "(bad)",  { XX } },
3639     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3640     { "(bad)",  { XX } },
3641   },
3642
3643   /* PREFIX_VEX_73_REG_2 */
3644   {
3645     { "(bad)",  { XX } },
3646     { "(bad)",  { XX } },
3647     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3648     { "(bad)",  { XX } },
3649   },
3650
3651   /* PREFIX_VEX_73_REG_3 */
3652   {
3653     { "(bad)",  { XX } },
3654     { "(bad)",  { XX } },
3655     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3656     { "(bad)",  { XX } },
3657   },
3658
3659   /* PREFIX_VEX_73_REG_6 */
3660   {
3661     { "(bad)",  { XX } },
3662     { "(bad)",  { XX } },
3663     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3664     { "(bad)",  { XX } },
3665   },
3666
3667   /* PREFIX_VEX_73_REG_7 */
3668   {
3669     { "(bad)",  { XX } },
3670     { "(bad)",  { XX } },
3671     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3672     { "(bad)",  { XX } },
3673   },
3674
3675   /* PREFIX_VEX_74 */
3676   {
3677     { "(bad)",  { XX } },
3678     { "(bad)",  { XX } },
3679     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3680     { "(bad)",  { XX } },
3681   },
3682
3683   /* PREFIX_VEX_75 */
3684   {
3685     { "(bad)",  { XX } },
3686     { "(bad)",  { XX } },
3687     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3688     { "(bad)",  { XX } },
3689   },
3690
3691   /* PREFIX_VEX_76 */
3692   {
3693     { "(bad)",  { XX } },
3694     { "(bad)",  { XX } },
3695     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3696     { "(bad)",  { XX } },
3697   },
3698
3699   /* PREFIX_VEX_77 */
3700   {
3701     { "",       { VZERO } },
3702     { "(bad)",  { XX } },
3703     { "(bad)",  { XX } },
3704     { "(bad)",  { XX } },
3705   },
3706
3707   /* PREFIX_VEX_7C */
3708   {
3709     { "(bad)",  { XX } },
3710     { "(bad)",  { XX } },
3711     { "vhaddpd", { XM, Vex, EXx } },
3712     { "vhaddps", { XM, Vex, EXx } },
3713   },
3714
3715   /* PREFIX_VEX_7D */
3716   {
3717     { "(bad)",  { XX } },
3718     { "(bad)",  { XX } },
3719     { "vhsubpd", { XM, Vex, EXx } },
3720     { "vhsubps", { XM, Vex, EXx } },
3721   },
3722
3723   /* PREFIX_VEX_7E */
3724   {
3725     { "(bad)",  { XX } },
3726     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3727     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3728     { "(bad)",  { XX } },
3729   },
3730
3731   /* PREFIX_VEX_7F */
3732   {
3733     { "(bad)",  { XX } },
3734     { "vmovdqu", { EXxS, XM } },
3735     { "vmovdqa", { EXxS, XM } },
3736     { "(bad)",  { XX } },
3737   },
3738
3739   /* PREFIX_VEX_C2 */
3740   {
3741     { "vcmpps", { XM, Vex, EXx, VCMP } },
3742     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3743     { "vcmppd", { XM, Vex, EXx, VCMP } },
3744     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3745   },
3746
3747   /* PREFIX_VEX_C4 */
3748   {
3749     { "(bad)",  { XX } },
3750     { "(bad)",  { XX } },
3751     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3752     { "(bad)",  { XX } },
3753   },
3754
3755   /* PREFIX_VEX_C5 */
3756   {
3757     { "(bad)",  { XX } },
3758     { "(bad)",  { XX } },
3759     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3760     { "(bad)",  { XX } },
3761   },
3762
3763   /* PREFIX_VEX_D0 */
3764   {
3765     { "(bad)",  { XX } },
3766     { "(bad)",  { XX } },
3767     { "vaddsubpd", { XM, Vex, EXx } },
3768     { "vaddsubps", { XM, Vex, EXx } },
3769   },
3770
3771   /* PREFIX_VEX_D1 */
3772   {
3773     { "(bad)",  { XX } },
3774     { "(bad)",  { XX } },
3775     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3776     { "(bad)",  { XX } },
3777   },
3778
3779   /* PREFIX_VEX_D2 */
3780   {
3781     { "(bad)",  { XX } },
3782     { "(bad)",  { XX } },
3783     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3784     { "(bad)",  { XX } },
3785   },
3786
3787   /* PREFIX_VEX_D3 */
3788   {
3789     { "(bad)",  { XX } },
3790     { "(bad)",  { XX } },
3791     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3792     { "(bad)",  { XX } },
3793   },
3794
3795   /* PREFIX_VEX_D4 */
3796   {
3797     { "(bad)",  { XX } },
3798     { "(bad)",  { XX } },
3799     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3800     { "(bad)",  { XX } },
3801   },
3802
3803   /* PREFIX_VEX_D5 */
3804   {
3805     { "(bad)",  { XX } },
3806     { "(bad)",  { XX } },
3807     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3808     { "(bad)",  { XX } },
3809   },
3810
3811   /* PREFIX_VEX_D6 */
3812   {
3813     { "(bad)",  { XX } },
3814     { "(bad)",  { XX } },
3815     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3816     { "(bad)",  { XX } },
3817   },
3818
3819   /* PREFIX_VEX_D7 */
3820   {
3821     { "(bad)",  { XX } },
3822     { "(bad)",  { XX } },
3823     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3824     { "(bad)",  { XX } },
3825   },
3826
3827   /* PREFIX_VEX_D8 */
3828   {
3829     { "(bad)",  { XX } },
3830     { "(bad)",  { XX } },
3831     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3832     { "(bad)",  { XX } },
3833   },
3834
3835   /* PREFIX_VEX_D9 */
3836   {
3837     { "(bad)",  { XX } },
3838     { "(bad)",  { XX } },
3839     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3840     { "(bad)",  { XX } },
3841   },
3842
3843   /* PREFIX_VEX_DA */
3844   {
3845     { "(bad)",  { XX } },
3846     { "(bad)",  { XX } },
3847     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3848     { "(bad)",  { XX } },
3849   },
3850
3851   /* PREFIX_VEX_DB */
3852   {
3853     { "(bad)",  { XX } },
3854     { "(bad)",  { XX } },
3855     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3856     { "(bad)",  { XX } },
3857   },
3858
3859   /* PREFIX_VEX_DC */
3860   {
3861     { "(bad)",  { XX } },
3862     { "(bad)",  { XX } },
3863     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3864     { "(bad)",  { XX } },
3865   },
3866
3867   /* PREFIX_VEX_DD */
3868   {
3869     { "(bad)",  { XX } },
3870     { "(bad)",  { XX } },
3871     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3872     { "(bad)",  { XX } },
3873   },
3874
3875   /* PREFIX_VEX_DE */
3876   {
3877     { "(bad)",  { XX } },
3878     { "(bad)",  { XX } },
3879     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3880     { "(bad)",  { XX } },
3881   },
3882
3883   /* PREFIX_VEX_DF */
3884   {
3885     { "(bad)",  { XX } },
3886     { "(bad)",  { XX } },
3887     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3888     { "(bad)",  { XX } },
3889   },
3890
3891   /* PREFIX_VEX_E0 */
3892   {
3893     { "(bad)",  { XX } },
3894     { "(bad)",  { XX } },
3895     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3896     { "(bad)",  { XX } },
3897   },
3898
3899   /* PREFIX_VEX_E1 */
3900   {
3901     { "(bad)",  { XX } },
3902     { "(bad)",  { XX } },
3903     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3904     { "(bad)",  { XX } },
3905   },
3906
3907   /* PREFIX_VEX_E2 */
3908   {
3909     { "(bad)",  { XX } },
3910     { "(bad)",  { XX } },
3911     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3912     { "(bad)",  { XX } },
3913   },
3914
3915   /* PREFIX_VEX_E3 */
3916   {
3917     { "(bad)",  { XX } },
3918     { "(bad)",  { XX } },
3919     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3920     { "(bad)",  { XX } },
3921   },
3922
3923   /* PREFIX_VEX_E4 */
3924   {
3925     { "(bad)",  { XX } },
3926     { "(bad)",  { XX } },
3927     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3928     { "(bad)",  { XX } },
3929   },
3930
3931   /* PREFIX_VEX_E5 */
3932   {
3933     { "(bad)",  { XX } },
3934     { "(bad)",  { XX } },
3935     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3936     { "(bad)",  { XX } },
3937   },
3938
3939   /* PREFIX_VEX_E6 */
3940   {
3941     { "(bad)",  { XX } },
3942     { "vcvtdq2pd", { XM, EXxmmq } },
3943     { "vcvttpd2dq%XY", { XMM, EXx } },
3944     { "vcvtpd2dq%XY", { XMM, EXx } },
3945   },
3946
3947   /* PREFIX_VEX_E7 */
3948   {
3949     { "(bad)",  { XX } },
3950     { "(bad)",  { XX } },
3951     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3952     { "(bad)",  { XX } },
3953   },
3954
3955   /* PREFIX_VEX_E8 */
3956   {
3957     { "(bad)",  { XX } },
3958     { "(bad)",  { XX } },
3959     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3960     { "(bad)",  { XX } },
3961   },
3962
3963   /* PREFIX_VEX_E9 */
3964   {
3965     { "(bad)",  { XX } },
3966     { "(bad)",  { XX } },
3967     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3968     { "(bad)",  { XX } },
3969   },
3970
3971   /* PREFIX_VEX_EA */
3972   {
3973     { "(bad)",  { XX } },
3974     { "(bad)",  { XX } },
3975     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3976     { "(bad)",  { XX } },
3977   },
3978
3979   /* PREFIX_VEX_EB */
3980   {
3981     { "(bad)",  { XX } },
3982     { "(bad)",  { XX } },
3983     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3984     { "(bad)",  { XX } },
3985   },
3986
3987   /* PREFIX_VEX_EC */
3988   {
3989     { "(bad)",  { XX } },
3990     { "(bad)",  { XX } },
3991     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3992     { "(bad)",  { XX } },
3993   },
3994
3995   /* PREFIX_VEX_ED */
3996   {
3997     { "(bad)",  { XX } },
3998     { "(bad)",  { XX } },
3999     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4000     { "(bad)",  { XX } },
4001   },
4002
4003   /* PREFIX_VEX_EE */
4004   {
4005     { "(bad)",  { XX } },
4006     { "(bad)",  { XX } },
4007     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4008     { "(bad)",  { XX } },
4009   },
4010
4011   /* PREFIX_VEX_EF */
4012   {
4013     { "(bad)",  { XX } },
4014     { "(bad)",  { XX } },
4015     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4016     { "(bad)",  { XX } },
4017   },
4018
4019   /* PREFIX_VEX_F0 */
4020   {
4021     { "(bad)",  { XX } },
4022     { "(bad)",  { XX } },
4023     { "(bad)",  { XX } },
4024     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4025   },
4026
4027   /* PREFIX_VEX_F1 */
4028   {
4029     { "(bad)",  { XX } },
4030     { "(bad)",  { XX } },
4031     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4032     { "(bad)",  { XX } },
4033   },
4034
4035   /* PREFIX_VEX_F2 */
4036   {
4037     { "(bad)",  { XX } },
4038     { "(bad)",  { XX } },
4039     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4040     { "(bad)",  { XX } },
4041   },
4042
4043   /* PREFIX_VEX_F3 */
4044   {
4045     { "(bad)",  { XX } },
4046     { "(bad)",  { XX } },
4047     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4048     { "(bad)",  { XX } },
4049   },
4050
4051   /* PREFIX_VEX_F4 */
4052   {
4053     { "(bad)",  { XX } },
4054     { "(bad)",  { XX } },
4055     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4056     { "(bad)",  { XX } },
4057   },
4058
4059   /* PREFIX_VEX_F5 */
4060   {
4061     { "(bad)",  { XX } },
4062     { "(bad)",  { XX } },
4063     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4064     { "(bad)",  { XX } },
4065   },
4066
4067   /* PREFIX_VEX_F6 */
4068   {
4069     { "(bad)",  { XX } },
4070     { "(bad)",  { XX } },
4071     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4072     { "(bad)",  { XX } },
4073   },
4074
4075   /* PREFIX_VEX_F7 */
4076   {
4077     { "(bad)",  { XX } },
4078     { "(bad)",  { XX } },
4079     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4080     { "(bad)",  { XX } },
4081   },
4082
4083   /* PREFIX_VEX_F8 */
4084   {
4085     { "(bad)",  { XX } },
4086     { "(bad)",  { XX } },
4087     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4088     { "(bad)",  { XX } },
4089   },
4090
4091   /* PREFIX_VEX_F9 */
4092   {
4093     { "(bad)",  { XX } },
4094     { "(bad)",  { XX } },
4095     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4096     { "(bad)",  { XX } },
4097   },
4098
4099   /* PREFIX_VEX_FA */
4100   {
4101     { "(bad)",  { XX } },
4102     { "(bad)",  { XX } },
4103     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4104     { "(bad)",  { XX } },
4105   },
4106
4107   /* PREFIX_VEX_FB */
4108   {
4109     { "(bad)",  { XX } },
4110     { "(bad)",  { XX } },
4111     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4112     { "(bad)",  { XX } },
4113   },
4114
4115   /* PREFIX_VEX_FC */
4116   {
4117     { "(bad)",  { XX } },
4118     { "(bad)",  { XX } },
4119     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4120     { "(bad)",  { XX } },
4121   },
4122
4123   /* PREFIX_VEX_FD */
4124   {
4125     { "(bad)",  { XX } },
4126     { "(bad)",  { XX } },
4127     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4128     { "(bad)",  { XX } },
4129   },
4130
4131   /* PREFIX_VEX_FE */
4132   {
4133     { "(bad)",  { XX } },
4134     { "(bad)",  { XX } },
4135     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4136     { "(bad)",  { XX } },
4137   },
4138
4139   /* PREFIX_VEX_3800 */
4140   {
4141     { "(bad)",  { XX } },
4142     { "(bad)",  { XX } },
4143     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4144     { "(bad)",  { XX } },
4145   },
4146
4147   /* PREFIX_VEX_3801 */
4148   {
4149     { "(bad)",  { XX } },
4150     { "(bad)",  { XX } },
4151     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4152     { "(bad)",  { XX } },
4153   },
4154
4155   /* PREFIX_VEX_3802 */
4156   {
4157     { "(bad)",  { XX } },
4158     { "(bad)",  { XX } },
4159     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4160     { "(bad)",  { XX } },
4161   },
4162
4163   /* PREFIX_VEX_3803 */
4164   {
4165     { "(bad)",  { XX } },
4166     { "(bad)",  { XX } },
4167     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4168     { "(bad)",  { XX } },
4169   },
4170
4171   /* PREFIX_VEX_3804 */
4172   {
4173     { "(bad)",  { XX } },
4174     { "(bad)",  { XX } },
4175     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4176     { "(bad)",  { XX } },
4177   },
4178
4179   /* PREFIX_VEX_3805 */
4180   {
4181     { "(bad)",  { XX } },
4182     { "(bad)",  { XX } },
4183     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4184     { "(bad)",  { XX } },
4185   },
4186
4187   /* PREFIX_VEX_3806 */
4188   {
4189     { "(bad)",  { XX } },
4190     { "(bad)",  { XX } },
4191     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4192     { "(bad)",  { XX } },
4193   },
4194
4195   /* PREFIX_VEX_3807 */
4196   {
4197     { "(bad)",  { XX } },
4198     { "(bad)",  { XX } },
4199     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4200     { "(bad)",  { XX } },
4201   },
4202
4203   /* PREFIX_VEX_3808 */
4204   {
4205     { "(bad)",  { XX } },
4206     { "(bad)",  { XX } },
4207     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4208     { "(bad)",  { XX } },
4209   },
4210
4211   /* PREFIX_VEX_3809 */
4212   {
4213     { "(bad)",  { XX } },
4214     { "(bad)",  { XX } },
4215     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4216     { "(bad)",  { XX } },
4217   },
4218
4219   /* PREFIX_VEX_380A */
4220   {
4221     { "(bad)",  { XX } },
4222     { "(bad)",  { XX } },
4223     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4224     { "(bad)",  { XX } },
4225   },
4226
4227   /* PREFIX_VEX_380B */
4228   {
4229     { "(bad)",  { XX } },
4230     { "(bad)",  { XX } },
4231     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4232     { "(bad)",  { XX } },
4233   },
4234
4235   /* PREFIX_VEX_380C */
4236   {
4237     { "(bad)",  { XX } },
4238     { "(bad)",  { XX } },
4239     { "vpermilps", { XM, Vex, EXx } },
4240     { "(bad)",  { XX } },
4241   },
4242
4243   /* PREFIX_VEX_380D */
4244   {
4245     { "(bad)",  { XX } },
4246     { "(bad)",  { XX } },
4247     { "vpermilpd", { XM, Vex, EXx } },
4248     { "(bad)",  { XX } },
4249   },
4250
4251   /* PREFIX_VEX_380E */
4252   {
4253     { "(bad)",  { XX } },
4254     { "(bad)",  { XX } },
4255     { "vtestps", { XM, EXx } },
4256     { "(bad)",  { XX } },
4257   },
4258
4259   /* PREFIX_VEX_380F */
4260   {
4261     { "(bad)",  { XX } },
4262     { "(bad)",  { XX } },
4263     { "vtestpd", { XM, EXx } },
4264     { "(bad)",  { XX } },
4265   },
4266
4267   /* PREFIX_VEX_3817 */
4268   {
4269     { "(bad)",  { XX } },
4270     { "(bad)",  { XX } },
4271     { "vptest", { XM, EXx } },
4272     { "(bad)",  { XX } },
4273   },
4274
4275   /* PREFIX_VEX_3818 */
4276   {
4277     { "(bad)",  { XX } },
4278     { "(bad)",  { XX } },
4279     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4280     { "(bad)",  { XX } },
4281   },
4282
4283   /* PREFIX_VEX_3819 */
4284   {
4285     { "(bad)",  { XX } },
4286     { "(bad)",  { XX } },
4287     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4288     { "(bad)",  { XX } },
4289   },
4290
4291   /* PREFIX_VEX_381A */
4292   {
4293     { "(bad)",  { XX } },
4294     { "(bad)",  { XX } },
4295     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4296     { "(bad)",  { XX } },
4297   },
4298
4299   /* PREFIX_VEX_381C */
4300   {
4301     { "(bad)",  { XX } },
4302     { "(bad)",  { XX } },
4303     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4304     { "(bad)",  { XX } },
4305   },
4306
4307   /* PREFIX_VEX_381D */
4308   {
4309     { "(bad)",  { XX } },
4310     { "(bad)",  { XX } },
4311     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4312     { "(bad)",  { XX } },
4313   },
4314
4315   /* PREFIX_VEX_381E */
4316   {
4317     { "(bad)",  { XX } },
4318     { "(bad)",  { XX } },
4319     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4320     { "(bad)",  { XX } },
4321   },
4322
4323   /* PREFIX_VEX_3820 */
4324   {
4325     { "(bad)",  { XX } },
4326     { "(bad)",  { XX } },
4327     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4328     { "(bad)",  { XX } },
4329   },
4330
4331   /* PREFIX_VEX_3821 */
4332   {
4333     { "(bad)",  { XX } },
4334     { "(bad)",  { XX } },
4335     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4336     { "(bad)",  { XX } },
4337   },
4338
4339   /* PREFIX_VEX_3822 */
4340   {
4341     { "(bad)",  { XX } },
4342     { "(bad)",  { XX } },
4343     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4344     { "(bad)",  { XX } },
4345   },
4346
4347   /* PREFIX_VEX_3823 */
4348   {
4349     { "(bad)",  { XX } },
4350     { "(bad)",  { XX } },
4351     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4352     { "(bad)",  { XX } },
4353   },
4354
4355   /* PREFIX_VEX_3824 */
4356   {
4357     { "(bad)",  { XX } },
4358     { "(bad)",  { XX } },
4359     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4360     { "(bad)",  { XX } },
4361   },
4362
4363   /* PREFIX_VEX_3825 */
4364   {
4365     { "(bad)",  { XX } },
4366     { "(bad)",  { XX } },
4367     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4368     { "(bad)",  { XX } },
4369   },
4370
4371   /* PREFIX_VEX_3828 */
4372   {
4373     { "(bad)",  { XX } },
4374     { "(bad)",  { XX } },
4375     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4376     { "(bad)",  { XX } },
4377   },
4378
4379   /* PREFIX_VEX_3829 */
4380   {
4381     { "(bad)",  { XX } },
4382     { "(bad)",  { XX } },
4383     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4384     { "(bad)",  { XX } },
4385   },
4386
4387   /* PREFIX_VEX_382A */
4388   {
4389     { "(bad)",  { XX } },
4390     { "(bad)",  { XX } },
4391     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4392     { "(bad)",  { XX } },
4393   },
4394
4395   /* PREFIX_VEX_382B */
4396   {
4397     { "(bad)",  { XX } },
4398     { "(bad)",  { XX } },
4399     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4400     { "(bad)",  { XX } },
4401   },
4402
4403   /* PREFIX_VEX_382C */
4404   {
4405     { "(bad)",  { XX } },
4406     { "(bad)",  { XX } },
4407      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4408     { "(bad)",  { XX } },
4409   },
4410
4411   /* PREFIX_VEX_382D */
4412   {
4413     { "(bad)",  { XX } },
4414     { "(bad)",  { XX } },
4415      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4416     { "(bad)",  { XX } },
4417   },
4418
4419   /* PREFIX_VEX_382E */
4420   {
4421     { "(bad)",  { XX } },
4422     { "(bad)",  { XX } },
4423      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4424     { "(bad)",  { XX } },
4425   },
4426
4427   /* PREFIX_VEX_382F */
4428   {
4429     { "(bad)",  { XX } },
4430     { "(bad)",  { XX } },
4431      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4432     { "(bad)",  { XX } },
4433   },
4434
4435   /* PREFIX_VEX_3830 */
4436   {
4437     { "(bad)",  { XX } },
4438     { "(bad)",  { XX } },
4439     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4440     { "(bad)",  { XX } },
4441   },
4442
4443   /* PREFIX_VEX_3831 */
4444   {
4445     { "(bad)",  { XX } },
4446     { "(bad)",  { XX } },
4447     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4448     { "(bad)",  { XX } },
4449   },
4450
4451   /* PREFIX_VEX_3832 */
4452   {
4453     { "(bad)",  { XX } },
4454     { "(bad)",  { XX } },
4455     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4456     { "(bad)",  { XX } },
4457   },
4458
4459   /* PREFIX_VEX_3833 */
4460   {
4461     { "(bad)",  { XX } },
4462     { "(bad)",  { XX } },
4463     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4464     { "(bad)",  { XX } },
4465   },
4466
4467   /* PREFIX_VEX_3834 */
4468   {
4469     { "(bad)",  { XX } },
4470     { "(bad)",  { XX } },
4471     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4472     { "(bad)",  { XX } },
4473   },
4474
4475   /* PREFIX_VEX_3835 */
4476   {
4477     { "(bad)",  { XX } },
4478     { "(bad)",  { XX } },
4479     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4480     { "(bad)",  { XX } },
4481   },
4482
4483   /* PREFIX_VEX_3837 */
4484   {
4485     { "(bad)",  { XX } },
4486     { "(bad)",  { XX } },
4487     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4488     { "(bad)",  { XX } },
4489   },
4490
4491   /* PREFIX_VEX_3838 */
4492   {
4493     { "(bad)",  { XX } },
4494     { "(bad)",  { XX } },
4495     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4496     { "(bad)",  { XX } },
4497   },
4498
4499   /* PREFIX_VEX_3839 */
4500   {
4501     { "(bad)",  { XX } },
4502     { "(bad)",  { XX } },
4503     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4504     { "(bad)",  { XX } },
4505   },
4506
4507   /* PREFIX_VEX_383A */
4508   {
4509     { "(bad)",  { XX } },
4510     { "(bad)",  { XX } },
4511     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4512     { "(bad)",  { XX } },
4513   },
4514
4515   /* PREFIX_VEX_383B */
4516   {
4517     { "(bad)",  { XX } },
4518     { "(bad)",  { XX } },
4519     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4520     { "(bad)",  { XX } },
4521   },
4522
4523   /* PREFIX_VEX_383C */
4524   {
4525     { "(bad)",  { XX } },
4526     { "(bad)",  { XX } },
4527     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4528     { "(bad)",  { XX } },
4529   },
4530
4531   /* PREFIX_VEX_383D */
4532   {
4533     { "(bad)",  { XX } },
4534     { "(bad)",  { XX } },
4535     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4536     { "(bad)",  { XX } },
4537   },
4538
4539   /* PREFIX_VEX_383E */
4540   {
4541     { "(bad)",  { XX } },
4542     { "(bad)",  { XX } },
4543     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4544     { "(bad)",  { XX } },
4545   },
4546
4547   /* PREFIX_VEX_383F */
4548   {
4549     { "(bad)",  { XX } },
4550     { "(bad)",  { XX } },
4551     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4552     { "(bad)",  { XX } },
4553   },
4554
4555   /* PREFIX_VEX_3840 */
4556   {
4557     { "(bad)",  { XX } },
4558     { "(bad)",  { XX } },
4559     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4560     { "(bad)",  { XX } },
4561   },
4562
4563   /* PREFIX_VEX_3841 */
4564   {
4565     { "(bad)",  { XX } },
4566     { "(bad)",  { XX } },
4567     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4568     { "(bad)",  { XX } },
4569   },
4570
4571   /* PREFIX_VEX_38DB */
4572   {
4573     { "(bad)",  { XX } },
4574     { "(bad)",  { XX } },
4575     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4576     { "(bad)",  { XX } },
4577   },
4578
4579   /* PREFIX_VEX_38DC */
4580   {
4581     { "(bad)",  { XX } },
4582     { "(bad)",  { XX } },
4583     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4584     { "(bad)",  { XX } },
4585   },
4586
4587   /* PREFIX_VEX_38DD */
4588   {
4589     { "(bad)",  { XX } },
4590     { "(bad)",  { XX } },
4591     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4592     { "(bad)",  { XX } },
4593   },
4594
4595   /* PREFIX_VEX_38DE */
4596   {
4597     { "(bad)",  { XX } },
4598     { "(bad)",  { XX } },
4599     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4600     { "(bad)",  { XX } },
4601   },
4602
4603   /* PREFIX_VEX_38DF */
4604   {
4605     { "(bad)",  { XX } },
4606     { "(bad)",  { XX } },
4607     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4608     { "(bad)",  { XX } },
4609   },
4610
4611   /* PREFIX_VEX_3A04 */
4612   {
4613     { "(bad)",  { XX } },
4614     { "(bad)",  { XX } },
4615     { "vpermilps", { XM, EXx, Ib } },
4616     { "(bad)",  { XX } },
4617   },
4618
4619   /* PREFIX_VEX_3A05 */
4620   {
4621     { "(bad)",  { XX } },
4622     { "(bad)",  { XX } },
4623     { "vpermilpd", { XM, EXx, Ib } },
4624     { "(bad)",  { XX } },
4625   },
4626
4627   /* PREFIX_VEX_3A06 */
4628   {
4629     { "(bad)",  { XX } },
4630     { "(bad)",  { XX } },
4631     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4632     { "(bad)",  { XX } },
4633   },
4634
4635   /* PREFIX_VEX_3A08 */
4636   {
4637     { "(bad)",  { XX } },
4638     { "(bad)",  { XX } },
4639     { "vroundps", { XM, EXx, Ib } },
4640     { "(bad)",  { XX } },
4641   },
4642
4643   /* PREFIX_VEX_3A09 */
4644   {
4645     { "(bad)",  { XX } },
4646     { "(bad)",  { XX } },
4647     { "vroundpd", { XM, EXx, Ib } },
4648     { "(bad)",  { XX } },
4649   },
4650
4651   /* PREFIX_VEX_3A0A */
4652   {
4653     { "(bad)",  { XX } },
4654     { "(bad)",  { XX } },
4655     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4656     { "(bad)",  { XX } },
4657   },
4658
4659   /* PREFIX_VEX_3A0B */
4660   {
4661     { "(bad)",  { XX } },
4662     { "(bad)",  { XX } },
4663     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4664     { "(bad)",  { XX } },
4665   },
4666
4667   /* PREFIX_VEX_3A0C */
4668   {
4669     { "(bad)",  { XX } },
4670     { "(bad)",  { XX } },
4671     { "vblendps", { XM, Vex, EXx, Ib } },
4672     { "(bad)",  { XX } },
4673   },
4674
4675   /* PREFIX_VEX_3A0D */
4676   {
4677     { "(bad)",  { XX } },
4678     { "(bad)",  { XX } },
4679     { "vblendpd", { XM, Vex, EXx, Ib } },
4680     { "(bad)",  { XX } },
4681   },
4682
4683   /* PREFIX_VEX_3A0E */
4684   {
4685     { "(bad)",  { XX } },
4686     { "(bad)",  { XX } },
4687     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4688     { "(bad)",  { XX } },
4689   },
4690
4691   /* PREFIX_VEX_3A0F */
4692   {
4693     { "(bad)",  { XX } },
4694     { "(bad)",  { XX } },
4695     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4696     { "(bad)",  { XX } },
4697   },
4698
4699   /* PREFIX_VEX_3A14 */
4700   {
4701     { "(bad)",  { XX } },
4702     { "(bad)",  { XX } },
4703     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4704     { "(bad)",  { XX } },
4705   },
4706
4707   /* PREFIX_VEX_3A15 */
4708   {
4709     { "(bad)",  { XX } },
4710     { "(bad)",  { XX } },
4711     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4712     { "(bad)",  { XX } },
4713   },
4714
4715   /* PREFIX_VEX_3A16 */
4716   {
4717     { "(bad)",  { XX } },
4718     { "(bad)",  { XX } },
4719     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4720     { "(bad)",  { XX } },
4721   },
4722
4723   /* PREFIX_VEX_3A17 */
4724   {
4725     { "(bad)",  { XX } },
4726     { "(bad)",  { XX } },
4727     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4728     { "(bad)",  { XX } },
4729   },
4730
4731   /* PREFIX_VEX_3A18 */
4732   {
4733     { "(bad)",  { XX } },
4734     { "(bad)",  { XX } },
4735     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4736     { "(bad)",  { XX } },
4737   },
4738
4739   /* PREFIX_VEX_3A19 */
4740   {
4741     { "(bad)",  { XX } },
4742     { "(bad)",  { XX } },
4743     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4744     { "(bad)",  { XX } },
4745   },
4746
4747   /* PREFIX_VEX_3A20 */
4748   {
4749     { "(bad)",  { XX } },
4750     { "(bad)",  { XX } },
4751     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4752     { "(bad)",  { XX } },
4753   },
4754
4755   /* PREFIX_VEX_3A21 */
4756   {
4757     { "(bad)",  { XX } },
4758     { "(bad)",  { XX } },
4759     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4760     { "(bad)",  { XX } },
4761   },
4762
4763   /* PREFIX_VEX_3A22 */
4764   {
4765     { "(bad)",  { XX } },
4766     { "(bad)",  { XX } },
4767     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4768     { "(bad)",  { XX } },
4769   },
4770
4771   /* PREFIX_VEX_3A40 */
4772   {
4773     { "(bad)",  { XX } },
4774     { "(bad)",  { XX } },
4775     { "vdpps",  { XM, Vex, EXx, Ib } },
4776     { "(bad)",  { XX } },
4777   },
4778
4779   /* PREFIX_VEX_3A41 */
4780   {
4781     { "(bad)",  { XX } },
4782     { "(bad)",  { XX } },
4783     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4784     { "(bad)",  { XX } },
4785   },
4786
4787   /* PREFIX_VEX_3A42 */
4788   {
4789     { "(bad)",  { XX } },
4790     { "(bad)",  { XX } },
4791     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4792     { "(bad)",  { XX } },
4793   },
4794
4795   /* PREFIX_VEX_3A48 */
4796   {
4797     { "(bad)",  { XX } },
4798     { "(bad)",  { XX } },
4799     { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4800     { "(bad)",  { XX } },
4801   },
4802
4803   /* PREFIX_VEX_3A49 */
4804   {
4805     { "(bad)",  { XX } },
4806     { "(bad)",  { XX } },
4807     { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4808     { "(bad)",  { XX } },
4809   },
4810
4811   /* PREFIX_VEX_3A4A */
4812   {
4813     { "(bad)",  { XX } },
4814     { "(bad)",  { XX } },
4815     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4816     { "(bad)",  { XX } },
4817   },
4818
4819   /* PREFIX_VEX_3A4B */
4820   {
4821     { "(bad)",  { XX } },
4822     { "(bad)",  { XX } },
4823     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4824     { "(bad)",  { XX } },
4825   },
4826
4827   /* PREFIX_VEX_3A4C */
4828   {
4829     { "(bad)",  { XX } },
4830     { "(bad)",  { XX } },
4831     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4832     { "(bad)",  { XX } },
4833   },
4834
4835   /* PREFIX_VEX_3A5C */
4836   {
4837     { "(bad)",  { XX } },
4838     { "(bad)",  { XX } },
4839     { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4840     { "(bad)",  { XX } },
4841   },
4842
4843   /* PREFIX_VEX_3A5D */
4844   {
4845     { "(bad)",  { XX } },
4846     { "(bad)",  { XX } },
4847     { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4848     { "(bad)",  { XX } },
4849   },
4850
4851   /* PREFIX_VEX_3A5E */
4852   {
4853     { "(bad)",  { XX } },
4854     { "(bad)",  { XX } },
4855     { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4856     { "(bad)",  { XX } },
4857   },
4858
4859   /* PREFIX_VEX_3A5F */
4860   {
4861     { "(bad)",  { XX } },
4862     { "(bad)",  { XX } },
4863     { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4864     { "(bad)",  { XX } },
4865   },
4866
4867   /* PREFIX_VEX_3A60 */
4868   {
4869     { "(bad)",  { XX } },
4870     { "(bad)",  { XX } },
4871     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4872     { "(bad)",  { XX } },
4873   },
4874
4875   /* PREFIX_VEX_3A61 */
4876   {
4877     { "(bad)",  { XX } },
4878     { "(bad)",  { XX } },
4879     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4880     { "(bad)",  { XX } },
4881   },
4882
4883   /* PREFIX_VEX_3A62 */
4884   {
4885     { "(bad)",  { XX } },
4886     { "(bad)",  { XX } },
4887     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4888     { "(bad)",  { XX } },
4889   },
4890
4891   /* PREFIX_VEX_3A63 */
4892   {
4893     { "(bad)",  { XX } },
4894     { "(bad)",  { XX } },
4895     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4896     { "(bad)",  { XX } },
4897   },
4898
4899   /* PREFIX_VEX_3A68 */
4900   {
4901     { "(bad)",  { XX } },
4902     { "(bad)",  { XX } },
4903     { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4904     { "(bad)",  { XX } },
4905   },
4906
4907   /* PREFIX_VEX_3A69 */
4908   {
4909     { "(bad)",  { XX } },
4910     { "(bad)",  { XX } },
4911     { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4912     { "(bad)",  { XX } },
4913   },
4914
4915   /* PREFIX_VEX_3A6A */
4916   {
4917     { "(bad)",  { XX } },
4918     { "(bad)",  { XX } },
4919     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4920     { "(bad)",  { XX } },
4921   },
4922
4923   /* PREFIX_VEX_3A6B */
4924   {
4925     { "(bad)",  { XX } },
4926     { "(bad)",  { XX } },
4927     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4928     { "(bad)",  { XX } },
4929   },
4930
4931   /* PREFIX_VEX_3A6C */
4932   {
4933     { "(bad)",  { XX } },
4934     { "(bad)",  { XX } },
4935     { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4936     { "(bad)",  { XX } },
4937   },
4938
4939   /* PREFIX_VEX_3A6D */
4940   {
4941     { "(bad)",  { XX } },
4942     { "(bad)",  { XX } },
4943     { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4944     { "(bad)",  { XX } },
4945   },
4946
4947   /* PREFIX_VEX_3A6E */
4948   {
4949     { "(bad)",  { XX } },
4950     { "(bad)",  { XX } },
4951     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4952     { "(bad)",  { XX } },
4953   },
4954
4955   /* PREFIX_VEX_3A6F */
4956   {
4957     { "(bad)",  { XX } },
4958     { "(bad)",  { XX } },
4959     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4960     { "(bad)",  { XX } },
4961   },
4962
4963   /* PREFIX_VEX_3A78 */
4964   {
4965     { "(bad)",  { XX } },
4966     { "(bad)",  { XX } },
4967     { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4968     { "(bad)",  { XX } },
4969   },
4970
4971   /* PREFIX_VEX_3A79 */
4972   {
4973     { "(bad)",  { XX } },
4974     { "(bad)",  { XX } },
4975     { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4976     { "(bad)",  { XX } },
4977   },
4978
4979   /* PREFIX_VEX_3A7A */
4980   {
4981     { "(bad)",  { XX } },
4982     { "(bad)",  { XX } },
4983     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4984     { "(bad)",  { XX } },
4985   },
4986
4987   /* PREFIX_VEX_3A7B */
4988   {
4989     { "(bad)",  { XX } },
4990     { "(bad)",  { XX } },
4991     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4992     { "(bad)",  { XX } },
4993   },
4994
4995   /* PREFIX_VEX_3A7C */
4996   {
4997     { "(bad)",  { XX } },
4998     { "(bad)",  { XX } },
4999     { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5000     { "(bad)",  { XX } },
5001   },
5002
5003   /* PREFIX_VEX_3A7D */
5004   {
5005     { "(bad)",  { XX } },
5006     { "(bad)",  { XX } },
5007     { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5008     { "(bad)",  { XX } },
5009   },
5010
5011   /* PREFIX_VEX_3A7E */
5012   {
5013     { "(bad)",  { XX } },
5014     { "(bad)",  { XX } },
5015     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5016     { "(bad)",  { XX } },
5017   },
5018
5019   /* PREFIX_VEX_3A7F */
5020   {
5021     { "(bad)",  { XX } },
5022     { "(bad)",  { XX } },
5023     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5024     { "(bad)",  { XX } },
5025   },
5026
5027   /* PREFIX_VEX_3ADF */
5028   {
5029     { "(bad)",  { XX } },
5030     { "(bad)",  { XX } },
5031     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5032     { "(bad)",  { XX } },
5033   },
5034 };
5035
5036 static const struct dis386 x86_64_table[][2] = {
5037   /* X86_64_06 */
5038   {
5039     { "push{T|}", { es } },
5040     { "(bad)", { XX } },
5041   },
5042
5043   /* X86_64_07 */
5044   {
5045     { "pop{T|}", { es } },
5046     { "(bad)", { XX } },
5047   },
5048
5049   /* X86_64_0D */
5050   {
5051     { "push{T|}", { cs } },
5052     { "(bad)", { XX } },
5053   },
5054
5055   /* X86_64_16 */
5056   {
5057     { "push{T|}", { ss } },
5058     { "(bad)", { XX } },
5059   },
5060
5061   /* X86_64_17 */
5062   {
5063     { "pop{T|}", { ss } },
5064     { "(bad)", { XX } },
5065   },
5066
5067   /* X86_64_1E */
5068   {
5069     { "push{T|}", { ds } },
5070     { "(bad)", { XX } },
5071   },
5072
5073   /* X86_64_1F */
5074   {
5075     { "pop{T|}", { ds } },
5076     { "(bad)", { XX } },
5077   },
5078
5079   /* X86_64_27 */
5080   {
5081     { "daa", { XX } },
5082     { "(bad)", { XX } },
5083   },
5084
5085   /* X86_64_2F */
5086   {
5087     { "das", { XX } },
5088     { "(bad)", { XX } },
5089   },
5090
5091   /* X86_64_37 */
5092   {
5093     { "aaa", { XX } },
5094     { "(bad)", { XX } },
5095   },
5096
5097   /* X86_64_3F */
5098   {
5099     { "aas", { XX } },
5100     { "(bad)", { XX } },
5101   },
5102
5103   /* X86_64_60 */
5104   {
5105     { "pusha{P|}", { XX } },
5106     { "(bad)", { XX } },
5107   },
5108
5109   /* X86_64_61 */
5110   {
5111     { "popa{P|}", { XX } },
5112     { "(bad)", { XX } },
5113   },
5114
5115   /* X86_64_62 */
5116   {
5117     { MOD_TABLE (MOD_62_32BIT) },
5118     { "(bad)", { XX } },
5119   },
5120
5121   /* X86_64_63 */
5122   {
5123     { "arpl", { Ew, Gw } },
5124     { "movs{lq|xd}", { Gv, Ed } },
5125   },
5126
5127   /* X86_64_6D */
5128   {
5129     { "ins{R|}", { Yzr, indirDX } },
5130     { "ins{G|}", { Yzr, indirDX } },
5131   },
5132
5133   /* X86_64_6F */
5134   {
5135     { "outs{R|}", { indirDXr, Xz } },
5136     { "outs{G|}", { indirDXr, Xz } },
5137   },
5138
5139   /* X86_64_9A */
5140   {
5141     { "Jcall{T|}", { Ap } },
5142     { "(bad)", { XX } },
5143   },
5144
5145   /* X86_64_C4 */
5146   {
5147     { MOD_TABLE (MOD_C4_32BIT) },
5148     { VEX_C4_TABLE (VEX_0F) },
5149   },
5150
5151   /* X86_64_C5 */
5152   {
5153     { MOD_TABLE (MOD_C5_32BIT) },
5154     { VEX_C5_TABLE (VEX_0F) },
5155   },
5156
5157   /* X86_64_CE */
5158   {
5159     { "into", { XX } },
5160     { "(bad)", { XX } },
5161   },
5162
5163   /* X86_64_D4 */
5164   {
5165     { "aam", { sIb } },
5166     { "(bad)", { XX } },
5167   },
5168
5169   /* X86_64_D5 */
5170   {
5171     { "aad", { sIb } },
5172     { "(bad)", { XX } },
5173   },
5174
5175   /* X86_64_EA */
5176   {
5177     { "Jjmp{T|}", { Ap } },
5178     { "(bad)", { XX } },
5179   },
5180
5181   /* X86_64_0F01_REG_0 */
5182   {
5183     { "sgdt{Q|IQ}", { M } },
5184     { "sgdt", { M } },
5185   },
5186
5187   /* X86_64_0F01_REG_1 */
5188   {
5189     { "sidt{Q|IQ}", { M } },
5190     { "sidt", { M } },
5191   },
5192
5193   /* X86_64_0F01_REG_2 */
5194   {
5195     { "lgdt{Q|Q}", { M } },
5196     { "lgdt", { M } },
5197   },
5198
5199   /* X86_64_0F01_REG_3 */
5200   {
5201     { "lidt{Q|Q}", { M } },
5202     { "lidt", { M } },
5203   },
5204 };
5205
5206 static const struct dis386 three_byte_table[][256] = {
5207   /* THREE_BYTE_0F24 */
5208   {
5209     /* 00 */
5210     { "fmaddps",        { { OP_DREX4, q_mode } } },
5211     { "fmaddpd",        { { OP_DREX4, q_mode } } },
5212     { "fmaddss",        { { OP_DREX4, w_mode } } },
5213     { "fmaddsd",        { { OP_DREX4, d_mode } } },
5214     { "fmaddps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5215     { "fmaddpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5216     { "fmaddss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5217     { "fmaddsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5218     /* 08 */
5219     { "fmsubps",        { { OP_DREX4, q_mode } } },
5220     { "fmsubpd",        { { OP_DREX4, q_mode } } },
5221     { "fmsubss",        { { OP_DREX4, w_mode } } },
5222     { "fmsubsd",        { { OP_DREX4, d_mode } } },
5223     { "fmsubps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5224     { "fmsubpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5225     { "fmsubss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5226     { "fmsubsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5227     /* 10 */
5228     { "fnmaddps",       { { OP_DREX4, q_mode } } },
5229     { "fnmaddpd",       { { OP_DREX4, q_mode } } },
5230     { "fnmaddss",       { { OP_DREX4, w_mode } } },
5231     { "fnmaddsd",       { { OP_DREX4, d_mode } } },
5232     { "fnmaddps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5233     { "fnmaddpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5234     { "fnmaddss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5235     { "fnmaddsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5236     /* 18 */
5237     { "fnmsubps",       { { OP_DREX4, q_mode } } },
5238     { "fnmsubpd",       { { OP_DREX4, q_mode } } },
5239     { "fnmsubss",       { { OP_DREX4, w_mode } } },
5240     { "fnmsubsd",       { { OP_DREX4, d_mode } } },
5241     { "fnmsubps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5242     { "fnmsubpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5243     { "fnmsubss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5244     { "fnmsubsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5245     /* 20 */
5246     { "permps",         { { OP_DREX4, q_mode } } },
5247     { "permpd",         { { OP_DREX4, q_mode } } },
5248     { "pcmov",          { { OP_DREX4, q_mode } } },
5249     { "pperm",          { { OP_DREX4, q_mode } } },
5250     { "permps",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5251     { "permpd",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5252     { "pcmov",          { { OP_DREX4, DREX_OC1 + w_mode } } },
5253     { "pperm",          { { OP_DREX4, DREX_OC1 + d_mode } } },
5254     /* 28 */
5255     { "(bad)",          { XX } },
5256     { "(bad)",          { XX } },
5257     { "(bad)",          { XX } },
5258     { "(bad)",          { XX } },
5259     { "(bad)",          { XX } },
5260     { "(bad)",          { XX } },
5261     { "(bad)",          { XX } },
5262     { "(bad)",          { XX } },
5263     /* 30 */
5264     { "(bad)",          { XX } },
5265     { "(bad)",          { XX } },
5266     { "(bad)",          { XX } },
5267     { "(bad)",          { XX } },
5268     { "(bad)",          { XX } },
5269     { "(bad)",          { XX } },
5270     { "(bad)",          { XX } },
5271     { "(bad)",          { XX } },
5272     /* 38 */
5273     { "(bad)",          { XX } },
5274     { "(bad)",          { XX } },
5275     { "(bad)",          { XX } },
5276     { "(bad)",          { XX } },
5277     { "(bad)",          { XX } },
5278     { "(bad)",          { XX } },
5279     { "(bad)",          { XX } },
5280     { "(bad)",          { XX } },
5281     /* 40 */
5282     { "protb",          { { OP_DREX3, q_mode } } },
5283     { "protw",          { { OP_DREX3, q_mode } } },
5284     { "protd",          { { OP_DREX3, q_mode } } },
5285     { "protq",          { { OP_DREX3, q_mode } } },
5286     { "pshlb",          { { OP_DREX3, q_mode } } },
5287     { "pshlw",          { { OP_DREX3, q_mode } } },
5288     { "pshld",          { { OP_DREX3, q_mode } } },
5289     { "pshlq",          { { OP_DREX3, q_mode } } },
5290     /* 48 */
5291     { "pshab",          { { OP_DREX3, q_mode } } },
5292     { "pshaw",          { { OP_DREX3, q_mode } } },
5293     { "pshad",          { { OP_DREX3, q_mode } } },
5294     { "pshaq",          { { OP_DREX3, q_mode } } },
5295     { "(bad)",          { XX } },
5296     { "(bad)",          { XX } },
5297     { "(bad)",          { XX } },
5298     { "(bad)",          { XX } },
5299     /* 50 */
5300     { "(bad)",          { XX } },
5301     { "(bad)",          { XX } },
5302     { "(bad)",          { XX } },
5303     { "(bad)",          { XX } },
5304     { "(bad)",          { XX } },
5305     { "(bad)",          { XX } },
5306     { "(bad)",          { XX } },
5307     { "(bad)",          { XX } },
5308     /* 58 */
5309     { "(bad)",          { XX } },
5310     { "(bad)",          { XX } },
5311     { "(bad)",          { XX } },
5312     { "(bad)",          { XX } },
5313     { "(bad)",          { XX } },
5314     { "(bad)",          { XX } },
5315     { "(bad)",          { XX } },
5316     { "(bad)",          { XX } },
5317     /* 60 */
5318     { "(bad)",          { XX } },
5319     { "(bad)",          { XX } },
5320     { "(bad)",          { XX } },
5321     { "(bad)",          { XX } },
5322     { "(bad)",          { XX } },
5323     { "(bad)",          { XX } },
5324     { "(bad)",          { XX } },
5325     { "(bad)",          { XX } },
5326     /* 68 */
5327     { "(bad)",          { XX } },
5328     { "(bad)",          { XX } },
5329     { "(bad)",          { XX } },
5330     { "(bad)",          { XX } },
5331     { "(bad)",          { XX } },
5332     { "(bad)",          { XX } },
5333     { "(bad)",          { XX } },
5334     { "(bad)",          { XX } },
5335     /* 70 */
5336     { "(bad)",          { XX } },
5337     { "(bad)",          { XX } },
5338     { "(bad)",          { XX } },
5339     { "(bad)",          { XX } },
5340     { "(bad)",          { XX } },
5341     { "(bad)",          { XX } },
5342     { "(bad)",          { XX } },
5343     { "(bad)",          { XX } },
5344     /* 78 */
5345     { "(bad)",          { XX } },
5346     { "(bad)",          { XX } },
5347     { "(bad)",          { XX } },
5348     { "(bad)",          { XX } },
5349     { "(bad)",          { XX } },
5350     { "(bad)",          { XX } },
5351     { "(bad)",          { XX } },
5352     { "(bad)",          { XX } },
5353     /* 80 */
5354     { "(bad)",          { XX } },
5355     { "(bad)",          { XX } },
5356     { "(bad)",          { XX } },
5357     { "(bad)",          { XX } },
5358     { "(bad)",          { XX } },
5359     { "pmacssww",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5360     { "pmacsswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5361     { "pmacssdql",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5362     /* 88 */
5363     { "(bad)",          { XX } },
5364     { "(bad)",          { XX } },
5365     { "(bad)",          { XX } },
5366     { "(bad)",          { XX } },
5367     { "(bad)",          { XX } },
5368     { "(bad)",          { XX } },
5369     { "pmacssdd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5370     { "pmacssdqh",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5371     /* 90 */
5372     { "(bad)",          { XX } },
5373     { "(bad)",          { XX } },
5374     { "(bad)",          { XX } },
5375     { "(bad)",          { XX } },
5376     { "(bad)",          { XX } },
5377     { "pmacsww",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5378     { "pmacswd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5379     { "pmacsdql",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5380     /* 98 */
5381     { "(bad)",          { XX } },
5382     { "(bad)",          { XX } },
5383     { "(bad)",          { XX } },
5384     { "(bad)",          { XX } },
5385     { "(bad)",          { XX } },
5386     { "(bad)",          { XX } },
5387     { "pmacsdd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5388     { "pmacsdqh",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5389     /* a0 */
5390     { "(bad)",          { XX } },
5391     { "(bad)",          { XX } },
5392     { "(bad)",          { XX } },
5393     { "(bad)",          { XX } },
5394     { "(bad)",          { XX } },
5395     { "(bad)",          { XX } },
5396     { "pmadcsswd",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5397     { "(bad)",          { XX } },
5398     /* a8 */
5399     { "(bad)",          { XX } },
5400     { "(bad)",          { XX } },
5401     { "(bad)",          { XX } },
5402     { "(bad)",          { XX } },
5403     { "(bad)",          { XX } },
5404     { "(bad)",          { XX } },
5405     { "(bad)",          { XX } },
5406     { "(bad)",          { XX } },
5407     /* b0 */
5408     { "(bad)",          { XX } },
5409     { "(bad)",          { XX } },
5410     { "(bad)",          { XX } },
5411     { "(bad)",          { XX } },
5412     { "(bad)",          { XX } },
5413     { "(bad)",          { XX } },
5414     { "pmadcswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5415     { "(bad)",          { XX } },
5416     /* b8 */
5417     { "(bad)",          { XX } },
5418     { "(bad)",          { XX } },
5419     { "(bad)",          { XX } },
5420     { "(bad)",          { XX } },
5421     { "(bad)",          { XX } },
5422     { "(bad)",          { XX } },
5423     { "(bad)",          { XX } },
5424     { "(bad)",          { XX } },
5425     /* c0 */
5426     { "(bad)",          { XX } },
5427     { "(bad)",          { XX } },
5428     { "(bad)",          { XX } },
5429     { "(bad)",          { XX } },
5430     { "(bad)",          { XX } },
5431     { "(bad)",          { XX } },
5432     { "(bad)",          { XX } },
5433     { "(bad)",          { XX } },
5434     /* c8 */
5435     { "(bad)",          { XX } },
5436     { "(bad)",          { XX } },
5437     { "(bad)",          { XX } },
5438     { "(bad)",          { XX } },
5439     { "(bad)",          { XX } },
5440     { "(bad)",          { XX } },
5441     { "(bad)",          { XX } },
5442     { "(bad)",          { XX } },
5443     /* d0 */
5444     { "(bad)",          { XX } },
5445     { "(bad)",          { XX } },
5446     { "(bad)",          { XX } },
5447     { "(bad)",          { XX } },
5448     { "(bad)",          { XX } },
5449     { "(bad)",          { XX } },
5450     { "(bad)",          { XX } },
5451     { "(bad)",          { XX } },
5452     /* d8 */
5453     { "(bad)",          { XX } },
5454     { "(bad)",          { XX } },
5455     { "(bad)",          { XX } },
5456     { "(bad)",          { XX } },
5457     { "(bad)",          { XX } },
5458     { "(bad)",          { XX } },
5459     { "(bad)",          { XX } },
5460     { "(bad)",          { XX } },
5461     /* e0 */
5462     { "(bad)",          { XX } },
5463     { "(bad)",          { XX } },
5464     { "(bad)",          { XX } },
5465     { "(bad)",          { XX } },
5466     { "(bad)",          { XX } },
5467     { "(bad)",          { XX } },
5468     { "(bad)",          { XX } },
5469     { "(bad)",          { XX } },
5470     /* e8 */
5471     { "(bad)",          { XX } },
5472     { "(bad)",          { XX } },
5473     { "(bad)",          { XX } },
5474     { "(bad)",          { XX } },
5475     { "(bad)",          { XX } },
5476     { "(bad)",          { XX } },
5477     { "(bad)",          { XX } },
5478     { "(bad)",          { XX } },
5479     /* f0 */
5480     { "(bad)",          { XX } },
5481     { "(bad)",          { XX } },
5482     { "(bad)",          { XX } },
5483     { "(bad)",          { XX } },
5484     { "(bad)",          { XX } },
5485     { "(bad)",          { XX } },
5486     { "(bad)",          { XX } },
5487     { "(bad)",          { XX } },
5488     /* f8 */
5489     { "(bad)",          { XX } },
5490     { "(bad)",          { XX } },
5491     { "(bad)",          { XX } },
5492     { "(bad)",          { XX } },
5493     { "(bad)",          { XX } },
5494     { "(bad)",          { XX } },
5495     { "(bad)",          { XX } },
5496     { "(bad)",          { XX } },
5497   },
5498   /* THREE_BYTE_0F25 */
5499   {
5500     /* 00 */
5501     { "(bad)",          { XX } },
5502     { "(bad)",          { XX } },
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     { "(bad)",          { XX } },
5506     { "(bad)",          { XX } },
5507     { "(bad)",          { XX } },
5508     { "(bad)",          { XX } },
5509     /* 08 */
5510     { "(bad)",          { XX } },
5511     { "(bad)",          { XX } },
5512     { "(bad)",          { XX } },
5513     { "(bad)",          { XX } },
5514     { "(bad)",          { XX } },
5515     { "(bad)",          { XX } },
5516     { "(bad)",          { XX } },
5517     { "(bad)",          { XX } },
5518     /* 10 */
5519     { "(bad)",          { XX } },
5520     { "(bad)",          { XX } },
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     { "(bad)",          { XX } },
5527     /* 18 */
5528     { "(bad)",          { XX } },
5529     { "(bad)",          { XX } },
5530     { "(bad)",          { XX } },
5531     { "(bad)",          { XX } },
5532     { "(bad)",          { XX } },
5533     { "(bad)",          { XX } },
5534     { "(bad)",          { XX } },
5535     { "(bad)",          { XX } },
5536     /* 20 */
5537     { "(bad)",          { XX } },
5538     { "(bad)",          { XX } },
5539     { "(bad)",          { XX } },
5540     { "(bad)",          { XX } },
5541     { "(bad)",          { XX } },
5542     { "(bad)",          { XX } },
5543     { "(bad)",          { XX } },
5544     { "(bad)",          { XX } },
5545     /* 28 */
5546     { "(bad)",          { XX } },
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "comps",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5551     { "compd",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5552     { "comss",          { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5553     { "comsd",          { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5554     /* 30 */
5555     { "(bad)",          { XX } },
5556     { "(bad)",          { XX } },
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563     /* 38 */
5564     { "(bad)",          { XX } },
5565     { "(bad)",          { XX } },
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     /* 40 */
5573     { "(bad)",          { XX } },
5574     { "(bad)",          { XX } },
5575     { "(bad)",          { XX } },
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     { "(bad)",          { XX } },
5581     /* 48 */
5582     { "(bad)",          { XX } },
5583     { "(bad)",          { XX } },
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "pcomb",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5587     { "pcomw",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5588     { "pcomd",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5589     { "pcomq",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5590     /* 50 */
5591     { "(bad)",          { XX } },
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     /* 58 */
5600     { "(bad)",          { XX } },
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     { "(bad)",          { XX } },
5608     /* 60 */
5609     { "(bad)",          { XX } },
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "(bad)",          { XX } },
5617     /* 68 */
5618     { "(bad)",          { XX } },
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "pcomub",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5623     { "pcomuw",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5624     { "pcomud",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5625     { "pcomuq",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5626     /* 70 */
5627     { "(bad)",          { XX } },
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     /* 78 */
5636     { "(bad)",          { XX } },
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     { "(bad)",          { XX } },
5644     /* 80 */
5645     { "(bad)",          { XX } },
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "(bad)",          { XX } },
5653     /* 88 */
5654     { "(bad)",          { XX } },
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     /* 90 */
5663     { "(bad)",          { XX } },
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     /* 98 */
5672     { "(bad)",          { XX } },
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     { "(bad)",          { XX } },
5680     /* a0 */
5681     { "(bad)",          { XX } },
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     { "(bad)",          { XX } },
5689     /* a8 */
5690     { "(bad)",          { XX } },
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     { "(bad)",          { XX } },
5698     /* b0 */
5699     { "(bad)",          { XX } },
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     /* b8 */
5708     { "(bad)",          { XX } },
5709     { "(bad)",          { XX } },
5710     { "(bad)",          { XX } },
5711     { "(bad)",          { XX } },
5712     { "(bad)",          { XX } },
5713     { "(bad)",          { XX } },
5714     { "(bad)",          { XX } },
5715     { "(bad)",          { XX } },
5716     /* c0 */
5717     { "(bad)",          { XX } },
5718     { "(bad)",          { XX } },
5719     { "(bad)",          { XX } },
5720     { "(bad)",          { XX } },
5721     { "(bad)",          { XX } },
5722     { "(bad)",          { XX } },
5723     { "(bad)",          { XX } },
5724     { "(bad)",          { XX } },
5725     /* c8 */
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     { "(bad)",          { XX } },
5730     { "(bad)",          { XX } },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     { "(bad)",          { XX } },
5734     /* d0 */
5735     { "(bad)",          { XX } },
5736     { "(bad)",          { XX } },
5737     { "(bad)",          { XX } },
5738     { "(bad)",          { XX } },
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     { "(bad)",          { XX } },
5743     /* d8 */
5744     { "(bad)",          { XX } },
5745     { "(bad)",          { XX } },
5746     { "(bad)",          { XX } },
5747     { "(bad)",          { XX } },
5748     { "(bad)",          { XX } },
5749     { "(bad)",          { XX } },
5750     { "(bad)",          { XX } },
5751     { "(bad)",          { XX } },
5752     /* e0 */
5753     { "(bad)",          { XX } },
5754     { "(bad)",          { XX } },
5755     { "(bad)",          { XX } },
5756     { "(bad)",          { XX } },
5757     { "(bad)",          { XX } },
5758     { "(bad)",          { XX } },
5759     { "(bad)",          { XX } },
5760     { "(bad)",          { XX } },
5761     /* e8 */
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     { "(bad)",          { XX } },
5766     { "(bad)",          { XX } },
5767     { "(bad)",          { XX } },
5768     { "(bad)",          { XX } },
5769     { "(bad)",          { XX } },
5770     /* f0 */
5771     { "(bad)",          { XX } },
5772     { "(bad)",          { XX } },
5773     { "(bad)",          { XX } },
5774     { "(bad)",          { XX } },
5775     { "(bad)",          { XX } },
5776     { "(bad)",          { XX } },
5777     { "(bad)",          { XX } },
5778     { "(bad)",          { XX } },
5779     /* f8 */
5780     { "(bad)",          { XX } },
5781     { "(bad)",          { XX } },
5782     { "(bad)",          { XX } },
5783     { "(bad)",          { XX } },
5784     { "(bad)",          { XX } },
5785     { "(bad)",          { XX } },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788   },
5789   /* THREE_BYTE_0F38 */
5790   {
5791     /* 00 */
5792     { "pshufb",         { MX, EM } },
5793     { "phaddw",         { MX, EM } },
5794     { "phaddd",         { MX, EM } },
5795     { "phaddsw",        { MX, EM } },
5796     { "pmaddubsw",      { MX, EM } },
5797     { "phsubw",         { MX, EM } },
5798     { "phsubd",         { MX, EM } },
5799     { "phsubsw",        { MX, EM } },
5800     /* 08 */
5801     { "psignb",         { MX, EM } },
5802     { "psignw",         { MX, EM } },
5803     { "psignd",         { MX, EM } },
5804     { "pmulhrsw",       { MX, EM } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     { "(bad)",          { XX } },
5809     /* 10 */
5810     { PREFIX_TABLE (PREFIX_0F3810) },
5811     { "(bad)",          { XX } },
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { PREFIX_TABLE (PREFIX_0F3814) },
5815     { PREFIX_TABLE (PREFIX_0F3815) },
5816     { "(bad)",          { XX } },
5817     { PREFIX_TABLE (PREFIX_0F3817) },
5818     /* 18 */
5819     { "(bad)",          { XX } },
5820     { "(bad)",          { XX } },
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "pabsb",          { MX, EM } },
5824     { "pabsw",          { MX, EM } },
5825     { "pabsd",          { MX, EM } },
5826     { "(bad)",          { XX } },
5827     /* 20 */
5828     { PREFIX_TABLE (PREFIX_0F3820) },
5829     { PREFIX_TABLE (PREFIX_0F3821) },
5830     { PREFIX_TABLE (PREFIX_0F3822) },
5831     { PREFIX_TABLE (PREFIX_0F3823) },
5832     { PREFIX_TABLE (PREFIX_0F3824) },
5833     { PREFIX_TABLE (PREFIX_0F3825) },
5834     { "(bad)",          { XX } },
5835     { "(bad)",          { XX } },
5836     /* 28 */
5837     { PREFIX_TABLE (PREFIX_0F3828) },
5838     { PREFIX_TABLE (PREFIX_0F3829) },
5839     { PREFIX_TABLE (PREFIX_0F382A) },
5840     { PREFIX_TABLE (PREFIX_0F382B) },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844     { "(bad)",          { XX } },
5845     /* 30 */
5846     { PREFIX_TABLE (PREFIX_0F3830) },
5847     { PREFIX_TABLE (PREFIX_0F3831) },
5848     { PREFIX_TABLE (PREFIX_0F3832) },
5849     { PREFIX_TABLE (PREFIX_0F3833) },
5850     { PREFIX_TABLE (PREFIX_0F3834) },
5851     { PREFIX_TABLE (PREFIX_0F3835) },
5852     { "(bad)",          { XX } },
5853     { PREFIX_TABLE (PREFIX_0F3837) },
5854     /* 38 */
5855     { PREFIX_TABLE (PREFIX_0F3838) },
5856     { PREFIX_TABLE (PREFIX_0F3839) },
5857     { PREFIX_TABLE (PREFIX_0F383A) },
5858     { PREFIX_TABLE (PREFIX_0F383B) },
5859     { PREFIX_TABLE (PREFIX_0F383C) },
5860     { PREFIX_TABLE (PREFIX_0F383D) },
5861     { PREFIX_TABLE (PREFIX_0F383E) },
5862     { PREFIX_TABLE (PREFIX_0F383F) },
5863     /* 40 */
5864     { PREFIX_TABLE (PREFIX_0F3840) },
5865     { PREFIX_TABLE (PREFIX_0F3841) },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     { "(bad)",          { XX } },
5872     /* 48 */
5873     { "(bad)",          { XX } },
5874     { "(bad)",          { XX } },
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     { "(bad)",          { XX } },
5881     /* 50 */
5882     { "(bad)",          { XX } },
5883     { "(bad)",          { XX } },
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     { "(bad)",          { XX } },
5890     /* 58 */
5891     { "(bad)",          { XX } },
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     { "(bad)",          { XX } },
5899     /* 60 */
5900     { "(bad)",          { XX } },
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     { "(bad)",          { XX } },
5908     /* 68 */
5909     { "(bad)",          { XX } },
5910     { "(bad)",          { XX } },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     { "(bad)",          { XX } },
5917     /* 70 */
5918     { "(bad)",          { XX } },
5919     { "(bad)",          { XX } },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     { "(bad)",          { XX } },
5926     /* 78 */
5927     { "(bad)",          { XX } },
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     { "(bad)",          { XX } },
5935     /* 80 */
5936     { PREFIX_TABLE (PREFIX_0F3880) },
5937     { PREFIX_TABLE (PREFIX_0F3881) },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     /* 88 */
5945     { "(bad)",          { XX } },
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     /* 90 */
5954     { "(bad)",          { XX } },
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { "(bad)",          { XX } },
5959     { "(bad)",          { XX } },
5960     { "(bad)",          { XX } },
5961     { "(bad)",          { XX } },
5962     /* 98 */
5963     { "(bad)",          { XX } },
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     /* a0 */
5972     { "(bad)",          { XX } },
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     /* a8 */
5981     { "(bad)",          { XX } },
5982     { "(bad)",          { XX } },
5983     { "(bad)",          { XX } },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     { "(bad)",          { XX } },
5989     /* b0 */
5990     { "(bad)",          { XX } },
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     /* b8 */
5999     { "(bad)",          { XX } },
6000     { "(bad)",          { XX } },
6001     { "(bad)",          { XX } },
6002     { "(bad)",          { XX } },
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     /* c0 */
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     { "(bad)",          { XX } },
6012     { "(bad)",          { XX } },
6013     { "(bad)",          { XX } },
6014     { "(bad)",          { XX } },
6015     { "(bad)",          { XX } },
6016     /* c8 */
6017     { "(bad)",          { XX } },
6018     { "(bad)",          { XX } },
6019     { "(bad)",          { XX } },
6020     { "(bad)",          { XX } },
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     /* d0 */
6026     { "(bad)",          { XX } },
6027     { "(bad)",          { XX } },
6028     { "(bad)",          { XX } },
6029     { "(bad)",          { XX } },
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     /* d8 */
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     { PREFIX_TABLE (PREFIX_0F38DB) },
6039     { PREFIX_TABLE (PREFIX_0F38DC) },
6040     { PREFIX_TABLE (PREFIX_0F38DD) },
6041     { PREFIX_TABLE (PREFIX_0F38DE) },
6042     { PREFIX_TABLE (PREFIX_0F38DF) },
6043     /* e0 */
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     { "(bad)",          { XX } },
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { "(bad)",          { XX } },
6051     { "(bad)",          { XX } },
6052     /* e8 */
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     { "(bad)",          { XX } },
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     /* f0 */
6062     { PREFIX_TABLE (PREFIX_0F38F0) },
6063     { PREFIX_TABLE (PREFIX_0F38F1) },
6064     { "(bad)",          { XX } },
6065     { "(bad)",          { XX } },
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     /* f8 */
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     { "(bad)",          { XX } },
6075     { "(bad)",          { XX } },
6076     { "(bad)",          { XX } },
6077     { "(bad)",          { XX } },
6078     { "(bad)",          { XX } },
6079   },
6080   /* THREE_BYTE_0F3A */
6081   {
6082     /* 00 */
6083     { "(bad)",          { XX } },
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     { "(bad)",          { XX } },
6087     { "(bad)",          { XX } },
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     /* 08 */
6092     { PREFIX_TABLE (PREFIX_0F3A08) },
6093     { PREFIX_TABLE (PREFIX_0F3A09) },
6094     { PREFIX_TABLE (PREFIX_0F3A0A) },
6095     { PREFIX_TABLE (PREFIX_0F3A0B) },
6096     { PREFIX_TABLE (PREFIX_0F3A0C) },
6097     { PREFIX_TABLE (PREFIX_0F3A0D) },
6098     { PREFIX_TABLE (PREFIX_0F3A0E) },
6099     { "palignr",        { MX, EM, Ib } },
6100     /* 10 */
6101     { "(bad)",          { XX } },
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { PREFIX_TABLE (PREFIX_0F3A14) },
6106     { PREFIX_TABLE (PREFIX_0F3A15) },
6107     { PREFIX_TABLE (PREFIX_0F3A16) },
6108     { PREFIX_TABLE (PREFIX_0F3A17) },
6109     /* 18 */
6110     { "(bad)",          { XX } },
6111     { "(bad)",          { XX } },
6112     { "(bad)",          { XX } },
6113     { "(bad)",          { XX } },
6114     { "(bad)",          { XX } },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     /* 20 */
6119     { PREFIX_TABLE (PREFIX_0F3A20) },
6120     { PREFIX_TABLE (PREFIX_0F3A21) },
6121     { PREFIX_TABLE (PREFIX_0F3A22) },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     /* 28 */
6128     { "(bad)",          { XX } },
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     { "(bad)",          { XX } },
6136     /* 30 */
6137     { "(bad)",          { XX } },
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145     /* 38 */
6146     { "(bad)",          { XX } },
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     { "(bad)",          { XX } },
6154     /* 40 */
6155     { PREFIX_TABLE (PREFIX_0F3A40) },
6156     { PREFIX_TABLE (PREFIX_0F3A41) },
6157     { PREFIX_TABLE (PREFIX_0F3A42) },
6158     { "(bad)",          { XX } },
6159     { PREFIX_TABLE (PREFIX_0F3A44) },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     { "(bad)",          { XX } },
6163     /* 48 */
6164     { "(bad)",          { XX } },
6165     { "(bad)",          { XX } },
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { "(bad)",          { XX } },
6172     /* 50 */
6173     { "(bad)",          { XX } },
6174     { "(bad)",          { XX } },
6175     { "(bad)",          { XX } },
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     /* 58 */
6182     { "(bad)",          { XX } },
6183     { "(bad)",          { XX } },
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     /* 60 */
6191     { PREFIX_TABLE (PREFIX_0F3A60) },
6192     { PREFIX_TABLE (PREFIX_0F3A61) },
6193     { PREFIX_TABLE (PREFIX_0F3A62) },
6194     { PREFIX_TABLE (PREFIX_0F3A63) },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     /* 68 */
6200     { "(bad)",          { XX } },
6201     { "(bad)",          { XX } },
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     /* 70 */
6209     { "(bad)",          { XX } },
6210     { "(bad)",          { XX } },
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     /* 78 */
6218     { "(bad)",          { XX } },
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     /* 80 */
6227     { "(bad)",          { XX } },
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     /* 88 */
6236     { "(bad)",          { XX } },
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     /* 90 */
6245     { "(bad)",          { XX } },
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     /* 98 */
6254     { "(bad)",          { XX } },
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     /* a0 */
6263     { "(bad)",          { XX } },
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     /* a8 */
6272     { "(bad)",          { XX } },
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     /* b0 */
6281     { "(bad)",          { XX } },
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     /* b8 */
6290     { "(bad)",          { XX } },
6291     { "(bad)",          { XX } },
6292     { "(bad)",          { XX } },
6293     { "(bad)",          { XX } },
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     /* c0 */
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     { "(bad)",          { XX } },
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     /* c8 */
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     { "(bad)",          { XX } },
6312     { "(bad)",          { XX } },
6313     { "(bad)",          { XX } },
6314     { "(bad)",          { XX } },
6315     { "(bad)",          { XX } },
6316     /* d0 */
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     { "(bad)",          { XX } },
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     /* d8 */
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     { "(bad)",          { XX } },
6330     { "(bad)",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { PREFIX_TABLE (PREFIX_0F3ADF) },
6334     /* e0 */
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     { "(bad)",          { XX } },
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     /* e8 */
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     { "(bad)",          { XX } },
6348     { "(bad)",          { XX } },
6349     { "(bad)",          { XX } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     /* f0 */
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     { "(bad)",          { XX } },
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     /* f8 */
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     { "(bad)",          { XX } },
6366     { "(bad)",          { XX } },
6367     { "(bad)",          { XX } },
6368     { "(bad)",          { XX } },
6369     { "(bad)",          { XX } },
6370   },
6371   /* THREE_BYTE_0F7A */
6372   {
6373     /* 00 */
6374     { "(bad)",          { XX } },
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     { "(bad)",          { XX } },
6379     { "(bad)",          { XX } },
6380     { "(bad)",          { XX } },
6381     { "(bad)",          { XX } },
6382     /* 08 */
6383     { "(bad)",          { XX } },
6384     { "(bad)",          { XX } },
6385     { "(bad)",          { XX } },
6386     { "(bad)",          { XX } },
6387     { "(bad)",          { XX } },
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "(bad)",          { XX } },
6391     /* 10 */
6392     { "frczps",         { XM, EXq } },
6393     { "frczpd",         { XM, EXq } },
6394     { "frczss",         { XM, EXq } },
6395     { "frczsd",         { XM, EXq } },
6396     { "(bad)",          { XX } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     /* 18 */
6401     { "(bad)",          { XX } },
6402     { "(bad)",          { XX } },
6403     { "(bad)",          { XX } },
6404     { "(bad)",          { XX } },
6405     { "(bad)",          { XX } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     /* 20 */
6410     { "ptest",          { XX } },
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     /* 28 */
6419     { "(bad)",          { XX } },
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     /* 30 */
6428     { "cvtph2ps",       { XM, EXd } },
6429     { "cvtps2ph",       { EXd, XM } },
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     /* 38 */
6437     { "(bad)",          { XX } },
6438     { "(bad)",          { XX } },
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     /* 40 */
6446     { "(bad)",          { XX } },
6447     { "phaddbw",        { XM, EXq } },
6448     { "phaddbd",        { XM, EXq } },
6449     { "phaddbq",        { XM, EXq } },
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "phaddwd",        { XM, EXq } },
6453     { "phaddwq",        { XM, EXq } },
6454     /* 48 */
6455     { "(bad)",          { XX } },
6456     { "(bad)",          { XX } },
6457     { "(bad)",          { XX } },
6458     { "phadddq",        { XM, EXq } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     /* 50 */
6464     { "(bad)",          { XX } },
6465     { "phaddubw",       { XM, EXq } },
6466     { "phaddubd",       { XM, EXq } },
6467     { "phaddubq",       { XM, EXq } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "phadduwd",       { XM, EXq } },
6471     { "phadduwq",       { XM, EXq } },
6472     /* 58 */
6473     { "(bad)",          { XX } },
6474     { "(bad)",          { XX } },
6475     { "(bad)",          { XX } },
6476     { "phaddudq",       { XM, EXq } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     /* 60 */
6482     { "(bad)",          { XX } },
6483     { "phsubbw",        { XM, EXq } },
6484     { "phsubbd",        { XM, EXq } },
6485     { "phsubbq",        { XM, EXq } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     /* 68 */
6491     { "(bad)",          { XX } },
6492     { "(bad)",          { XX } },
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     /* 70 */
6500     { "(bad)",          { XX } },
6501     { "(bad)",          { XX } },
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     /* 78 */
6509     { "(bad)",          { XX } },
6510     { "(bad)",          { XX } },
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     /* 80 */
6518     { "(bad)",          { XX } },
6519     { "(bad)",          { XX } },
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     /* 88 */
6527     { "(bad)",          { XX } },
6528     { "(bad)",          { XX } },
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     /* 90 */
6536     { "(bad)",          { XX } },
6537     { "(bad)",          { XX } },
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     /* 98 */
6545     { "(bad)",          { XX } },
6546     { "(bad)",          { XX } },
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     /* a0 */
6554     { "(bad)",          { XX } },
6555     { "(bad)",          { XX } },
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     /* a8 */
6563     { "(bad)",          { XX } },
6564     { "(bad)",          { XX } },
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     /* b0 */
6572     { "(bad)",          { XX } },
6573     { "(bad)",          { XX } },
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     /* b8 */
6581     { "(bad)",          { XX } },
6582     { "(bad)",          { XX } },
6583     { "(bad)",          { XX } },
6584     { "(bad)",          { XX } },
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     /* c0 */
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     { "(bad)",          { XX } },
6593     { "(bad)",          { XX } },
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     /* c8 */
6599     { "(bad)",          { XX } },
6600     { "(bad)",          { XX } },
6601     { "(bad)",          { XX } },
6602     { "(bad)",          { XX } },
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     /* d0 */
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     { "(bad)",          { XX } },
6611     { "(bad)",          { XX } },
6612     { "(bad)",          { XX } },
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     /* d8 */
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     { "(bad)",          { XX } },
6620     { "(bad)",          { XX } },
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     /* e0 */
6626     { "(bad)",          { XX } },
6627     { "(bad)",          { XX } },
6628     { "(bad)",          { XX } },
6629     { "(bad)",          { XX } },
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     /* e8 */
6635     { "(bad)",          { XX } },
6636     { "(bad)",          { XX } },
6637     { "(bad)",          { XX } },
6638     { "(bad)",          { XX } },
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     /* f0 */
6644     { "(bad)",          { XX } },
6645     { "(bad)",          { XX } },
6646     { "(bad)",          { XX } },
6647     { "(bad)",          { XX } },
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     /* f8 */
6653     { "(bad)",          { XX } },
6654     { "(bad)",          { XX } },
6655     { "(bad)",          { XX } },
6656     { "(bad)",          { XX } },
6657     { "(bad)",          { XX } },
6658     { "(bad)",          { XX } },
6659     { "(bad)",          { XX } },
6660     { "(bad)",          { XX } },
6661   },
6662   /* THREE_BYTE_0F7B */
6663   {
6664     /* 00 */
6665     { "(bad)",          { XX } },
6666     { "(bad)",          { XX } },
6667     { "(bad)",          { XX } },
6668     { "(bad)",          { XX } },
6669     { "(bad)",          { XX } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     { "(bad)",          { XX } },
6673     /* 08 */
6674     { "(bad)",          { XX } },
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     /* 10 */
6683     { "(bad)",          { XX } },
6684     { "(bad)",          { XX } },
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     /* 18 */
6692     { "(bad)",          { XX } },
6693     { "(bad)",          { XX } },
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     /* 20 */
6701     { "(bad)",          { XX } },
6702     { "(bad)",          { XX } },
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     /* 28 */
6710     { "(bad)",          { XX } },
6711     { "(bad)",          { XX } },
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     /* 30 */
6719     { "(bad)",          { XX } },
6720     { "(bad)",          { XX } },
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     /* 38 */
6728     { "(bad)",          { XX } },
6729     { "(bad)",          { XX } },
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     /* 40 */
6737     { "protb",          { XM, EXq, Ib } },
6738     { "protw",          { XM, EXq, Ib } },
6739     { "protd",          { XM, EXq, Ib } },
6740     { "protq",          { XM, EXq, Ib } },
6741     { "pshlb",          { XM, EXq, Ib } },
6742     { "pshlw",          { XM, EXq, Ib } },
6743     { "pshld",          { XM, EXq, Ib } },
6744     { "pshlq",          { XM, EXq, Ib } },
6745     /* 48 */
6746     { "pshab",          { XM, EXq, Ib } },
6747     { "pshaw",          { XM, EXq, Ib } },
6748     { "pshad",          { XM, EXq, Ib } },
6749     { "pshaq",          { XM, EXq, Ib } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     /* 50 */
6755     { "(bad)",          { XX } },
6756     { "(bad)",          { XX } },
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     /* 58 */
6764     { "(bad)",          { XX } },
6765     { "(bad)",          { XX } },
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     /* 60 */
6773     { "(bad)",          { XX } },
6774     { "(bad)",          { XX } },
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     /* 68 */
6782     { "(bad)",          { XX } },
6783     { "(bad)",          { XX } },
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     /* 70 */
6791     { "(bad)",          { XX } },
6792     { "(bad)",          { XX } },
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     /* 78 */
6800     { "(bad)",          { XX } },
6801     { "(bad)",          { XX } },
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     /* 80 */
6809     { "(bad)",          { XX } },
6810     { "(bad)",          { XX } },
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     /* 88 */
6818     { "(bad)",          { XX } },
6819     { "(bad)",          { XX } },
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     /* 90 */
6827     { "(bad)",          { XX } },
6828     { "(bad)",          { XX } },
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     /* 98 */
6836     { "(bad)",          { XX } },
6837     { "(bad)",          { XX } },
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     /* a0 */
6845     { "(bad)",          { XX } },
6846     { "(bad)",          { XX } },
6847     { "(bad)",          { XX } },
6848     { "(bad)",          { XX } },
6849     { "(bad)",          { XX } },
6850     { "(bad)",          { XX } },
6851     { "(bad)",          { XX } },
6852     { "(bad)",          { XX } },
6853     /* a8 */
6854     { "(bad)",          { XX } },
6855     { "(bad)",          { XX } },
6856     { "(bad)",          { XX } },
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     /* b0 */
6863     { "(bad)",          { XX } },
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     /* b8 */
6872     { "(bad)",          { XX } },
6873     { "(bad)",          { XX } },
6874     { "(bad)",          { XX } },
6875     { "(bad)",          { XX } },
6876     { "(bad)",          { XX } },
6877     { "(bad)",          { XX } },
6878     { "(bad)",          { XX } },
6879     { "(bad)",          { XX } },
6880     /* c0 */
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     { "(bad)",          { XX } },
6888     { "(bad)",          { XX } },
6889     /* c8 */
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     { "(bad)",          { XX } },
6897     { "(bad)",          { XX } },
6898     /* d0 */
6899     { "(bad)",          { XX } },
6900     { "(bad)",          { XX } },
6901     { "(bad)",          { XX } },
6902     { "(bad)",          { XX } },
6903     { "(bad)",          { XX } },
6904     { "(bad)",          { XX } },
6905     { "(bad)",          { XX } },
6906     { "(bad)",          { XX } },
6907     /* d8 */
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     { "(bad)",          { XX } },
6915     { "(bad)",          { XX } },
6916     /* e0 */
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     { "(bad)",          { XX } },
6924     { "(bad)",          { XX } },
6925     /* e8 */
6926     { "(bad)",          { XX } },
6927     { "(bad)",          { XX } },
6928     { "(bad)",          { XX } },
6929     { "(bad)",          { XX } },
6930     { "(bad)",          { XX } },
6931     { "(bad)",          { XX } },
6932     { "(bad)",          { XX } },
6933     { "(bad)",          { XX } },
6934     /* f0 */
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     { "(bad)",          { XX } },
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     { "(bad)",          { XX } },
6942     { "(bad)",          { XX } },
6943     /* f8 */
6944     { "(bad)",          { XX } },
6945     { "(bad)",          { XX } },
6946     { "(bad)",          { XX } },
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     { "(bad)",          { XX } },
6951     { "(bad)",          { XX } },
6952   },
6953 };
6954
6955 static const struct dis386 vex_table[][256] = {
6956   /* VEX_0F */
6957   {
6958     /* 00 */
6959     { "(bad)",          { XX } },
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     { "(bad)",          { XX } },
6964     { "(bad)",          { XX } },
6965     { "(bad)",          { XX } },
6966     { "(bad)",          { XX } },
6967     /* 08 */
6968     { "(bad)",          { XX } },
6969     { "(bad)",          { XX } },
6970     { "(bad)",          { XX } },
6971     { "(bad)",          { XX } },
6972     { "(bad)",          { XX } },
6973     { "(bad)",          { XX } },
6974     { "(bad)",          { XX } },
6975     { "(bad)",          { XX } },
6976     /* 10 */
6977     { PREFIX_TABLE (PREFIX_VEX_10) },
6978     { PREFIX_TABLE (PREFIX_VEX_11) },
6979     { PREFIX_TABLE (PREFIX_VEX_12) },
6980     { MOD_TABLE (MOD_VEX_13) },
6981     { "vunpcklpX",      { XM, Vex, EXx } },
6982     { "vunpckhpX",      { XM, Vex, EXx } },
6983     { PREFIX_TABLE (PREFIX_VEX_16) },
6984     { MOD_TABLE (MOD_VEX_17) },
6985     /* 18 */
6986     { "(bad)",          { XX } },
6987     { "(bad)",          { XX } },
6988     { "(bad)",          { XX } },
6989     { "(bad)",          { XX } },
6990     { "(bad)",          { XX } },
6991     { "(bad)",          { XX } },
6992     { "(bad)",          { XX } },
6993     { "(bad)",          { XX } },
6994     /* 20 */
6995     { "(bad)",          { XX } },
6996     { "(bad)",          { XX } },
6997     { "(bad)",          { XX } },
6998     { "(bad)",          { XX } },
6999     { "(bad)",          { XX } },
7000     { "(bad)",          { XX } },
7001     { "(bad)",          { XX } },
7002     { "(bad)",          { XX } },
7003     /* 28 */
7004     { "vmovapX",        { XM, EXx } },
7005     { "vmovapX",        { EXxS, XM } },
7006     { PREFIX_TABLE (PREFIX_VEX_2A) },
7007     { MOD_TABLE (MOD_VEX_2B) },
7008     { PREFIX_TABLE (PREFIX_VEX_2C) },
7009     { PREFIX_TABLE (PREFIX_VEX_2D) },
7010     { PREFIX_TABLE (PREFIX_VEX_2E) },
7011     { PREFIX_TABLE (PREFIX_VEX_2F) },
7012     /* 30 */
7013     { "(bad)",          { XX } },
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018     { "(bad)",          { XX } },
7019     { "(bad)",          { XX } },
7020     { "(bad)",          { XX } },
7021     /* 38 */
7022     { "(bad)",          { XX } },
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     /* 40 */
7031     { "(bad)",          { XX } },
7032     { "(bad)",          { XX } },
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     /* 48 */
7040     { "(bad)",          { XX } },
7041     { "(bad)",          { XX } },
7042     { "(bad)",          { XX } },
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     /* 50 */
7049     { MOD_TABLE (MOD_VEX_51) },
7050     { PREFIX_TABLE (PREFIX_VEX_51) },
7051     { PREFIX_TABLE (PREFIX_VEX_52) },
7052     { PREFIX_TABLE (PREFIX_VEX_53) },
7053     { "vandpX",         { XM, Vex, EXx } },
7054     { "vandnpX",        { XM, Vex, EXx } },
7055     { "vorpX",          { XM, Vex, EXx } },
7056     { "vxorpX",         { XM, Vex, EXx } },
7057     /* 58 */
7058     { PREFIX_TABLE (PREFIX_VEX_58) },
7059     { PREFIX_TABLE (PREFIX_VEX_59) },
7060     { PREFIX_TABLE (PREFIX_VEX_5A) },
7061     { PREFIX_TABLE (PREFIX_VEX_5B) },
7062     { PREFIX_TABLE (PREFIX_VEX_5C) },
7063     { PREFIX_TABLE (PREFIX_VEX_5D) },
7064     { PREFIX_TABLE (PREFIX_VEX_5E) },
7065     { PREFIX_TABLE (PREFIX_VEX_5F) },
7066     /* 60 */
7067     { PREFIX_TABLE (PREFIX_VEX_60) },
7068     { PREFIX_TABLE (PREFIX_VEX_61) },
7069     { PREFIX_TABLE (PREFIX_VEX_62) },
7070     { PREFIX_TABLE (PREFIX_VEX_63) },
7071     { PREFIX_TABLE (PREFIX_VEX_64) },
7072     { PREFIX_TABLE (PREFIX_VEX_65) },
7073     { PREFIX_TABLE (PREFIX_VEX_66) },
7074     { PREFIX_TABLE (PREFIX_VEX_67) },
7075     /* 68 */
7076     { PREFIX_TABLE (PREFIX_VEX_68) },
7077     { PREFIX_TABLE (PREFIX_VEX_69) },
7078     { PREFIX_TABLE (PREFIX_VEX_6A) },
7079     { PREFIX_TABLE (PREFIX_VEX_6B) },
7080     { PREFIX_TABLE (PREFIX_VEX_6C) },
7081     { PREFIX_TABLE (PREFIX_VEX_6D) },
7082     { PREFIX_TABLE (PREFIX_VEX_6E) },
7083     { PREFIX_TABLE (PREFIX_VEX_6F) },
7084     /* 70 */
7085     { PREFIX_TABLE (PREFIX_VEX_70) },
7086     { REG_TABLE (REG_VEX_71) },
7087     { REG_TABLE (REG_VEX_72) },
7088     { REG_TABLE (REG_VEX_73) },
7089     { PREFIX_TABLE (PREFIX_VEX_74) },
7090     { PREFIX_TABLE (PREFIX_VEX_75) },
7091     { PREFIX_TABLE (PREFIX_VEX_76) },
7092     { PREFIX_TABLE (PREFIX_VEX_77) },
7093     /* 78 */
7094     { "(bad)",          { XX } },
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     { "(bad)",          { XX } },
7098     { PREFIX_TABLE (PREFIX_VEX_7C) },
7099     { PREFIX_TABLE (PREFIX_VEX_7D) },
7100     { PREFIX_TABLE (PREFIX_VEX_7E) },
7101     { PREFIX_TABLE (PREFIX_VEX_7F) },
7102     /* 80 */
7103     { "(bad)",          { XX } },
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { "(bad)",          { XX } },
7111     /* 88 */
7112     { "(bad)",          { XX } },
7113     { "(bad)",          { XX } },
7114     { "(bad)",          { XX } },
7115     { "(bad)",          { XX } },
7116     { "(bad)",          { XX } },
7117     { "(bad)",          { XX } },
7118     { "(bad)",          { XX } },
7119     { "(bad)",          { XX } },
7120     /* 90 */
7121     { "(bad)",          { XX } },
7122     { "(bad)",          { XX } },
7123     { "(bad)",          { XX } },
7124     { "(bad)",          { XX } },
7125     { "(bad)",          { XX } },
7126     { "(bad)",          { XX } },
7127     { "(bad)",          { XX } },
7128     { "(bad)",          { XX } },
7129     /* 98 */
7130     { "(bad)",          { XX } },
7131     { "(bad)",          { XX } },
7132     { "(bad)",          { XX } },
7133     { "(bad)",          { XX } },
7134     { "(bad)",          { XX } },
7135     { "(bad)",          { XX } },
7136     { "(bad)",          { XX } },
7137     { "(bad)",          { XX } },
7138     /* a0 */
7139     { "(bad)",          { XX } },
7140     { "(bad)",          { XX } },
7141     { "(bad)",          { XX } },
7142     { "(bad)",          { XX } },
7143     { "(bad)",          { XX } },
7144     { "(bad)",          { XX } },
7145     { "(bad)",          { XX } },
7146     { "(bad)",          { XX } },
7147     /* a8 */
7148     { "(bad)",          { XX } },
7149     { "(bad)",          { XX } },
7150     { "(bad)",          { XX } },
7151     { "(bad)",          { XX } },
7152     { "(bad)",          { XX } },
7153     { "(bad)",          { XX } },
7154     { REG_TABLE (REG_VEX_AE) },
7155     { "(bad)",          { XX } },
7156     /* b0 */
7157     { "(bad)",          { XX } },
7158     { "(bad)",          { XX } },
7159     { "(bad)",          { XX } },
7160     { "(bad)",          { XX } },
7161     { "(bad)",          { XX } },
7162     { "(bad)",          { XX } },
7163     { "(bad)",          { XX } },
7164     { "(bad)",          { XX } },
7165     /* b8 */
7166     { "(bad)",          { XX } },
7167     { "(bad)",          { XX } },
7168     { "(bad)",          { XX } },
7169     { "(bad)",          { XX } },
7170     { "(bad)",          { XX } },
7171     { "(bad)",          { XX } },
7172     { "(bad)",          { XX } },
7173     { "(bad)",          { XX } },
7174     /* c0 */
7175     { "(bad)",          { XX } },
7176     { "(bad)",          { XX } },
7177     { PREFIX_TABLE (PREFIX_VEX_C2) },
7178     { "(bad)",          { XX } },
7179     { PREFIX_TABLE (PREFIX_VEX_C4) },
7180     { PREFIX_TABLE (PREFIX_VEX_C5) },
7181     { "vshufpX",        { XM, Vex, EXx, Ib } },
7182     { "(bad)",          { XX } },
7183     /* c8 */
7184     { "(bad)",          { XX } },
7185     { "(bad)",          { XX } },
7186     { "(bad)",          { XX } },
7187     { "(bad)",          { XX } },
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     { "(bad)",          { XX } },
7192     /* d0 */
7193     { PREFIX_TABLE (PREFIX_VEX_D0) },
7194     { PREFIX_TABLE (PREFIX_VEX_D1) },
7195     { PREFIX_TABLE (PREFIX_VEX_D2) },
7196     { PREFIX_TABLE (PREFIX_VEX_D3) },
7197     { PREFIX_TABLE (PREFIX_VEX_D4) },
7198     { PREFIX_TABLE (PREFIX_VEX_D5) },
7199     { PREFIX_TABLE (PREFIX_VEX_D6) },
7200     { PREFIX_TABLE (PREFIX_VEX_D7) },
7201     /* d8 */
7202     { PREFIX_TABLE (PREFIX_VEX_D8) },
7203     { PREFIX_TABLE (PREFIX_VEX_D9) },
7204     { PREFIX_TABLE (PREFIX_VEX_DA) },
7205     { PREFIX_TABLE (PREFIX_VEX_DB) },
7206     { PREFIX_TABLE (PREFIX_VEX_DC) },
7207     { PREFIX_TABLE (PREFIX_VEX_DD) },
7208     { PREFIX_TABLE (PREFIX_VEX_DE) },
7209     { PREFIX_TABLE (PREFIX_VEX_DF) },
7210     /* e0 */
7211     { PREFIX_TABLE (PREFIX_VEX_E0) },
7212     { PREFIX_TABLE (PREFIX_VEX_E1) },
7213     { PREFIX_TABLE (PREFIX_VEX_E2) },
7214     { PREFIX_TABLE (PREFIX_VEX_E3) },
7215     { PREFIX_TABLE (PREFIX_VEX_E4) },
7216     { PREFIX_TABLE (PREFIX_VEX_E5) },
7217     { PREFIX_TABLE (PREFIX_VEX_E6) },
7218     { PREFIX_TABLE (PREFIX_VEX_E7) },
7219     /* e8 */
7220     { PREFIX_TABLE (PREFIX_VEX_E8) },
7221     { PREFIX_TABLE (PREFIX_VEX_E9) },
7222     { PREFIX_TABLE (PREFIX_VEX_EA) },
7223     { PREFIX_TABLE (PREFIX_VEX_EB) },
7224     { PREFIX_TABLE (PREFIX_VEX_EC) },
7225     { PREFIX_TABLE (PREFIX_VEX_ED) },
7226     { PREFIX_TABLE (PREFIX_VEX_EE) },
7227     { PREFIX_TABLE (PREFIX_VEX_EF) },
7228     /* f0 */
7229     { PREFIX_TABLE (PREFIX_VEX_F0) },
7230     { PREFIX_TABLE (PREFIX_VEX_F1) },
7231     { PREFIX_TABLE (PREFIX_VEX_F2) },
7232     { PREFIX_TABLE (PREFIX_VEX_F3) },
7233     { PREFIX_TABLE (PREFIX_VEX_F4) },
7234     { PREFIX_TABLE (PREFIX_VEX_F5) },
7235     { PREFIX_TABLE (PREFIX_VEX_F6) },
7236     { PREFIX_TABLE (PREFIX_VEX_F7) },
7237     /* f8 */
7238     { PREFIX_TABLE (PREFIX_VEX_F8) },
7239     { PREFIX_TABLE (PREFIX_VEX_F9) },
7240     { PREFIX_TABLE (PREFIX_VEX_FA) },
7241     { PREFIX_TABLE (PREFIX_VEX_FB) },
7242     { PREFIX_TABLE (PREFIX_VEX_FC) },
7243     { PREFIX_TABLE (PREFIX_VEX_FD) },
7244     { PREFIX_TABLE (PREFIX_VEX_FE) },
7245     { "(bad)",          { XX } },
7246   },
7247   /* VEX_0F38 */
7248   {
7249     /* 00 */
7250     { PREFIX_TABLE (PREFIX_VEX_3800) },
7251     { PREFIX_TABLE (PREFIX_VEX_3801) },
7252     { PREFIX_TABLE (PREFIX_VEX_3802) },
7253     { PREFIX_TABLE (PREFIX_VEX_3803) },
7254     { PREFIX_TABLE (PREFIX_VEX_3804) },
7255     { PREFIX_TABLE (PREFIX_VEX_3805) },
7256     { PREFIX_TABLE (PREFIX_VEX_3806) },
7257     { PREFIX_TABLE (PREFIX_VEX_3807) },
7258     /* 08 */
7259     { PREFIX_TABLE (PREFIX_VEX_3808) },
7260     { PREFIX_TABLE (PREFIX_VEX_3809) },
7261     { PREFIX_TABLE (PREFIX_VEX_380A) },
7262     { PREFIX_TABLE (PREFIX_VEX_380B) },
7263     { PREFIX_TABLE (PREFIX_VEX_380C) },
7264     { PREFIX_TABLE (PREFIX_VEX_380D) },
7265     { PREFIX_TABLE (PREFIX_VEX_380E) },
7266     { PREFIX_TABLE (PREFIX_VEX_380F) },
7267     /* 10 */
7268     { "(bad)",          { XX } },
7269     { "(bad)",          { XX } },
7270     { "(bad)",          { XX } },
7271     { "(bad)",          { XX } },
7272     { "(bad)",          { XX } },
7273     { "(bad)",          { XX } },
7274     { "(bad)",          { XX } },
7275     { PREFIX_TABLE (PREFIX_VEX_3817) },
7276     /* 18 */
7277     { PREFIX_TABLE (PREFIX_VEX_3818) },
7278     { PREFIX_TABLE (PREFIX_VEX_3819) },
7279     { PREFIX_TABLE (PREFIX_VEX_381A) },
7280     { "(bad)",          { XX } },
7281     { PREFIX_TABLE (PREFIX_VEX_381C) },
7282     { PREFIX_TABLE (PREFIX_VEX_381D) },
7283     { PREFIX_TABLE (PREFIX_VEX_381E) },
7284     { "(bad)",          { XX } },
7285     /* 20 */
7286     { PREFIX_TABLE (PREFIX_VEX_3820) },
7287     { PREFIX_TABLE (PREFIX_VEX_3821) },
7288     { PREFIX_TABLE (PREFIX_VEX_3822) },
7289     { PREFIX_TABLE (PREFIX_VEX_3823) },
7290     { PREFIX_TABLE (PREFIX_VEX_3824) },
7291     { PREFIX_TABLE (PREFIX_VEX_3825) },
7292     { "(bad)",          { XX } },
7293     { "(bad)",          { XX } },
7294     /* 28 */
7295     { PREFIX_TABLE (PREFIX_VEX_3828) },
7296     { PREFIX_TABLE (PREFIX_VEX_3829) },
7297     { PREFIX_TABLE (PREFIX_VEX_382A) },
7298     { PREFIX_TABLE (PREFIX_VEX_382B) },
7299     { PREFIX_TABLE (PREFIX_VEX_382C) },
7300     { PREFIX_TABLE (PREFIX_VEX_382D) },
7301     { PREFIX_TABLE (PREFIX_VEX_382E) },
7302     { PREFIX_TABLE (PREFIX_VEX_382F) },
7303     /* 30 */
7304     { PREFIX_TABLE (PREFIX_VEX_3830) },
7305     { PREFIX_TABLE (PREFIX_VEX_3831) },
7306     { PREFIX_TABLE (PREFIX_VEX_3832) },
7307     { PREFIX_TABLE (PREFIX_VEX_3833) },
7308     { PREFIX_TABLE (PREFIX_VEX_3834) },
7309     { PREFIX_TABLE (PREFIX_VEX_3835) },
7310     { "(bad)",          { XX } },
7311     { PREFIX_TABLE (PREFIX_VEX_3837) },
7312     /* 38 */
7313     { PREFIX_TABLE (PREFIX_VEX_3838) },
7314     { PREFIX_TABLE (PREFIX_VEX_3839) },
7315     { PREFIX_TABLE (PREFIX_VEX_383A) },
7316     { PREFIX_TABLE (PREFIX_VEX_383B) },
7317     { PREFIX_TABLE (PREFIX_VEX_383C) },
7318     { PREFIX_TABLE (PREFIX_VEX_383D) },
7319     { PREFIX_TABLE (PREFIX_VEX_383E) },
7320     { PREFIX_TABLE (PREFIX_VEX_383F) },
7321     /* 40 */
7322     { PREFIX_TABLE (PREFIX_VEX_3840) },
7323     { PREFIX_TABLE (PREFIX_VEX_3841) },
7324     { "(bad)",          { XX } },
7325     { "(bad)",          { XX } },
7326     { "(bad)",          { XX } },
7327     { "(bad)",          { XX } },
7328     { "(bad)",          { XX } },
7329     { "(bad)",          { XX } },
7330     /* 48 */
7331     { "(bad)",          { XX } },
7332     { "(bad)",          { XX } },
7333     { "(bad)",          { XX } },
7334     { "(bad)",          { XX } },
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     /* 50 */
7340     { "(bad)",          { XX } },
7341     { "(bad)",          { XX } },
7342     { "(bad)",          { XX } },
7343     { "(bad)",          { XX } },
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     /* 58 */
7349     { "(bad)",          { XX } },
7350     { "(bad)",          { XX } },
7351     { "(bad)",          { XX } },
7352     { "(bad)",          { XX } },
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     /* 60 */
7358     { "(bad)",          { XX } },
7359     { "(bad)",          { XX } },
7360     { "(bad)",          { XX } },
7361     { "(bad)",          { XX } },
7362     { "(bad)",          { XX } },
7363     { "(bad)",          { XX } },
7364     { "(bad)",          { XX } },
7365     { "(bad)",          { XX } },
7366     /* 68 */
7367     { "(bad)",          { XX } },
7368     { "(bad)",          { XX } },
7369     { "(bad)",          { XX } },
7370     { "(bad)",          { XX } },
7371     { "(bad)",          { XX } },
7372     { "(bad)",          { XX } },
7373     { "(bad)",          { XX } },
7374     { "(bad)",          { XX } },
7375     /* 70 */
7376     { "(bad)",          { XX } },
7377     { "(bad)",          { XX } },
7378     { "(bad)",          { XX } },
7379     { "(bad)",          { XX } },
7380     { "(bad)",          { XX } },
7381     { "(bad)",          { XX } },
7382     { "(bad)",          { XX } },
7383     { "(bad)",          { XX } },
7384     /* 78 */
7385     { "(bad)",          { XX } },
7386     { "(bad)",          { XX } },
7387     { "(bad)",          { XX } },
7388     { "(bad)",          { XX } },
7389     { "(bad)",          { XX } },
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     /* 80 */
7394     { "(bad)",          { XX } },
7395     { "(bad)",          { XX } },
7396     { "(bad)",          { XX } },
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     /* 88 */
7403     { "(bad)",          { XX } },
7404     { "(bad)",          { XX } },
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     /* 90 */
7412     { "(bad)",          { XX } },
7413     { "(bad)",          { XX } },
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     /* 98 */
7421     { "(bad)",          { XX } },
7422     { "(bad)",          { XX } },
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     /* a0 */
7430     { "(bad)",          { XX } },
7431     { "(bad)",          { XX } },
7432     { "(bad)",          { XX } },
7433     { "(bad)",          { XX } },
7434     { "(bad)",          { XX } },
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     /* a8 */
7439     { "(bad)",          { XX } },
7440     { "(bad)",          { XX } },
7441     { "(bad)",          { XX } },
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     /* b0 */
7448     { "(bad)",          { XX } },
7449     { "(bad)",          { XX } },
7450     { "(bad)",          { XX } },
7451     { "(bad)",          { XX } },
7452     { "(bad)",          { XX } },
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     /* b8 */
7457     { "(bad)",          { XX } },
7458     { "(bad)",          { XX } },
7459     { "(bad)",          { XX } },
7460     { "(bad)",          { XX } },
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     /* c0 */
7466     { "(bad)",          { XX } },
7467     { "(bad)",          { XX } },
7468     { "(bad)",          { XX } },
7469     { "(bad)",          { XX } },
7470     { "(bad)",          { XX } },
7471     { "(bad)",          { XX } },
7472     { "(bad)",          { XX } },
7473     { "(bad)",          { XX } },
7474     /* c8 */
7475     { "(bad)",          { XX } },
7476     { "(bad)",          { XX } },
7477     { "(bad)",          { XX } },
7478     { "(bad)",          { XX } },
7479     { "(bad)",          { XX } },
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     /* d0 */
7484     { "(bad)",          { XX } },
7485     { "(bad)",          { XX } },
7486     { "(bad)",          { XX } },
7487     { "(bad)",          { XX } },
7488     { "(bad)",          { XX } },
7489     { "(bad)",          { XX } },
7490     { "(bad)",          { XX } },
7491     { "(bad)",          { XX } },
7492     /* d8 */
7493     { "(bad)",          { XX } },
7494     { "(bad)",          { XX } },
7495     { "(bad)",          { XX } },
7496     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7497     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7498     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7499     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7500     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7501     /* e0 */
7502     { "(bad)",          { XX } },
7503     { "(bad)",          { XX } },
7504     { "(bad)",          { XX } },
7505     { "(bad)",          { XX } },
7506     { "(bad)",          { XX } },
7507     { "(bad)",          { XX } },
7508     { "(bad)",          { XX } },
7509     { "(bad)",          { XX } },
7510     /* e8 */
7511     { "(bad)",          { XX } },
7512     { "(bad)",          { XX } },
7513     { "(bad)",          { XX } },
7514     { "(bad)",          { XX } },
7515     { "(bad)",          { XX } },
7516     { "(bad)",          { XX } },
7517     { "(bad)",          { XX } },
7518     { "(bad)",          { XX } },
7519     /* f0 */
7520     { "(bad)",          { XX } },
7521     { "(bad)",          { XX } },
7522     { "(bad)",          { XX } },
7523     { "(bad)",          { XX } },
7524     { "(bad)",          { XX } },
7525     { "(bad)",          { XX } },
7526     { "(bad)",          { XX } },
7527     { "(bad)",          { XX } },
7528     /* f8 */
7529     { "(bad)",          { XX } },
7530     { "(bad)",          { XX } },
7531     { "(bad)",          { XX } },
7532     { "(bad)",          { XX } },
7533     { "(bad)",          { XX } },
7534     { "(bad)",          { XX } },
7535     { "(bad)",          { XX } },
7536     { "(bad)",          { XX } },
7537   },
7538   /* VEX_0F3A */
7539   {
7540     /* 00 */
7541     { "(bad)",          { XX } },
7542     { "(bad)",          { XX } },
7543     { "(bad)",          { XX } },
7544     { "(bad)",          { XX } },
7545     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7546     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7547     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7548     { "(bad)",          { XX } },
7549     /* 08 */
7550     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7551     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7552     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7553     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7554     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7555     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7556     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7557     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7558     /* 10 */
7559     { "(bad)",          { XX } },
7560     { "(bad)",          { XX } },
7561     { "(bad)",          { XX } },
7562     { "(bad)",          { XX } },
7563     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7564     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7565     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7566     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7567     /* 18 */
7568     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7569     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7570     { "(bad)",          { XX } },
7571     { "(bad)",          { XX } },
7572     { "(bad)",          { XX } },
7573     { "(bad)",          { XX } },
7574     { "(bad)",          { XX } },
7575     { "(bad)",          { XX } },
7576     /* 20 */
7577     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7578     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7579     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7580     { "(bad)",          { XX } },
7581     { "(bad)",          { XX } },
7582     { "(bad)",          { XX } },
7583     { "(bad)",          { XX } },
7584     { "(bad)",          { XX } },
7585     /* 28 */
7586     { "(bad)",          { XX } },
7587     { "(bad)",          { XX } },
7588     { "(bad)",          { XX } },
7589     { "(bad)",          { XX } },
7590     { "(bad)",          { XX } },
7591     { "(bad)",          { XX } },
7592     { "(bad)",          { XX } },
7593     { "(bad)",          { XX } },
7594     /* 30 */
7595     { "(bad)",          { XX } },
7596     { "(bad)",          { XX } },
7597     { "(bad)",          { XX } },
7598     { "(bad)",          { XX } },
7599     { "(bad)",          { XX } },
7600     { "(bad)",          { XX } },
7601     { "(bad)",          { XX } },
7602     { "(bad)",          { XX } },
7603     /* 38 */
7604     { "(bad)",          { XX } },
7605     { "(bad)",          { XX } },
7606     { "(bad)",          { XX } },
7607     { "(bad)",          { XX } },
7608     { "(bad)",          { XX } },
7609     { "(bad)",          { XX } },
7610     { "(bad)",          { XX } },
7611     { "(bad)",          { XX } },
7612     /* 40 */
7613     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7614     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7615     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7616     { "(bad)",          { XX } },
7617     { "(bad)",          { XX } },
7618     { "(bad)",          { XX } },
7619     { "(bad)",          { XX } },
7620     { "(bad)",          { XX } },
7621     /* 48 */
7622     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7623     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7624     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7625     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7626     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7627     { "(bad)",          { XX } },
7628     { "(bad)",          { XX } },
7629     { "(bad)",          { XX } },
7630     /* 50 */
7631     { "(bad)",          { XX } },
7632     { "(bad)",          { XX } },
7633     { "(bad)",          { XX } },
7634     { "(bad)",          { XX } },
7635     { "(bad)",          { XX } },
7636     { "(bad)",          { XX } },
7637     { "(bad)",          { XX } },
7638     { "(bad)",          { XX } },
7639     /* 58 */
7640     { "(bad)",          { XX } },
7641     { "(bad)",          { XX } },
7642     { "(bad)",          { XX } },
7643     { "(bad)",          { XX } },
7644     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7645     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7646     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7647     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7648     /* 60 */
7649     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7650     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7651     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7652     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     /* 68 */
7658     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7659     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7660     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7661     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7662     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7663     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7664     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7665     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7666     /* 70 */
7667     { "(bad)",          { XX } },
7668     { "(bad)",          { XX } },
7669     { "(bad)",          { XX } },
7670     { "(bad)",          { XX } },
7671     { "(bad)",          { XX } },
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     /* 78 */
7676     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7677     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7678     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7679     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7680     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7681     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7682     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7683     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7684     /* 80 */
7685     { "(bad)",          { XX } },
7686     { "(bad)",          { XX } },
7687     { "(bad)",          { XX } },
7688     { "(bad)",          { XX } },
7689     { "(bad)",          { XX } },
7690     { "(bad)",          { XX } },
7691     { "(bad)",          { XX } },
7692     { "(bad)",          { XX } },
7693     /* 88 */
7694     { "(bad)",          { XX } },
7695     { "(bad)",          { XX } },
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     /* 90 */
7703     { "(bad)",          { XX } },
7704     { "(bad)",          { XX } },
7705     { "(bad)",          { XX } },
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     /* 98 */
7712     { "(bad)",          { XX } },
7713     { "(bad)",          { XX } },
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     /* a0 */
7721     { "(bad)",          { XX } },
7722     { "(bad)",          { XX } },
7723     { "(bad)",          { XX } },
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     /* a8 */
7730     { "(bad)",          { XX } },
7731     { "(bad)",          { XX } },
7732     { "(bad)",          { XX } },
7733     { "(bad)",          { XX } },
7734     { "(bad)",          { XX } },
7735     { "(bad)",          { XX } },
7736     { "(bad)",          { XX } },
7737     { "(bad)",          { XX } },
7738     /* b0 */
7739     { "(bad)",          { XX } },
7740     { "(bad)",          { XX } },
7741     { "(bad)",          { XX } },
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     /* b8 */
7748     { "(bad)",          { XX } },
7749     { "(bad)",          { XX } },
7750     { "(bad)",          { XX } },
7751     { "(bad)",          { XX } },
7752     { "(bad)",          { XX } },
7753     { "(bad)",          { XX } },
7754     { "(bad)",          { XX } },
7755     { "(bad)",          { XX } },
7756     /* c0 */
7757     { "(bad)",          { XX } },
7758     { "(bad)",          { XX } },
7759     { "(bad)",          { XX } },
7760     { "(bad)",          { XX } },
7761     { "(bad)",          { XX } },
7762     { "(bad)",          { XX } },
7763     { "(bad)",          { XX } },
7764     { "(bad)",          { XX } },
7765     /* c8 */
7766     { "(bad)",          { XX } },
7767     { "(bad)",          { XX } },
7768     { "(bad)",          { XX } },
7769     { "(bad)",          { XX } },
7770     { "(bad)",          { XX } },
7771     { "(bad)",          { XX } },
7772     { "(bad)",          { XX } },
7773     { "(bad)",          { XX } },
7774     /* d0 */
7775     { "(bad)",          { XX } },
7776     { "(bad)",          { XX } },
7777     { "(bad)",          { XX } },
7778     { "(bad)",          { XX } },
7779     { "(bad)",          { XX } },
7780     { "(bad)",          { XX } },
7781     { "(bad)",          { XX } },
7782     { "(bad)",          { XX } },
7783     /* d8 */
7784     { "(bad)",          { XX } },
7785     { "(bad)",          { XX } },
7786     { "(bad)",          { XX } },
7787     { "(bad)",          { XX } },
7788     { "(bad)",          { XX } },
7789     { "(bad)",          { XX } },
7790     { "(bad)",          { XX } },
7791     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7792     /* e0 */
7793     { "(bad)",          { XX } },
7794     { "(bad)",          { XX } },
7795     { "(bad)",          { XX } },
7796     { "(bad)",          { XX } },
7797     { "(bad)",          { XX } },
7798     { "(bad)",          { XX } },
7799     { "(bad)",          { XX } },
7800     { "(bad)",          { XX } },
7801     /* e8 */
7802     { "(bad)",          { XX } },
7803     { "(bad)",          { XX } },
7804     { "(bad)",          { XX } },
7805     { "(bad)",          { XX } },
7806     { "(bad)",          { XX } },
7807     { "(bad)",          { XX } },
7808     { "(bad)",          { XX } },
7809     { "(bad)",          { XX } },
7810     /* f0 */
7811     { "(bad)",          { XX } },
7812     { "(bad)",          { XX } },
7813     { "(bad)",          { XX } },
7814     { "(bad)",          { XX } },
7815     { "(bad)",          { XX } },
7816     { "(bad)",          { XX } },
7817     { "(bad)",          { XX } },
7818     { "(bad)",          { XX } },
7819     /* f8 */
7820     { "(bad)",          { XX } },
7821     { "(bad)",          { XX } },
7822     { "(bad)",          { XX } },
7823     { "(bad)",          { XX } },
7824     { "(bad)",          { XX } },
7825     { "(bad)",          { XX } },
7826     { "(bad)",          { XX } },
7827     { "(bad)",          { XX } },
7828   },
7829 };
7830
7831 static const struct dis386 vex_len_table[][2] = {
7832   /* VEX_LEN_10_P_1 */
7833   {
7834     { "vmovss",         { XMVex, Vex128, EXd } },
7835     { "(bad)",          { XX } },
7836   },
7837
7838   /* VEX_LEN_10_P_3 */
7839   {
7840     { "vmovsd",         { XMVex, Vex128, EXq } },
7841     { "(bad)",          { XX } },
7842   },
7843
7844   /* VEX_LEN_11_P_1 */
7845   {
7846     { "vmovss",         { EXdVex, Vex128, XM } },
7847     { "(bad)",          { XX } },
7848   },
7849
7850   /* VEX_LEN_11_P_3 */
7851   {
7852     { "vmovsd",         { EXqVex, Vex128, XM } },
7853     { "(bad)",          { XX } },
7854   },
7855
7856   /* VEX_LEN_12_P_0_M_0 */
7857   {
7858     { "vmovlps",        { XM, Vex128, EXq } },
7859     { "(bad)",          { XX } },
7860   },
7861
7862   /* VEX_LEN_12_P_0_M_1 */
7863   {
7864     { "vmovhlps",       { XM, Vex128, EXq } },
7865     { "(bad)",          { XX } },
7866   },
7867
7868   /* VEX_LEN_12_P_2 */
7869   {
7870     { "vmovlpd",        { XM, Vex128, EXq } },
7871     { "(bad)",          { XX } },
7872   },
7873
7874   /* VEX_LEN_13_M_0 */
7875   {
7876     { "vmovlpX",        { EXq, XM } },
7877     { "(bad)",          { XX } },
7878   },
7879
7880   /* VEX_LEN_16_P_0_M_0 */
7881   {
7882     { "vmovhps",        { XM, Vex128, EXq } },
7883     { "(bad)",          { XX } },
7884   },
7885
7886   /* VEX_LEN_16_P_0_M_1 */
7887   {
7888     { "vmovlhps",       { XM, Vex128, EXq } },
7889     { "(bad)",          { XX } },
7890   },
7891
7892   /* VEX_LEN_16_P_2 */
7893   {
7894     { "vmovhpd",        { XM, Vex128, EXq } },
7895     { "(bad)",          { XX } },
7896   },
7897
7898   /* VEX_LEN_17_M_0 */
7899   {
7900     { "vmovhpX",        { EXq, XM } },
7901     { "(bad)",          { XX } },
7902   },
7903
7904   /* VEX_LEN_2A_P_1 */
7905   {
7906     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7907     { "(bad)",          { XX } },
7908   },
7909
7910   /* VEX_LEN_2A_P_3 */
7911   {
7912     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7913     { "(bad)",          { XX } },
7914   },
7915
7916   /* VEX_LEN_2B_M_0 */
7917   {
7918     { "vmovntpX",       { Mx, XM } },
7919     { "(bad)",          { XX } },
7920   },
7921
7922   /* VEX_LEN_2C_P_1 */
7923   {
7924     { "vcvttss2siY",    { Gv, EXd } },
7925     { "(bad)",          { XX } },
7926   },
7927
7928   /* VEX_LEN_2C_P_3 */
7929   {
7930     { "vcvttsd2siY",    { Gv, EXq } },
7931     { "(bad)",          { XX } },
7932   },
7933
7934   /* VEX_LEN_2D_P_1 */
7935   {
7936     { "vcvtss2siY",     { Gv, EXd } },
7937     { "(bad)",          { XX } },
7938   },
7939
7940   /* VEX_LEN_2D_P_3 */
7941   {
7942     { "vcvtsd2siY",     { Gv, EXq } },
7943     { "(bad)",          { XX } },
7944   },
7945
7946   /* VEX_LEN_2E_P_0 */
7947   {
7948     { "vucomiss",       { XM, EXd } },
7949     { "(bad)",          { XX } },
7950   },
7951
7952   /* VEX_LEN_2E_P_2 */
7953   {
7954     { "vucomisd",       { XM, EXq } },
7955     { "(bad)",          { XX } },
7956   },
7957
7958   /* VEX_LEN_2F_P_0 */
7959   {
7960     { "vcomiss",        { XM, EXd } },
7961     { "(bad)",          { XX } },
7962   },
7963
7964   /* VEX_LEN_2F_P_2 */
7965   {
7966     { "vcomisd",        { XM, EXq } },
7967     { "(bad)",          { XX } },
7968   },
7969
7970   /* VEX_LEN_51_P_1 */
7971   {
7972     { "vsqrtss",        { XM, Vex128, EXd } },
7973     { "(bad)",          { XX } },
7974   },
7975
7976   /* VEX_LEN_51_P_3 */
7977   {
7978     { "vsqrtsd",        { XM, Vex128, EXq } },
7979     { "(bad)",          { XX } },
7980   },
7981
7982   /* VEX_LEN_52_P_1 */
7983   {
7984     { "vrsqrtss",       { XM, Vex128, EXd } },
7985     { "(bad)",          { XX } },
7986   },
7987
7988   /* VEX_LEN_53_P_1 */
7989   {
7990     { "vrcpss",         { XM, Vex128, EXd } },
7991     { "(bad)",          { XX } },
7992   },
7993
7994   /* VEX_LEN_58_P_1 */
7995   {
7996     { "vaddss",         { XM, Vex128, EXd } },
7997     { "(bad)",          { XX } },
7998   },
7999
8000   /* VEX_LEN_58_P_3 */
8001   {
8002     { "vaddsd",         { XM, Vex128, EXq } },
8003     { "(bad)",          { XX } },
8004   },
8005
8006   /* VEX_LEN_59_P_1 */
8007   {
8008     { "vmulss",         { XM, Vex128, EXd } },
8009     { "(bad)",          { XX } },
8010   },
8011
8012   /* VEX_LEN_59_P_3 */
8013   {
8014     { "vmulsd",         { XM, Vex128, EXq } },
8015     { "(bad)",          { XX } },
8016   },
8017
8018   /* VEX_LEN_5A_P_1 */
8019   {
8020     { "vcvtss2sd",      { XM, Vex128, EXd } },
8021     { "(bad)",          { XX } },
8022   },
8023
8024   /* VEX_LEN_5A_P_3 */
8025   {
8026     { "vcvtsd2ss",      { XM, Vex128, EXq } },
8027     { "(bad)",          { XX } },
8028   },
8029
8030   /* VEX_LEN_5C_P_1 */
8031   {
8032     { "vsubss",         { XM, Vex128, EXd } },
8033     { "(bad)",          { XX } },
8034   },
8035
8036   /* VEX_LEN_5C_P_3 */
8037   {
8038     { "vsubsd",         { XM, Vex128, EXq } },
8039     { "(bad)",          { XX } },
8040   },
8041
8042   /* VEX_LEN_5D_P_1 */
8043   {
8044     { "vminss",         { XM, Vex128, EXd } },
8045     { "(bad)",          { XX } },
8046   },
8047
8048   /* VEX_LEN_5D_P_3 */
8049   {
8050     { "vminsd",         { XM, Vex128, EXq } },
8051     { "(bad)",          { XX } },
8052   },
8053
8054   /* VEX_LEN_5E_P_1 */
8055   {
8056     { "vdivss",         { XM, Vex128, EXd } },
8057     { "(bad)",          { XX } },
8058   },
8059
8060   /* VEX_LEN_5E_P_3 */
8061   {
8062     { "vdivsd",         { XM, Vex128, EXq } },
8063     { "(bad)",          { XX } },
8064   },
8065
8066   /* VEX_LEN_5F_P_1 */
8067   {
8068     { "vmaxss",         { XM, Vex128, EXd } },
8069     { "(bad)",          { XX } },
8070   },
8071
8072   /* VEX_LEN_5F_P_3 */
8073   {
8074     { "vmaxsd",         { XM, Vex128, EXq } },
8075     { "(bad)",          { XX } },
8076   },
8077
8078   /* VEX_LEN_60_P_2 */
8079   {
8080     { "vpunpcklbw",     { XM, Vex128, EXx } },
8081     { "(bad)",          { XX } },
8082   },
8083
8084   /* VEX_LEN_61_P_2 */
8085   {
8086     { "vpunpcklwd",     { XM, Vex128, EXx } },
8087     { "(bad)",          { XX } },
8088   },
8089
8090   /* VEX_LEN_62_P_2 */
8091   {
8092     { "vpunpckldq",     { XM, Vex128, EXx } },
8093     { "(bad)",          { XX } },
8094   },
8095
8096   /* VEX_LEN_63_P_2 */
8097   {
8098     { "vpacksswb",      { XM, Vex128, EXx } },
8099     { "(bad)",          { XX } },
8100   },
8101
8102   /* VEX_LEN_64_P_2 */
8103   {
8104     { "vpcmpgtb",       { XM, Vex128, EXx } },
8105     { "(bad)",          { XX } },
8106   },
8107
8108   /* VEX_LEN_65_P_2 */
8109   {
8110     { "vpcmpgtw",       { XM, Vex128, EXx } },
8111     { "(bad)",          { XX } },
8112   },
8113
8114   /* VEX_LEN_66_P_2 */
8115   {
8116     { "vpcmpgtd",       { XM, Vex128, EXx } },
8117     { "(bad)",          { XX } },
8118   },
8119
8120   /* VEX_LEN_67_P_2 */
8121   {
8122     { "vpackuswb",      { XM, Vex128, EXx } },
8123     { "(bad)",          { XX } },
8124   },
8125
8126   /* VEX_LEN_68_P_2 */
8127   {
8128     { "vpunpckhbw",     { XM, Vex128, EXx } },
8129     { "(bad)",          { XX } },
8130   },
8131
8132   /* VEX_LEN_69_P_2 */
8133   {
8134     { "vpunpckhwd",     { XM, Vex128, EXx } },
8135     { "(bad)",          { XX } },
8136   },
8137
8138   /* VEX_LEN_6A_P_2 */
8139   {
8140     { "vpunpckhdq",     { XM, Vex128, EXx } },
8141     { "(bad)",          { XX } },
8142   },
8143
8144   /* VEX_LEN_6B_P_2 */
8145   {
8146     { "vpackssdw",      { XM, Vex128, EXx } },
8147     { "(bad)",          { XX } },
8148   },
8149
8150   /* VEX_LEN_6C_P_2 */
8151   {
8152     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8153     { "(bad)",          { XX } },
8154   },
8155
8156   /* VEX_LEN_6D_P_2 */
8157   {
8158     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8159     { "(bad)",          { XX } },
8160   },
8161
8162   /* VEX_LEN_6E_P_2 */
8163   {
8164     { "vmovK",          { XM, Edq } },
8165     { "(bad)",          { XX } },
8166   },
8167
8168   /* VEX_LEN_70_P_1 */
8169   {
8170     { "vpshufhw",       { XM, EXx, Ib } },
8171     { "(bad)",          { XX } },
8172   },
8173
8174   /* VEX_LEN_70_P_2 */
8175   {
8176     { "vpshufd",        { XM, EXx, Ib } },
8177     { "(bad)",          { XX } },
8178   },
8179
8180   /* VEX_LEN_70_P_3 */
8181   {
8182     { "vpshuflw",       { XM, EXx, Ib } },
8183     { "(bad)",          { XX } },
8184   },
8185
8186   /* VEX_LEN_71_R_2_P_2 */
8187   {
8188     { "vpsrlw",         { Vex128, XS, Ib } },
8189     { "(bad)",          { XX } },
8190   },
8191
8192   /* VEX_LEN_71_R_4_P_2 */
8193   {
8194     { "vpsraw",         { Vex128, XS, Ib } },
8195     { "(bad)",          { XX } },
8196   },
8197
8198   /* VEX_LEN_71_R_6_P_2 */
8199   {
8200     { "vpsllw",         { Vex128, XS, Ib } },
8201     { "(bad)",          { XX } },
8202   },
8203
8204   /* VEX_LEN_72_R_2_P_2 */
8205   {
8206     { "vpsrld",         { Vex128, XS, Ib } },
8207     { "(bad)",          { XX } },
8208   },
8209
8210   /* VEX_LEN_72_R_4_P_2 */
8211   {
8212     { "vpsrad",         { Vex128, XS, Ib } },
8213     { "(bad)",          { XX } },
8214   },
8215
8216   /* VEX_LEN_72_R_6_P_2 */
8217   {
8218     { "vpslld",         { Vex128, XS, Ib } },
8219     { "(bad)",          { XX } },
8220   },
8221
8222   /* VEX_LEN_73_R_2_P_2 */
8223   {
8224     { "vpsrlq",         { Vex128, XS, Ib } },
8225     { "(bad)",          { XX } },
8226   },
8227
8228   /* VEX_LEN_73_R_3_P_2 */
8229   {
8230     { "vpsrldq",        { Vex128, XS, Ib } },
8231     { "(bad)",          { XX } },
8232   },
8233
8234   /* VEX_LEN_73_R_6_P_2 */
8235   {
8236     { "vpsllq",         { Vex128, XS, Ib } },
8237     { "(bad)",          { XX } },
8238   },
8239
8240   /* VEX_LEN_73_R_7_P_2 */
8241   {
8242     { "vpslldq",        { Vex128, XS, Ib } },
8243     { "(bad)",          { XX } },
8244   },
8245
8246   /* VEX_LEN_74_P_2 */
8247   {
8248     { "vpcmpeqb",       { XM, Vex128, EXx } },
8249     { "(bad)",          { XX } },
8250   },
8251
8252   /* VEX_LEN_75_P_2 */
8253   {
8254     { "vpcmpeqw",       { XM, Vex128, EXx } },
8255     { "(bad)",          { XX } },
8256   },
8257
8258   /* VEX_LEN_76_P_2 */
8259   {
8260     { "vpcmpeqd",       { XM, Vex128, EXx } },
8261     { "(bad)",          { XX } },
8262   },
8263
8264   /* VEX_LEN_7E_P_1 */
8265   {
8266     { "vmovq",          { XM, EXq } },
8267     { "(bad)",          { XX } },
8268   },
8269
8270   /* VEX_LEN_7E_P_2 */
8271   {
8272     { "vmovK",          { Edq, XM } },
8273     { "(bad)",          { XX } },
8274   },
8275
8276   /* VEX_LEN_AE_R_2_M0 */
8277   {
8278     { "vldmxcsr",       { Md } },
8279     { "(bad)",          { XX } },
8280   },
8281
8282   /* VEX_LEN_AE_R_3_M0 */
8283   {
8284     { "vstmxcsr",       { Md } },
8285     { "(bad)",          { XX } },
8286   },
8287
8288   /* VEX_LEN_C2_P_1 */
8289   {
8290     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8291     { "(bad)",          { XX } },
8292   },
8293
8294   /* VEX_LEN_C2_P_3 */
8295   {
8296     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8297     { "(bad)",          { XX } },
8298   },
8299
8300   /* VEX_LEN_C4_P_2 */
8301   {
8302     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8303     { "(bad)",          { XX } },
8304   },
8305
8306   /* VEX_LEN_C5_P_2 */
8307   {
8308     { "vpextrw",        { Gdq, XS, Ib } },
8309     { "(bad)",          { XX } },
8310   },
8311
8312   /* VEX_LEN_D1_P_2 */
8313   {
8314     { "vpsrlw",         { XM, Vex128, EXx } },
8315     { "(bad)",          { XX } },
8316   },
8317
8318   /* VEX_LEN_D2_P_2 */
8319   {
8320     { "vpsrld",         { XM, Vex128, EXx } },
8321     { "(bad)",          { XX } },
8322   },
8323
8324   /* VEX_LEN_D3_P_2 */
8325   {
8326     { "vpsrlq",         { XM, Vex128, EXx } },
8327     { "(bad)",          { XX } },
8328   },
8329
8330   /* VEX_LEN_D4_P_2 */
8331   {
8332     { "vpaddq",         { XM, Vex128, EXx } },
8333     { "(bad)",          { XX } },
8334   },
8335
8336   /* VEX_LEN_D5_P_2 */
8337   {
8338     { "vpmullw",        { XM, Vex128, EXx } },
8339     { "(bad)",          { XX } },
8340   },
8341
8342   /* VEX_LEN_D6_P_2 */
8343   {
8344     { "vmovq",          { EXqS, XM } },
8345     { "(bad)",          { XX } },
8346   },
8347
8348   /* VEX_LEN_D7_P_2_M_1 */
8349   {
8350     { "vpmovmskb",      { Gdq, XS } },
8351     { "(bad)",          { XX } },
8352   },
8353
8354   /* VEX_LEN_D8_P_2 */
8355   {
8356     { "vpsubusb",       { XM, Vex128, EXx } },
8357     { "(bad)",          { XX } },
8358   },
8359
8360   /* VEX_LEN_D9_P_2 */
8361   {
8362     { "vpsubusw",       { XM, Vex128, EXx } },
8363     { "(bad)",          { XX } },
8364   },
8365
8366   /* VEX_LEN_DA_P_2 */
8367   {
8368     { "vpminub",        { XM, Vex128, EXx } },
8369     { "(bad)",          { XX } },
8370   },
8371
8372   /* VEX_LEN_DB_P_2 */
8373   {
8374     { "vpand",          { XM, Vex128, EXx } },
8375     { "(bad)",          { XX } },
8376   },
8377
8378   /* VEX_LEN_DC_P_2 */
8379   {
8380     { "vpaddusb",       { XM, Vex128, EXx } },
8381     { "(bad)",          { XX } },
8382   },
8383
8384   /* VEX_LEN_DD_P_2 */
8385   {
8386     { "vpaddusw",       { XM, Vex128, EXx } },
8387     { "(bad)",          { XX } },
8388   },
8389
8390   /* VEX_LEN_DE_P_2 */
8391   {
8392     { "vpmaxub",        { XM, Vex128, EXx } },
8393     { "(bad)",          { XX } },
8394   },
8395
8396   /* VEX_LEN_DF_P_2 */
8397   {
8398     { "vpandn",         { XM, Vex128, EXx } },
8399     { "(bad)",          { XX } },
8400   },
8401
8402   /* VEX_LEN_E0_P_2 */
8403   {
8404     { "vpavgb",         { XM, Vex128, EXx } },
8405     { "(bad)",          { XX } },
8406   },
8407
8408   /* VEX_LEN_E1_P_2 */
8409   {
8410     { "vpsraw",         { XM, Vex128, EXx } },
8411     { "(bad)",          { XX } },
8412   },
8413
8414   /* VEX_LEN_E2_P_2 */
8415   {
8416     { "vpsrad",         { XM, Vex128, EXx } },
8417     { "(bad)",          { XX } },
8418   },
8419
8420   /* VEX_LEN_E3_P_2 */
8421   {
8422     { "vpavgw",         { XM, Vex128, EXx } },
8423     { "(bad)",          { XX } },
8424   },
8425
8426   /* VEX_LEN_E4_P_2 */
8427   {
8428     { "vpmulhuw",       { XM, Vex128, EXx } },
8429     { "(bad)",          { XX } },
8430   },
8431
8432   /* VEX_LEN_E5_P_2 */
8433   {
8434     { "vpmulhw",        { XM, Vex128, EXx } },
8435     { "(bad)",          { XX } },
8436   },
8437
8438   /* VEX_LEN_E7_P_2_M_0 */
8439   {
8440     { "vmovntdq",       { Mx, XM } },
8441     { "(bad)",          { XX } },
8442   },
8443
8444   /* VEX_LEN_E8_P_2 */
8445   {
8446     { "vpsubsb",        { XM, Vex128, EXx } },
8447     { "(bad)",          { XX } },
8448   },
8449
8450   /* VEX_LEN_E9_P_2 */
8451   {
8452     { "vpsubsw",        { XM, Vex128, EXx } },
8453     { "(bad)",          { XX } },
8454   },
8455
8456   /* VEX_LEN_EA_P_2 */
8457   {
8458     { "vpminsw",        { XM, Vex128, EXx } },
8459     { "(bad)",          { XX } },
8460   },
8461
8462   /* VEX_LEN_EB_P_2 */
8463   {
8464     { "vpor",           { XM, Vex128, EXx } },
8465     { "(bad)",          { XX } },
8466   },
8467
8468   /* VEX_LEN_EC_P_2 */
8469   {
8470     { "vpaddsb",        { XM, Vex128, EXx } },
8471     { "(bad)",          { XX } },
8472   },
8473
8474   /* VEX_LEN_ED_P_2 */
8475   {
8476     { "vpaddsw",        { XM, Vex128, EXx } },
8477     { "(bad)",          { XX } },
8478   },
8479
8480   /* VEX_LEN_EE_P_2 */
8481   {
8482     { "vpmaxsw",        { XM, Vex128, EXx } },
8483     { "(bad)",          { XX } },
8484   },
8485
8486   /* VEX_LEN_EF_P_2 */
8487   {
8488     { "vpxor",          { XM, Vex128, EXx } },
8489     { "(bad)",          { XX } },
8490   },
8491
8492   /* VEX_LEN_F1_P_2 */
8493   {
8494     { "vpsllw",         { XM, Vex128, EXx } },
8495     { "(bad)",          { XX } },
8496   },
8497
8498   /* VEX_LEN_F2_P_2 */
8499   {
8500     { "vpslld",         { XM, Vex128, EXx } },
8501     { "(bad)",          { XX } },
8502   },
8503
8504   /* VEX_LEN_F3_P_2 */
8505   {
8506     { "vpsllq",         { XM, Vex128, EXx } },
8507     { "(bad)",          { XX } },
8508   },
8509
8510   /* VEX_LEN_F4_P_2 */
8511   {
8512     { "vpmuludq",       { XM, Vex128, EXx } },
8513     { "(bad)",          { XX } },
8514   },
8515
8516   /* VEX_LEN_F5_P_2 */
8517   {
8518     { "vpmaddwd",       { XM, Vex128, EXx } },
8519     { "(bad)",          { XX } },
8520   },
8521
8522   /* VEX_LEN_F6_P_2 */
8523   {
8524     { "vpsadbw",        { XM, Vex128, EXx } },
8525     { "(bad)",          { XX } },
8526   },
8527
8528   /* VEX_LEN_F7_P_2 */
8529   {
8530     { "vmaskmovdqu",    { XM, XS } },
8531     { "(bad)",          { XX } },
8532   },
8533
8534   /* VEX_LEN_F8_P_2 */
8535   {
8536     { "vpsubb",         { XM, Vex128, EXx } },
8537     { "(bad)",          { XX } },
8538   },
8539
8540   /* VEX_LEN_F9_P_2 */
8541   {
8542     { "vpsubw",         { XM, Vex128, EXx } },
8543     { "(bad)",          { XX } },
8544   },
8545
8546   /* VEX_LEN_FA_P_2 */
8547   {
8548     { "vpsubd",         { XM, Vex128, EXx } },
8549     { "(bad)",          { XX } },
8550   },
8551
8552   /* VEX_LEN_FB_P_2 */
8553   {
8554     { "vpsubq",         { XM, Vex128, EXx } },
8555     { "(bad)",          { XX } },
8556   },
8557
8558   /* VEX_LEN_FC_P_2 */
8559   {
8560     { "vpaddb",         { XM, Vex128, EXx } },
8561     { "(bad)",          { XX } },
8562   },
8563
8564   /* VEX_LEN_FD_P_2 */
8565   {
8566     { "vpaddw",         { XM, Vex128, EXx } },
8567     { "(bad)",          { XX } },
8568   },
8569
8570   /* VEX_LEN_FE_P_2 */
8571   {
8572     { "vpaddd",         { XM, Vex128, EXx } },
8573     { "(bad)",          { XX } },
8574   },
8575
8576   /* VEX_LEN_3800_P_2 */
8577   {
8578     { "vpshufb",        { XM, Vex128, EXx } },
8579     { "(bad)",          { XX } },
8580   },
8581
8582   /* VEX_LEN_3801_P_2 */
8583   {
8584     { "vphaddw",        { XM, Vex128, EXx } },
8585     { "(bad)",          { XX } },
8586   },
8587
8588   /* VEX_LEN_3802_P_2 */
8589   {
8590     { "vphaddd",        { XM, Vex128, EXx } },
8591     { "(bad)",          { XX } },
8592   },
8593
8594   /* VEX_LEN_3803_P_2 */
8595   {
8596     { "vphaddsw",       { XM, Vex128, EXx } },
8597     { "(bad)",          { XX } },
8598   },
8599
8600   /* VEX_LEN_3804_P_2 */
8601   {
8602     { "vpmaddubsw",     { XM, Vex128, EXx } },
8603     { "(bad)",          { XX } },
8604   },
8605
8606   /* VEX_LEN_3805_P_2 */
8607   {
8608     { "vphsubw",        { XM, Vex128, EXx } },
8609     { "(bad)",          { XX } },
8610   },
8611
8612   /* VEX_LEN_3806_P_2 */
8613   {
8614     { "vphsubd",        { XM, Vex128, EXx } },
8615     { "(bad)",          { XX } },
8616   },
8617
8618   /* VEX_LEN_3807_P_2 */
8619   {
8620     { "vphsubsw",       { XM, Vex128, EXx } },
8621     { "(bad)",          { XX } },
8622   },
8623
8624   /* VEX_LEN_3808_P_2 */
8625   {
8626     { "vpsignb",        { XM, Vex128, EXx } },
8627     { "(bad)",          { XX } },
8628   },
8629
8630   /* VEX_LEN_3809_P_2 */
8631   {
8632     { "vpsignw",        { XM, Vex128, EXx } },
8633     { "(bad)",          { XX } },
8634   },
8635
8636   /* VEX_LEN_380A_P_2 */
8637   {
8638     { "vpsignd",        { XM, Vex128, EXx } },
8639     { "(bad)",          { XX } },
8640   },
8641
8642   /* VEX_LEN_380B_P_2 */
8643   {
8644     { "vpmulhrsw",      { XM, Vex128, EXx } },
8645     { "(bad)",          { XX } },
8646   },
8647
8648   /* VEX_LEN_3819_P_2_M_0 */
8649   {
8650     { "(bad)",          { XX } },
8651     { "vbroadcastsd",   { XM, Mq } },
8652   },
8653
8654   /* VEX_LEN_381A_P_2_M_0 */
8655   {
8656     { "(bad)",          { XX } },
8657     { "vbroadcastf128", { XM, Mxmm } },
8658   },
8659
8660   /* VEX_LEN_381C_P_2 */
8661   {
8662     { "vpabsb",         { XM, EXx } },
8663     { "(bad)",          { XX } },
8664   },
8665
8666   /* VEX_LEN_381D_P_2 */
8667   {
8668     { "vpabsw",         { XM, EXx } },
8669     { "(bad)",          { XX } },
8670   },
8671
8672   /* VEX_LEN_381E_P_2 */
8673   {
8674     { "vpabsd",         { XM, EXx } },
8675     { "(bad)",          { XX } },
8676   },
8677
8678   /* VEX_LEN_3820_P_2 */
8679   {
8680     { "vpmovsxbw",      { XM, EXq } },
8681     { "(bad)",          { XX } },
8682   },
8683
8684   /* VEX_LEN_3821_P_2 */
8685   {
8686     { "vpmovsxbd",      { XM, EXd } },
8687     { "(bad)",          { XX } },
8688   },
8689
8690   /* VEX_LEN_3822_P_2 */
8691   {
8692     { "vpmovsxbq",      { XM, EXw } },
8693     { "(bad)",          { XX } },
8694   },
8695
8696   /* VEX_LEN_3823_P_2 */
8697   {
8698     { "vpmovsxwd",      { XM, EXq } },
8699     { "(bad)",          { XX } },
8700   },
8701
8702   /* VEX_LEN_3824_P_2 */
8703   {
8704     { "vpmovsxwq",      { XM, EXd } },
8705     { "(bad)",          { XX } },
8706   },
8707
8708   /* VEX_LEN_3825_P_2 */
8709   {
8710     { "vpmovsxdq",      { XM, EXq } },
8711     { "(bad)",          { XX } },
8712   },
8713
8714   /* VEX_LEN_3828_P_2 */
8715   {
8716     { "vpmuldq",        { XM, Vex128, EXx } },
8717     { "(bad)",          { XX } },
8718   },
8719
8720   /* VEX_LEN_3829_P_2 */
8721   {
8722     { "vpcmpeqq",       { XM, Vex128, EXx } },
8723     { "(bad)",          { XX } },
8724   },
8725
8726   /* VEX_LEN_382A_P_2_M_0 */
8727   {
8728     { "vmovntdqa",      { XM, Mx } },
8729     { "(bad)",          { XX } },
8730   },
8731
8732   /* VEX_LEN_382B_P_2 */
8733   {
8734     { "vpackusdw",      { XM, Vex128, EXx } },
8735     { "(bad)",          { XX } },
8736   },
8737
8738   /* VEX_LEN_3830_P_2 */
8739   {
8740     { "vpmovzxbw",      { XM, EXq } },
8741     { "(bad)",          { XX } },
8742   },
8743
8744   /* VEX_LEN_3831_P_2 */
8745   {
8746     { "vpmovzxbd",      { XM, EXd } },
8747     { "(bad)",          { XX } },
8748   },
8749
8750   /* VEX_LEN_3832_P_2 */
8751   {
8752     { "vpmovzxbq",      { XM, EXw } },
8753     { "(bad)",          { XX } },
8754   },
8755
8756   /* VEX_LEN_3833_P_2 */
8757   {
8758     { "vpmovzxwd",      { XM, EXq } },
8759     { "(bad)",          { XX } },
8760   },
8761
8762   /* VEX_LEN_3834_P_2 */
8763   {
8764     { "vpmovzxwq",      { XM, EXd } },
8765     { "(bad)",          { XX } },
8766   },
8767
8768   /* VEX_LEN_3835_P_2 */
8769   {
8770     { "vpmovzxdq",      { XM, EXq } },
8771     { "(bad)",          { XX } },
8772   },
8773
8774   /* VEX_LEN_3837_P_2 */
8775   {
8776     { "vpcmpgtq",       { XM, Vex128, EXx } },
8777     { "(bad)",          { XX } },
8778   },
8779
8780   /* VEX_LEN_3838_P_2 */
8781   {
8782     { "vpminsb",        { XM, Vex128, EXx } },
8783     { "(bad)",          { XX } },
8784   },
8785
8786   /* VEX_LEN_3839_P_2 */
8787   {
8788     { "vpminsd",        { XM, Vex128, EXx } },
8789     { "(bad)",          { XX } },
8790   },
8791
8792   /* VEX_LEN_383A_P_2 */
8793   {
8794     { "vpminuw",        { XM, Vex128, EXx } },
8795     { "(bad)",          { XX } },
8796   },
8797
8798   /* VEX_LEN_383B_P_2 */
8799   {
8800     { "vpminud",        { XM, Vex128, EXx } },
8801     { "(bad)",          { XX } },
8802   },
8803
8804   /* VEX_LEN_383C_P_2 */
8805   {
8806     { "vpmaxsb",        { XM, Vex128, EXx } },
8807     { "(bad)",          { XX } },
8808   },
8809
8810   /* VEX_LEN_383D_P_2 */
8811   {
8812     { "vpmaxsd",        { XM, Vex128, EXx } },
8813     { "(bad)",          { XX } },
8814   },
8815
8816   /* VEX_LEN_383E_P_2 */
8817   {
8818     { "vpmaxuw",        { XM, Vex128, EXx } },
8819     { "(bad)",          { XX } },
8820   },
8821
8822   /* VEX_LEN_383F_P_2 */
8823   {
8824     { "vpmaxud",        { XM, Vex128, EXx } },
8825     { "(bad)",          { XX } },
8826   },
8827
8828   /* VEX_LEN_3840_P_2 */
8829   {
8830     { "vpmulld",        { XM, Vex128, EXx } },
8831     { "(bad)",          { XX } },
8832   },
8833
8834   /* VEX_LEN_3841_P_2 */
8835   {
8836     { "vphminposuw",    { XM, EXx } },
8837     { "(bad)",          { XX } },
8838   },
8839
8840   /* VEX_LEN_38DB_P_2 */
8841   {
8842     { "vaesimc",        { XM, EXx } },
8843     { "(bad)",          { XX } },
8844   },
8845
8846   /* VEX_LEN_38DC_P_2 */
8847   {
8848     { "vaesenc",        { XM, Vex128, EXx } },
8849     { "(bad)",          { XX } },
8850   },
8851
8852   /* VEX_LEN_38DD_P_2 */
8853   {
8854     { "vaesenclast",    { XM, Vex128, EXx } },
8855     { "(bad)",          { XX } },
8856   },
8857
8858   /* VEX_LEN_38DE_P_2 */
8859   {
8860     { "vaesdec",        { XM, Vex128, EXx } },
8861     { "(bad)",          { XX } },
8862   },
8863
8864   /* VEX_LEN_38DF_P_2 */
8865   {
8866     { "vaesdeclast",    { XM, Vex128, EXx } },
8867     { "(bad)",          { XX } },
8868   },
8869
8870   /* VEX_LEN_3A06_P_2 */
8871   {
8872     { "(bad)",          { XX } },
8873     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8874   },
8875
8876   /* VEX_LEN_3A0A_P_2 */
8877   {
8878     { "vroundss",       { XM, Vex128, EXd, Ib } },
8879     { "(bad)",          { XX } },
8880   },
8881
8882   /* VEX_LEN_3A0B_P_2 */
8883   {
8884     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8885     { "(bad)",          { XX } },
8886   },
8887
8888   /* VEX_LEN_3A0E_P_2 */
8889   {
8890     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8891     { "(bad)",          { XX } },
8892   },
8893
8894   /* VEX_LEN_3A0F_P_2 */
8895   {
8896     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8897     { "(bad)",          { XX } },
8898   },
8899
8900   /* VEX_LEN_3A14_P_2 */
8901   {
8902     { "vpextrb",        { Edqb, XM, Ib } },
8903     { "(bad)",          { XX } },
8904   },
8905
8906   /* VEX_LEN_3A15_P_2 */
8907   {
8908     { "vpextrw",        { Edqw, XM, Ib } },
8909     { "(bad)",          { XX } },
8910   },
8911
8912   /* VEX_LEN_3A16_P_2  */
8913   {
8914     { "vpextrK",        { Edq, XM, Ib } },
8915     { "(bad)",          { XX } },
8916   },
8917
8918   /* VEX_LEN_3A17_P_2 */
8919   {
8920     { "vextractps",     { Edqd, XM, Ib } },
8921     { "(bad)",          { XX } },
8922   },
8923
8924   /* VEX_LEN_3A18_P_2 */
8925   {
8926     { "(bad)",          { XX } },
8927     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8928   },
8929
8930   /* VEX_LEN_3A19_P_2 */
8931   {
8932     { "(bad)",          { XX } },
8933     { "vextractf128",   { EXxmm, XM, Ib } },
8934   },
8935
8936   /* VEX_LEN_3A20_P_2 */
8937   {
8938     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8939     { "(bad)",          { XX } },
8940   },
8941
8942   /* VEX_LEN_3A21_P_2 */
8943   {
8944     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8945     { "(bad)",          { XX } },
8946   },
8947
8948   /* VEX_LEN_3A22_P_2 */
8949   {
8950     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8951     { "(bad)",          { XX } },
8952   },
8953
8954   /* VEX_LEN_3A41_P_2 */
8955   {
8956     { "vdppd",          { XM, Vex128, EXx, Ib } },
8957     { "(bad)",          { XX } },
8958   },
8959
8960   /* VEX_LEN_3A42_P_2 */
8961   {
8962     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8963     { "(bad)",          { XX } },
8964   },
8965
8966   /* VEX_LEN_3A4C_P_2 */
8967   {
8968     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8969     { "(bad)",          { XX } },
8970   },
8971
8972   /* VEX_LEN_3A60_P_2 */
8973   {
8974     { "vpcmpestrm",     { XM, EXx, Ib } },
8975     { "(bad)",          { XX } },
8976   },
8977
8978   /* VEX_LEN_3A61_P_2 */
8979   {
8980     { "vpcmpestri",     { XM, EXx, Ib } },
8981     { "(bad)",          { XX } },
8982   },
8983
8984   /* VEX_LEN_3A62_P_2 */
8985   {
8986     { "vpcmpistrm",     { XM, EXx, Ib } },
8987     { "(bad)",          { XX } },
8988   },
8989
8990   /* VEX_LEN_3A63_P_2 */
8991   {
8992     { "vpcmpistri",     { XM, EXx, Ib } },
8993     { "(bad)",          { XX } },
8994   },
8995
8996   /* VEX_LEN_3A6A_P_2 */
8997   {
8998     { "vfmaddss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8999     { "(bad)",          { XX } },
9000   },
9001
9002   /* VEX_LEN_3A6B_P_2 */
9003   {
9004     { "vfmaddsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9005     { "(bad)",          { XX } },
9006   },
9007
9008   /* VEX_LEN_3A6E_P_2 */
9009   {
9010     { "vfmsubss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9011     { "(bad)",          { XX } },
9012   },
9013
9014   /* VEX_LEN_3A6F_P_2 */
9015   {
9016     { "vfmsubsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9017     { "(bad)",          { XX } },
9018   },
9019
9020   /* VEX_LEN_3A7A_P_2 */
9021   {
9022     { "vfnmaddss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9023     { "(bad)",          { XX } },
9024   },
9025
9026   /* VEX_LEN_3A7B_P_2 */
9027   {
9028     { "vfnmaddsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9029     { "(bad)",          { XX } },
9030   },
9031
9032   /* VEX_LEN_3A7E_P_2 */
9033   {
9034     { "vfnmsubss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9035     { "(bad)",          { XX } },
9036   },
9037
9038   /* VEX_LEN_3A7F_P_2 */
9039   {
9040     { "vfnmsubsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9041     { "(bad)",          { XX } },
9042   },
9043
9044   /* VEX_LEN_3ADF_P_2 */
9045   {
9046     { "vaeskeygenassist", { XM, EXx, Ib } },
9047     { "(bad)",          { XX } },
9048   },
9049 };
9050
9051 static const struct dis386 mod_table[][2] = {
9052   {
9053     /* MOD_8D */
9054     { "leaS",           { Gv, M } },
9055     { "(bad)",          { XX } },
9056   },
9057   {
9058     /* MOD_0F01_REG_0 */
9059     { X86_64_TABLE (X86_64_0F01_REG_0) },
9060     { RM_TABLE (RM_0F01_REG_0) },
9061   },
9062   {
9063     /* MOD_0F01_REG_1 */
9064     { X86_64_TABLE (X86_64_0F01_REG_1) },
9065     { RM_TABLE (RM_0F01_REG_1) },
9066   },
9067   {
9068     /* MOD_0F01_REG_2 */
9069     { X86_64_TABLE (X86_64_0F01_REG_2) },
9070     { RM_TABLE (RM_0F01_REG_2) },
9071   },
9072   {
9073     /* MOD_0F01_REG_3 */
9074     { X86_64_TABLE (X86_64_0F01_REG_3) },
9075     { RM_TABLE (RM_0F01_REG_3) },
9076   },
9077   {
9078     /* MOD_0F01_REG_7 */
9079     { "invlpg",         { Mb } },
9080     { RM_TABLE (RM_0F01_REG_7) },
9081   },
9082   {
9083     /* MOD_0F12_PREFIX_0 */
9084     { "movlps",         { XM, EXq } },
9085     { "movhlps",        { XM, EXq } },
9086   },
9087   {
9088     /* MOD_0F13 */
9089     { "movlpX",         { EXq, XM } },
9090     { "(bad)",          { XX } },
9091   },
9092   {
9093     /* MOD_0F16_PREFIX_0 */
9094     { "movhps",         { XM, EXq } },
9095     { "movlhps",        { XM, EXq } },
9096   },
9097   {
9098     /* MOD_0F17 */
9099     { "movhpX",         { EXq, XM } },
9100     { "(bad)",          { XX } },
9101   },
9102   {
9103     /* MOD_0F18_REG_0 */
9104     { "prefetchnta",    { Mb } },
9105     { "(bad)",          { XX } },
9106   },
9107   {
9108     /* MOD_0F18_REG_1 */
9109     { "prefetcht0",     { Mb } },
9110     { "(bad)",          { XX } },
9111   },
9112   {
9113     /* MOD_0F18_REG_2 */
9114     { "prefetcht1",     { Mb } },
9115     { "(bad)",          { XX } },
9116   },
9117   {
9118     /* MOD_0F18_REG_3 */
9119     { "prefetcht2",     { Mb } },
9120     { "(bad)",          { XX } },
9121   },
9122   {
9123     /* MOD_0F20 */
9124     { "(bad)",          { XX } },
9125     { "movZ",           { Rm, Cm } },
9126   },
9127   {
9128     /* MOD_0F21 */
9129     { "(bad)",          { XX } },
9130     { "movZ",           { Rm, Dm } },
9131   },
9132   {
9133     /* MOD_0F22 */
9134     { "(bad)",          { XX } },
9135     { "movZ",           { Cm, Rm } },
9136   },
9137   {
9138     /* MOD_0F23 */
9139     { "(bad)",          { XX } },
9140     { "movZ",           { Dm, Rm } },
9141   },
9142   {
9143     /* MOD_0F24 */
9144     { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9145     { "movL",           { Rd, Td } },
9146   },
9147   {
9148     /* MOD_0F26 */
9149     { "(bad)",          { XX } },
9150     { "movL",           { Td, Rd } },
9151   },
9152   {
9153     /* MOD_0F2B_PREFIX_0 */
9154     {"movntps",         { Mx, XM } },
9155     { "(bad)",          { XX } },
9156   },
9157   {
9158     /* MOD_0F2B_PREFIX_1 */
9159     {"movntss",         { Md, XM } },
9160     { "(bad)",          { XX } },
9161   },
9162   {
9163     /* MOD_0F2B_PREFIX_2 */
9164     {"movntpd",         { Mx, XM } },
9165     { "(bad)",          { XX } },
9166   },
9167   {
9168     /* MOD_0F2B_PREFIX_3 */
9169     {"movntsd",         { Mq, XM } },
9170     { "(bad)",          { XX } },
9171   },
9172   {
9173     /* MOD_0F51 */
9174     { "(bad)",          { XX } },
9175     { "movmskpX",       { Gdq, XS } },
9176   },
9177   {
9178     /* MOD_0F71_REG_2 */
9179     { "(bad)",          { XX } },
9180     { "psrlw",          { MS, Ib } },
9181   },
9182   {
9183     /* MOD_0F71_REG_4 */
9184     { "(bad)",          { XX } },
9185     { "psraw",          { MS, Ib } },
9186   },
9187   {
9188     /* MOD_0F71_REG_6 */
9189     { "(bad)",          { XX } },
9190     { "psllw",          { MS, Ib } },
9191   },
9192   {
9193     /* MOD_0F72_REG_2 */
9194     { "(bad)",          { XX } },
9195     { "psrld",          { MS, Ib } },
9196   },
9197   {
9198     /* MOD_0F72_REG_4 */
9199     { "(bad)",          { XX } },
9200     { "psrad",          { MS, Ib } },
9201   },
9202   {
9203     /* MOD_0F72_REG_6 */
9204     { "(bad)",          { XX } },
9205     { "pslld",          { MS, Ib } },
9206   },
9207   {
9208     /* MOD_0F73_REG_2 */
9209     { "(bad)",          { XX } },
9210     { "psrlq",          { MS, Ib } },
9211   },
9212   {
9213     /* MOD_0F73_REG_3 */
9214     { "(bad)",          { XX } },
9215     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9216   },
9217   {
9218     /* MOD_0F73_REG_6 */
9219     { "(bad)",          { XX } },
9220     { "psllq",          { MS, Ib } },
9221   },
9222   {
9223     /* MOD_0F73_REG_7 */
9224     { "(bad)",          { XX } },
9225     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9226   },
9227   {
9228     /* MOD_0FAE_REG_0 */
9229     { "fxsave",         { M } },
9230     { "(bad)",          { XX } },
9231   },
9232   {
9233     /* MOD_0FAE_REG_1 */
9234     { "fxrstor",        { M } },
9235     { "(bad)",          { XX } },
9236   },
9237   {
9238     /* MOD_0FAE_REG_2 */
9239     { "ldmxcsr",        { Md } },
9240     { "(bad)",          { XX } },
9241   },
9242   {
9243     /* MOD_0FAE_REG_3 */
9244     { "stmxcsr",        { Md } },
9245     { "(bad)",          { XX } },
9246   },
9247   {
9248     /* MOD_0FAE_REG_4 */
9249     { "xsave",          { M } },
9250     { "(bad)",          { XX } },
9251   },
9252   {
9253     /* MOD_0FAE_REG_5 */
9254     { "xrstor",         { M } },
9255     { RM_TABLE (RM_0FAE_REG_5) },
9256   },
9257   {
9258     /* MOD_0FAE_REG_6 */
9259     { "xsaveopt",       { M } },
9260     { RM_TABLE (RM_0FAE_REG_6) },
9261   },
9262   {
9263     /* MOD_0FAE_REG_7 */
9264     { "clflush",        { Mb } },
9265     { RM_TABLE (RM_0FAE_REG_7) },
9266   },
9267   {
9268     /* MOD_0FB2 */
9269     { "lssS",           { Gv, Mp } },
9270     { "(bad)",          { XX } },
9271   },
9272   {
9273     /* MOD_0FB4 */
9274     { "lfsS",           { Gv, Mp } },
9275     { "(bad)",          { XX } },
9276   },
9277   {
9278     /* MOD_0FB5 */
9279     { "lgsS",           { Gv, Mp } },
9280     { "(bad)",          { XX } },
9281   },
9282   {
9283     /* MOD_0FC7_REG_6 */
9284     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9285     { "(bad)",          { XX } },
9286   },
9287   {
9288     /* MOD_0FC7_REG_7 */
9289     { "vmptrst",        { Mq } },
9290     { "(bad)",          { XX } },
9291   },
9292   {
9293     /* MOD_0FD7 */
9294     { "(bad)",          { XX } },
9295     { "pmovmskb",       { Gdq, MS } },
9296   },
9297   {
9298     /* MOD_0FE7_PREFIX_2 */
9299     { "movntdq",        { Mx, XM } },
9300     { "(bad)",          { XX } },
9301   },
9302   {
9303     /* MOD_0FF0_PREFIX_3 */
9304     { "lddqu",          { XM, M } },
9305     { "(bad)",          { XX } },
9306   },
9307   {
9308     /* MOD_0F382A_PREFIX_2 */
9309     { "movntdqa",       { XM, Mx } },
9310     { "(bad)",          { XX } },
9311   },
9312   {
9313     /* MOD_62_32BIT */
9314     { "bound{S|}",      { Gv, Ma } },
9315     { "(bad)",          { XX } },
9316   },
9317   {
9318     /* MOD_C4_32BIT */
9319     { "lesS",           { Gv, Mp } },
9320     { VEX_C4_TABLE (VEX_0F) },
9321   },
9322   {
9323     /* MOD_C5_32BIT */
9324     { "ldsS",           { Gv, Mp } },
9325     { VEX_C5_TABLE (VEX_0F) },
9326   },
9327   {
9328     /* MOD_VEX_12_PREFIX_0 */
9329     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9330     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9331   },
9332   {
9333     /* MOD_VEX_13 */
9334     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9335     { "(bad)",          { XX } },
9336   },
9337   {
9338     /* MOD_VEX_16_PREFIX_0 */
9339     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9340     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9341   },
9342   {
9343     /* MOD_VEX_17 */
9344     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9345     { "(bad)",          { XX } },
9346   },
9347   {
9348     /* MOD_VEX_2B */
9349     { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9350     { "(bad)",          { XX } },
9351   },
9352   {
9353     /* MOD_VEX_51 */
9354     { "(bad)",          { XX } },
9355     { "vmovmskpX",      { Gdq, XS } },
9356   },
9357   {
9358     /* MOD_VEX_71_REG_2 */
9359     { "(bad)",          { XX } },
9360     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9361   },
9362   {
9363     /* MOD_VEX_71_REG_4 */
9364     { "(bad)",          { XX } },
9365     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9366   },
9367   {
9368     /* MOD_VEX_71_REG_6 */
9369     { "(bad)",          { XX } },
9370     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9371   },
9372   {
9373     /* MOD_VEX_72_REG_2 */
9374     { "(bad)",          { XX } },
9375     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9376   },
9377   {
9378     /* MOD_VEX_72_REG_4 */
9379     { "(bad)",          { XX } },
9380     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9381   },
9382   {
9383     /* MOD_VEX_72_REG_6 */
9384     { "(bad)",          { XX } },
9385     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9386   },
9387   {
9388     /* MOD_VEX_73_REG_2 */
9389     { "(bad)",          { XX } },
9390     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9391   },
9392   {
9393     /* MOD_VEX_73_REG_3 */
9394     { "(bad)",          { XX } },
9395     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9396   },
9397   {
9398     /* MOD_VEX_73_REG_6 */
9399     { "(bad)",          { XX } },
9400     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9401   },
9402   {
9403     /* MOD_VEX_73_REG_7 */
9404     { "(bad)",          { XX } },
9405     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9406   },
9407   {
9408     /* MOD_VEX_AE_REG_2 */
9409     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9410     { "(bad)",          { XX } },
9411   },
9412   {
9413     /* MOD_VEX_AE_REG_3 */
9414     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9415     { "(bad)",          { XX } },
9416   },
9417   {
9418     /* MOD_VEX_D7_PREFIX_2 */
9419     { "(bad)",          { XX } },
9420     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9421   },
9422   {
9423     /* MOD_VEX_E7_PREFIX_2 */
9424     { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9425     { "(bad)",          { XX } },
9426   },
9427   {
9428     /* MOD_VEX_F0_PREFIX_3 */
9429     { "vlddqu",         { XM, M } },
9430     { "(bad)",          { XX } },
9431   },
9432   {
9433     /* MOD_VEX_3818_PREFIX_2 */
9434     { "vbroadcastss",   { XM, Md } },
9435     { "(bad)",          { XX } },
9436   },
9437   {
9438     /* MOD_VEX_3819_PREFIX_2 */
9439     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9440     { "(bad)",          { XX } },
9441   },
9442   {
9443     /* MOD_VEX_381A_PREFIX_2 */
9444     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9445     { "(bad)",          { XX } },
9446   },
9447   {
9448     /* MOD_VEX_382A_PREFIX_2 */
9449     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9450     { "(bad)",          { XX } },
9451   },
9452   {
9453     /* MOD_VEX_382C_PREFIX_2 */
9454     { "vmaskmovps",     { XM, Vex, Mx } },
9455     { "(bad)",          { XX } },
9456   },
9457   {
9458     /* MOD_VEX_382D_PREFIX_2 */
9459     { "vmaskmovpd",     { XM, Vex, Mx } },
9460     { "(bad)",          { XX } },
9461   },
9462   {
9463     /* MOD_VEX_382E_PREFIX_2 */
9464     { "vmaskmovps",     { Mx, Vex, XM } },
9465     { "(bad)",          { XX } },
9466   },
9467   {
9468     /* MOD_VEX_382F_PREFIX_2 */
9469     { "vmaskmovpd",     { Mx, Vex, XM } },
9470     { "(bad)",          { XX } },
9471   },
9472 };
9473
9474 static const struct dis386 rm_table[][8] = {
9475   {
9476     /* RM_0F01_REG_0 */
9477     { "(bad)",          { XX } },
9478     { "vmcall",         { Skip_MODRM } },
9479     { "vmlaunch",       { Skip_MODRM } },
9480     { "vmresume",       { Skip_MODRM } },
9481     { "vmxoff",         { Skip_MODRM } },
9482     { "(bad)",          { XX } },
9483     { "(bad)",          { XX } },
9484     { "(bad)",          { XX } },
9485   },
9486   {
9487     /* RM_0F01_REG_1 */
9488     { "monitor",        { { OP_Monitor, 0 } } },
9489     { "mwait",          { { OP_Mwait, 0 } } },
9490     { "(bad)",          { XX } },
9491     { "(bad)",          { XX } },
9492     { "(bad)",          { XX } },
9493     { "(bad)",          { XX } },
9494     { "(bad)",          { XX } },
9495     { "(bad)",          { XX } },
9496   },
9497   {
9498     /* RM_0F01_REG_2 */
9499     { "xgetbv",         { Skip_MODRM } },
9500     { "xsetbv",         { Skip_MODRM } },
9501     { "(bad)",          { XX } },
9502     { "(bad)",          { XX } },
9503     { "(bad)",          { XX } },
9504     { "(bad)",          { XX } },
9505     { "(bad)",          { XX } },
9506     { "(bad)",          { XX } },
9507   },
9508   {
9509     /* RM_0F01_REG_3 */
9510     { "vmrun",          { Skip_MODRM } },
9511     { "vmmcall",        { Skip_MODRM } },
9512     { "vmload",         { Skip_MODRM } },
9513     { "vmsave",         { Skip_MODRM } },
9514     { "stgi",           { Skip_MODRM } },
9515     { "clgi",           { Skip_MODRM } },
9516     { "skinit",         { Skip_MODRM } },
9517     { "invlpga",        { Skip_MODRM } },
9518   },
9519   {
9520     /* RM_0F01_REG_7 */
9521     { "swapgs",         { Skip_MODRM } },
9522     { "rdtscp",         { Skip_MODRM } },
9523     { "(bad)",          { XX } },
9524     { "(bad)",          { XX } },
9525     { "(bad)",          { XX } },
9526     { "(bad)",          { XX } },
9527     { "(bad)",          { XX } },
9528     { "(bad)",          { XX } },
9529   },
9530   {
9531     /* RM_0FAE_REG_5 */
9532     { "lfence",         { Skip_MODRM } },
9533     { "(bad)",          { XX } },
9534     { "(bad)",          { XX } },
9535     { "(bad)",          { XX } },
9536     { "(bad)",          { XX } },
9537     { "(bad)",          { XX } },
9538     { "(bad)",          { XX } },
9539     { "(bad)",          { XX } },
9540   },
9541   {
9542     /* RM_0FAE_REG_6 */
9543     { "mfence",         { Skip_MODRM } },
9544     { "(bad)",          { XX } },
9545     { "(bad)",          { XX } },
9546     { "(bad)",          { XX } },
9547     { "(bad)",          { XX } },
9548     { "(bad)",          { XX } },
9549     { "(bad)",          { XX } },
9550     { "(bad)",          { XX } },
9551   },
9552   {
9553     /* RM_0FAE_REG_7 */
9554     { "sfence",         { Skip_MODRM } },
9555     { "(bad)",          { XX } },
9556     { "(bad)",          { XX } },
9557     { "(bad)",          { XX } },
9558     { "(bad)",          { XX } },
9559     { "(bad)",          { XX } },
9560     { "(bad)",          { XX } },
9561     { "(bad)",          { XX } },
9562   },
9563 };
9564
9565 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9566
9567 static void
9568 ckprefix (void)
9569 {
9570   int newrex;
9571   rex = 0;
9572   rex_original = 0;
9573   rex_ignored = 0;
9574   prefixes = 0;
9575   used_prefixes = 0;
9576   rex_used = 0;
9577   while (1)
9578     {
9579       FETCH_DATA (the_info, codep + 1);
9580       newrex = 0;
9581       switch (*codep)
9582         {
9583         /* REX prefixes family.  */
9584         case 0x40:
9585         case 0x41:
9586         case 0x42:
9587         case 0x43:
9588         case 0x44:
9589         case 0x45:
9590         case 0x46:
9591         case 0x47:
9592         case 0x48:
9593         case 0x49:
9594         case 0x4a:
9595         case 0x4b:
9596         case 0x4c:
9597         case 0x4d:
9598         case 0x4e:
9599         case 0x4f:
9600             if (address_mode == mode_64bit)
9601               newrex = *codep;
9602             else
9603               return;
9604           break;
9605         case 0xf3:
9606           prefixes |= PREFIX_REPZ;
9607           break;
9608         case 0xf2:
9609           prefixes |= PREFIX_REPNZ;
9610           break;
9611         case 0xf0:
9612           prefixes |= PREFIX_LOCK;
9613           break;
9614         case 0x2e:
9615           prefixes |= PREFIX_CS;
9616           break;
9617         case 0x36:
9618           prefixes |= PREFIX_SS;
9619           break;
9620         case 0x3e:
9621           prefixes |= PREFIX_DS;
9622           break;
9623         case 0x26:
9624           prefixes |= PREFIX_ES;
9625           break;
9626         case 0x64:
9627           prefixes |= PREFIX_FS;
9628           break;
9629         case 0x65:
9630           prefixes |= PREFIX_GS;
9631           break;
9632         case 0x66:
9633           prefixes |= PREFIX_DATA;
9634           break;
9635         case 0x67:
9636           prefixes |= PREFIX_ADDR;
9637           break;
9638         case FWAIT_OPCODE:
9639           /* fwait is really an instruction.  If there are prefixes
9640              before the fwait, they belong to the fwait, *not* to the
9641              following instruction.  */
9642           if (prefixes || rex)
9643             {
9644               prefixes |= PREFIX_FWAIT;
9645               codep++;
9646               return;
9647             }
9648           prefixes = PREFIX_FWAIT;
9649           break;
9650         default:
9651           return;
9652         }
9653       /* Rex is ignored when followed by another prefix.  */
9654       if (rex)
9655         {
9656           rex_used = rex;
9657           return;
9658         }
9659       rex = newrex;
9660       rex_original = rex;
9661       codep++;
9662     }
9663 }
9664
9665 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9666    prefix byte.  */
9667
9668 static const char *
9669 prefix_name (int pref, int sizeflag)
9670 {
9671   static const char *rexes [16] =
9672     {
9673       "rex",            /* 0x40 */
9674       "rex.B",          /* 0x41 */
9675       "rex.X",          /* 0x42 */
9676       "rex.XB",         /* 0x43 */
9677       "rex.R",          /* 0x44 */
9678       "rex.RB",         /* 0x45 */
9679       "rex.RX",         /* 0x46 */
9680       "rex.RXB",        /* 0x47 */
9681       "rex.W",          /* 0x48 */
9682       "rex.WB",         /* 0x49 */
9683       "rex.WX",         /* 0x4a */
9684       "rex.WXB",        /* 0x4b */
9685       "rex.WR",         /* 0x4c */
9686       "rex.WRB",        /* 0x4d */
9687       "rex.WRX",        /* 0x4e */
9688       "rex.WRXB",       /* 0x4f */
9689     };
9690
9691   switch (pref)
9692     {
9693     /* REX prefixes family.  */
9694     case 0x40:
9695     case 0x41:
9696     case 0x42:
9697     case 0x43:
9698     case 0x44:
9699     case 0x45:
9700     case 0x46:
9701     case 0x47:
9702     case 0x48:
9703     case 0x49:
9704     case 0x4a:
9705     case 0x4b:
9706     case 0x4c:
9707     case 0x4d:
9708     case 0x4e:
9709     case 0x4f:
9710       return rexes [pref - 0x40];
9711     case 0xf3:
9712       return "repz";
9713     case 0xf2:
9714       return "repnz";
9715     case 0xf0:
9716       return "lock";
9717     case 0x2e:
9718       return "cs";
9719     case 0x36:
9720       return "ss";
9721     case 0x3e:
9722       return "ds";
9723     case 0x26:
9724       return "es";
9725     case 0x64:
9726       return "fs";
9727     case 0x65:
9728       return "gs";
9729     case 0x66:
9730       return (sizeflag & DFLAG) ? "data16" : "data32";
9731     case 0x67:
9732       if (address_mode == mode_64bit)
9733         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9734       else
9735         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9736     case FWAIT_OPCODE:
9737       return "fwait";
9738     default:
9739       return NULL;
9740     }
9741 }
9742
9743 static char op_out[MAX_OPERANDS][100];
9744 static int op_ad, op_index[MAX_OPERANDS];
9745 static int two_source_ops;
9746 static bfd_vma op_address[MAX_OPERANDS];
9747 static bfd_vma op_riprel[MAX_OPERANDS];
9748 static bfd_vma start_pc;
9749
9750 /*
9751  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9752  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9753  *   section of the "Virtual 8086 Mode" chapter.)
9754  * 'pc' should be the address of this instruction, it will
9755  *   be used to print the target address if this is a relative jump or call
9756  * The function returns the length of this instruction in bytes.
9757  */
9758
9759 static char intel_syntax;
9760 static char intel_mnemonic = !SYSV386_COMPAT;
9761 static char open_char;
9762 static char close_char;
9763 static char separator_char;
9764 static char scale_char;
9765
9766 /* Here for backwards compatibility.  When gdb stops using
9767    print_insn_i386_att and print_insn_i386_intel these functions can
9768    disappear, and print_insn_i386 be merged into print_insn.  */
9769 int
9770 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9771 {
9772   intel_syntax = 0;
9773
9774   return print_insn (pc, info);
9775 }
9776
9777 int
9778 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9779 {
9780   intel_syntax = 1;
9781
9782   return print_insn (pc, info);
9783 }
9784
9785 int
9786 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9787 {
9788   intel_syntax = -1;
9789
9790   return print_insn (pc, info);
9791 }
9792
9793 void
9794 print_i386_disassembler_options (FILE *stream)
9795 {
9796   fprintf (stream, _("\n\
9797 The following i386/x86-64 specific disassembler options are supported for use\n\
9798 with the -M switch (multiple options should be separated by commas):\n"));
9799
9800   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9801   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9802   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9803   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9804   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9805   fprintf (stream, _("  att-mnemonic\n"
9806                      "              Display instruction in AT&T mnemonic\n"));
9807   fprintf (stream, _("  intel-mnemonic\n"
9808                      "              Display instruction in Intel mnemonic\n"));
9809   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9810   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9811   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9812   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9813   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9814   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9815 }
9816
9817 /* Get a pointer to struct dis386 with a valid name.  */
9818
9819 static const struct dis386 *
9820 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9821 {
9822   int index, vex_table_index;
9823
9824   if (dp->name != NULL)
9825     return dp;
9826
9827   switch (dp->op[0].bytemode)
9828     {
9829     case USE_REG_TABLE:
9830       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9831       break;
9832
9833     case USE_MOD_TABLE:
9834       index = modrm.mod == 0x3 ? 1 : 0;
9835       dp = &mod_table[dp->op[1].bytemode][index];
9836       break;
9837
9838     case USE_RM_TABLE:
9839       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9840       break;
9841
9842     case USE_PREFIX_TABLE:
9843       if (need_vex)
9844         {
9845           /* The prefix in VEX is implicit.  */
9846           switch (vex.prefix)
9847             {
9848             case 0:
9849               index = 0;
9850               break;
9851             case REPE_PREFIX_OPCODE:
9852               index = 1;
9853               break;
9854             case DATA_PREFIX_OPCODE:
9855               index = 2;
9856               break;
9857             case REPNE_PREFIX_OPCODE:
9858               index = 3;
9859               break;
9860             default:
9861               abort ();
9862               break;
9863             }
9864         }
9865       else
9866         {
9867           index = 0;
9868           used_prefixes |= (prefixes & PREFIX_REPZ);
9869           if (prefixes & PREFIX_REPZ)
9870             {
9871               index = 1;
9872               repz_prefix = NULL;
9873             }
9874           else
9875             {
9876               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9877                  PREFIX_DATA.  */
9878               used_prefixes |= (prefixes & PREFIX_REPNZ);
9879               if (prefixes & PREFIX_REPNZ)
9880                 {
9881                   index = 3;
9882                   repnz_prefix = NULL;
9883                 }
9884               else
9885                 {
9886                   used_prefixes |= (prefixes & PREFIX_DATA);
9887                   if (prefixes & PREFIX_DATA)
9888                     {
9889                       index = 2;
9890                       data_prefix = NULL;
9891                     }
9892                 }
9893             }
9894         }
9895       dp = &prefix_table[dp->op[1].bytemode][index];
9896       break;
9897
9898     case USE_X86_64_TABLE:
9899       index = address_mode == mode_64bit ? 1 : 0;
9900       dp = &x86_64_table[dp->op[1].bytemode][index];
9901       break;
9902
9903     case USE_3BYTE_TABLE:
9904       FETCH_DATA (info, codep + 2);
9905       index = *codep++;
9906       dp = &three_byte_table[dp->op[1].bytemode][index];
9907       modrm.mod = (*codep >> 6) & 3;
9908       modrm.reg = (*codep >> 3) & 7;
9909       modrm.rm = *codep & 7;
9910       break;
9911
9912     case USE_VEX_LEN_TABLE:
9913       if (!need_vex)
9914         abort ();
9915
9916       switch (vex.length)
9917         {
9918         case 128:
9919           index = 0;
9920           break;
9921         case 256:
9922           index = 1;
9923           break;
9924         default:
9925           abort ();
9926           break;
9927         }
9928
9929       dp = &vex_len_table[dp->op[1].bytemode][index];
9930       break;
9931
9932     case USE_VEX_C4_TABLE:
9933       FETCH_DATA (info, codep + 3);
9934       /* All bits in the REX prefix are ignored.  */
9935       rex_ignored = rex;
9936       rex = ~(*codep >> 5) & 0x7;
9937       switch ((*codep & 0x1f))
9938         {
9939         default:
9940           BadOp ();
9941         case 0x1:
9942           vex_table_index = 0;
9943           break;
9944         case 0x2:
9945           vex_table_index = 1;
9946           break;
9947         case 0x3:
9948           vex_table_index = 2;
9949           break;
9950         }
9951       codep++;
9952       vex.w = *codep & 0x80;
9953       if (vex.w && address_mode == mode_64bit)
9954         rex |= REX_W;
9955
9956       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9957       if (address_mode != mode_64bit
9958           && vex.register_specifier > 0x7)
9959         BadOp ();
9960
9961       vex.length = (*codep & 0x4) ? 256 : 128;
9962       switch ((*codep & 0x3))
9963         {
9964         case 0:
9965           vex.prefix = 0;
9966           break;
9967         case 1:
9968           vex.prefix = DATA_PREFIX_OPCODE;
9969           break;
9970         case 2:
9971           vex.prefix = REPE_PREFIX_OPCODE;
9972           break;
9973         case 3:
9974           vex.prefix = REPNE_PREFIX_OPCODE;
9975           break;
9976         }
9977       need_vex = 1;
9978       need_vex_reg = 1;
9979       codep++;
9980       index = *codep++;
9981       dp = &vex_table[vex_table_index][index];
9982       /* There is no MODRM byte for VEX [82|77].  */
9983       if (index != 0x77 && index != 0x82)
9984         {
9985           FETCH_DATA (info, codep + 1);
9986           modrm.mod = (*codep >> 6) & 3;
9987           modrm.reg = (*codep >> 3) & 7;
9988           modrm.rm = *codep & 7;
9989         }
9990       break;
9991
9992     case USE_VEX_C5_TABLE:
9993       FETCH_DATA (info, codep + 2);
9994       /* All bits in the REX prefix are ignored.  */
9995       rex_ignored = rex;
9996       rex = (*codep & 0x80) ? 0 : REX_R;
9997
9998       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9999       if (address_mode != mode_64bit
10000           && vex.register_specifier > 0x7)
10001         BadOp ();
10002
10003       vex.length = (*codep & 0x4) ? 256 : 128;
10004       switch ((*codep & 0x3))
10005         {
10006         case 0:
10007           vex.prefix = 0;
10008           break;
10009         case 1:
10010           vex.prefix = DATA_PREFIX_OPCODE;
10011           break;
10012         case 2:
10013           vex.prefix = REPE_PREFIX_OPCODE;
10014           break;
10015         case 3:
10016           vex.prefix = REPNE_PREFIX_OPCODE;
10017           break;
10018         }
10019       need_vex = 1;
10020       need_vex_reg = 1;
10021       codep++;
10022       index = *codep++;
10023       dp = &vex_table[dp->op[1].bytemode][index];
10024       /* There is no MODRM byte for VEX [82|77].  */
10025       if (index != 0x77 && index != 0x82)
10026         {
10027           FETCH_DATA (info, codep + 1);
10028           modrm.mod = (*codep >> 6) & 3;
10029           modrm.reg = (*codep >> 3) & 7;
10030           modrm.rm = *codep & 7;
10031         }
10032       break;
10033
10034     default:
10035       oappend (INTERNAL_DISASSEMBLER_ERROR);
10036       return NULL;
10037     }
10038
10039   if (dp->name != NULL)
10040     return dp;
10041   else
10042     return get_valid_dis386 (dp, info);
10043 }
10044
10045 static int
10046 print_insn (bfd_vma pc, disassemble_info *info)
10047 {
10048   const struct dis386 *dp;
10049   int i;
10050   char *op_txt[MAX_OPERANDS];
10051   int needcomma;
10052   int sizeflag;
10053   const char *p;
10054   struct dis_private priv;
10055   unsigned char op;
10056   char prefix_obuf[32];
10057   char *prefix_obufp;
10058
10059   if (info->mach == bfd_mach_x86_64_intel_syntax
10060       || info->mach == bfd_mach_x86_64)
10061     address_mode = mode_64bit;
10062   else
10063     address_mode = mode_32bit;
10064
10065   if (intel_syntax == (char) -1)
10066     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10067                     || info->mach == bfd_mach_x86_64_intel_syntax);
10068
10069   if (info->mach == bfd_mach_i386_i386
10070       || info->mach == bfd_mach_x86_64
10071       || info->mach == bfd_mach_i386_i386_intel_syntax
10072       || info->mach == bfd_mach_x86_64_intel_syntax)
10073     priv.orig_sizeflag = AFLAG | DFLAG;
10074   else if (info->mach == bfd_mach_i386_i8086)
10075     priv.orig_sizeflag = 0;
10076   else
10077     abort ();
10078
10079   for (p = info->disassembler_options; p != NULL; )
10080     {
10081       if (CONST_STRNEQ (p, "x86-64"))
10082         {
10083           address_mode = mode_64bit;
10084           priv.orig_sizeflag = AFLAG | DFLAG;
10085         }
10086       else if (CONST_STRNEQ (p, "i386"))
10087         {
10088           address_mode = mode_32bit;
10089           priv.orig_sizeflag = AFLAG | DFLAG;
10090         }
10091       else if (CONST_STRNEQ (p, "i8086"))
10092         {
10093           address_mode = mode_16bit;
10094           priv.orig_sizeflag = 0;
10095         }
10096       else if (CONST_STRNEQ (p, "intel"))
10097         {
10098           intel_syntax = 1;
10099           if (CONST_STRNEQ (p + 5, "-mnemonic"))
10100             intel_mnemonic = 1;
10101         }
10102       else if (CONST_STRNEQ (p, "att"))
10103         {
10104           intel_syntax = 0;
10105           if (CONST_STRNEQ (p + 3, "-mnemonic"))
10106             intel_mnemonic = 0;
10107         }
10108       else if (CONST_STRNEQ (p, "addr"))
10109         {
10110           if (address_mode == mode_64bit)
10111             {
10112               if (p[4] == '3' && p[5] == '2')
10113                 priv.orig_sizeflag &= ~AFLAG;
10114               else if (p[4] == '6' && p[5] == '4')
10115                 priv.orig_sizeflag |= AFLAG;
10116             }
10117           else
10118             {
10119               if (p[4] == '1' && p[5] == '6')
10120                 priv.orig_sizeflag &= ~AFLAG;
10121               else if (p[4] == '3' && p[5] == '2')
10122                 priv.orig_sizeflag |= AFLAG;
10123             }
10124         }
10125       else if (CONST_STRNEQ (p, "data"))
10126         {
10127           if (p[4] == '1' && p[5] == '6')
10128             priv.orig_sizeflag &= ~DFLAG;
10129           else if (p[4] == '3' && p[5] == '2')
10130             priv.orig_sizeflag |= DFLAG;
10131         }
10132       else if (CONST_STRNEQ (p, "suffix"))
10133         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10134
10135       p = strchr (p, ',');
10136       if (p != NULL)
10137         p++;
10138     }
10139
10140   if (intel_syntax)
10141     {
10142       names64 = intel_names64;
10143       names32 = intel_names32;
10144       names16 = intel_names16;
10145       names8 = intel_names8;
10146       names8rex = intel_names8rex;
10147       names_seg = intel_names_seg;
10148       index64 = intel_index64;
10149       index32 = intel_index32;
10150       index16 = intel_index16;
10151       open_char = '[';
10152       close_char = ']';
10153       separator_char = '+';
10154       scale_char = '*';
10155     }
10156   else
10157     {
10158       names64 = att_names64;
10159       names32 = att_names32;
10160       names16 = att_names16;
10161       names8 = att_names8;
10162       names8rex = att_names8rex;
10163       names_seg = att_names_seg;
10164       index64 = att_index64;
10165       index32 = att_index32;
10166       index16 = att_index16;
10167       open_char = '(';
10168       close_char =  ')';
10169       separator_char = ',';
10170       scale_char = ',';
10171     }
10172
10173   /* The output looks better if we put 7 bytes on a line, since that
10174      puts most long word instructions on a single line.  */
10175   info->bytes_per_line = 7;
10176
10177   info->private_data = &priv;
10178   priv.max_fetched = priv.the_buffer;
10179   priv.insn_start = pc;
10180
10181   obuf[0] = 0;
10182   for (i = 0; i < MAX_OPERANDS; ++i)
10183     {
10184       op_out[i][0] = 0;
10185       op_index[i] = -1;
10186     }
10187
10188   the_info = info;
10189   start_pc = pc;
10190   start_codep = priv.the_buffer;
10191   codep = priv.the_buffer;
10192
10193   if (setjmp (priv.bailout) != 0)
10194     {
10195       const char *name;
10196
10197       /* Getting here means we tried for data but didn't get it.  That
10198          means we have an incomplete instruction of some sort.  Just
10199          print the first byte as a prefix or a .byte pseudo-op.  */
10200       if (codep > priv.the_buffer)
10201         {
10202           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10203           if (name != NULL)
10204             (*info->fprintf_func) (info->stream, "%s", name);
10205           else
10206             {
10207               /* Just print the first byte as a .byte instruction.  */
10208               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10209                                      (unsigned int) priv.the_buffer[0]);
10210             }
10211
10212           return 1;
10213         }
10214
10215       return -1;
10216     }
10217
10218   obufp = obuf;
10219   ckprefix ();
10220
10221   insn_codep = codep;
10222   sizeflag = priv.orig_sizeflag;
10223
10224   FETCH_DATA (info, codep + 1);
10225   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10226
10227   if (((prefixes & PREFIX_FWAIT)
10228        && ((*codep < 0xd8) || (*codep > 0xdf)))
10229       || (rex && rex_used))
10230     {
10231       const char *name;
10232
10233       /* fwait not followed by floating point instruction, or rex followed
10234          by other prefixes.  Print the first prefix.  */
10235       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10236       if (name == NULL)
10237         name = INTERNAL_DISASSEMBLER_ERROR;
10238       (*info->fprintf_func) (info->stream, "%s", name);
10239       return 1;
10240     }
10241
10242   op = 0;
10243   if (*codep == 0x0f)
10244     {
10245       unsigned char threebyte;
10246       FETCH_DATA (info, codep + 2);
10247       threebyte = *++codep;
10248       dp = &dis386_twobyte[threebyte];
10249       need_modrm = twobyte_has_modrm[*codep];
10250       codep++;
10251     }
10252   else
10253     {
10254       dp = &dis386[*codep];
10255       need_modrm = onebyte_has_modrm[*codep];
10256       codep++;
10257     }
10258
10259   if ((prefixes & PREFIX_REPZ))
10260     {
10261       repz_prefix = "repz ";
10262       used_prefixes |= PREFIX_REPZ;
10263     }
10264   else
10265     repz_prefix = NULL;
10266
10267   if ((prefixes & PREFIX_REPNZ))
10268     {
10269       repnz_prefix = "repnz ";
10270       used_prefixes |= PREFIX_REPNZ;
10271     }
10272   else
10273     repnz_prefix = NULL;
10274
10275   if ((prefixes & PREFIX_LOCK))
10276     {
10277       lock_prefix = "lock ";
10278       used_prefixes |= PREFIX_LOCK;
10279     }
10280   else
10281     lock_prefix = NULL;
10282
10283   addr_prefix = NULL;
10284   if (prefixes & PREFIX_ADDR)
10285     {
10286       sizeflag ^= AFLAG;
10287       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10288         {
10289           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10290             addr_prefix = "addr32 ";
10291           else
10292             addr_prefix = "addr16 ";
10293           used_prefixes |= PREFIX_ADDR;
10294         }
10295     }
10296
10297   data_prefix = NULL;
10298   if ((prefixes & PREFIX_DATA))
10299     {
10300       sizeflag ^= DFLAG;
10301       if (dp->op[2].bytemode == cond_jump_mode
10302           && dp->op[0].bytemode == v_mode
10303           && !intel_syntax)
10304         {
10305           if (sizeflag & DFLAG)
10306             data_prefix = "data32 ";
10307           else
10308             data_prefix = "data16 ";
10309           used_prefixes |= PREFIX_DATA;
10310         }
10311     }
10312
10313   if (need_modrm)
10314     {
10315       FETCH_DATA (info, codep + 1);
10316       modrm.mod = (*codep >> 6) & 3;
10317       modrm.reg = (*codep >> 3) & 7;
10318       modrm.rm = *codep & 7;
10319     }
10320
10321   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10322     {
10323       dofloat (sizeflag);
10324     }
10325   else
10326     {
10327       need_vex = 0;
10328       need_vex_reg = 0;
10329       vex_w_done = 0;
10330       dp = get_valid_dis386 (dp, info);
10331       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10332         {
10333           for (i = 0; i < MAX_OPERANDS; ++i)
10334             {
10335               obufp = op_out[i];
10336               op_ad = MAX_OPERANDS - 1 - i;
10337               if (dp->op[i].rtn)
10338                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10339             }
10340         }
10341     }
10342
10343   /* See if any prefixes were not used.  If so, print the first one
10344      separately.  If we don't do this, we'll wind up printing an
10345      instruction stream which does not precisely correspond to the
10346      bytes we are disassembling.  */
10347   if ((prefixes & ~used_prefixes) != 0)
10348     {
10349       const char *name;
10350
10351       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10352       if (name == NULL)
10353         name = INTERNAL_DISASSEMBLER_ERROR;
10354       (*info->fprintf_func) (info->stream, "%s", name);
10355       return 1;
10356     }
10357   if ((rex_original & ~rex_used) || rex_ignored)
10358     {
10359       const char *name;
10360       name = prefix_name (rex_original, priv.orig_sizeflag);
10361       if (name == NULL)
10362         name = INTERNAL_DISASSEMBLER_ERROR;
10363       (*info->fprintf_func) (info->stream, "%s ", name);
10364     }
10365
10366   prefix_obuf[0] = 0;
10367   prefix_obufp = prefix_obuf;
10368   if (lock_prefix)
10369     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10370   if (repz_prefix)
10371     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10372   if (repnz_prefix)
10373     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10374   if (addr_prefix)
10375     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10376   if (data_prefix)
10377     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10378
10379   if (prefix_obuf[0] != 0)
10380     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10381
10382   obufp = mnemonicendp;
10383   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10384     oappend (" ");
10385   oappend (" ");
10386   (*info->fprintf_func) (info->stream, "%s", obuf);
10387
10388   /* The enter and bound instructions are printed with operands in the same
10389      order as the intel book; everything else is printed in reverse order.  */
10390   if (intel_syntax || two_source_ops)
10391     {
10392       bfd_vma riprel;
10393
10394       for (i = 0; i < MAX_OPERANDS; ++i)
10395         op_txt[i] = op_out[i];
10396
10397       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10398         {
10399           op_ad = op_index[i];
10400           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10401           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10402           riprel = op_riprel[i];
10403           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10404           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10405         }
10406     }
10407   else
10408     {
10409       for (i = 0; i < MAX_OPERANDS; ++i)
10410         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10411     }
10412
10413   needcomma = 0;
10414   for (i = 0; i < MAX_OPERANDS; ++i)
10415     if (*op_txt[i])
10416       {
10417         if (needcomma)
10418           (*info->fprintf_func) (info->stream, ",");
10419         if (op_index[i] != -1 && !op_riprel[i])
10420           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10421         else
10422           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10423         needcomma = 1;
10424       }
10425
10426   for (i = 0; i < MAX_OPERANDS; i++)
10427     if (op_index[i] != -1 && op_riprel[i])
10428       {
10429         (*info->fprintf_func) (info->stream, "        # ");
10430         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10431                                                 + op_address[op_index[i]]), info);
10432         break;
10433       }
10434   return codep - priv.the_buffer;
10435 }
10436
10437 static const char *float_mem[] = {
10438   /* d8 */
10439   "fadd{s|}",
10440   "fmul{s|}",
10441   "fcom{s|}",
10442   "fcomp{s|}",
10443   "fsub{s|}",
10444   "fsubr{s|}",
10445   "fdiv{s|}",
10446   "fdivr{s|}",
10447   /* d9 */
10448   "fld{s|}",
10449   "(bad)",
10450   "fst{s|}",
10451   "fstp{s|}",
10452   "fldenvIC",
10453   "fldcw",
10454   "fNstenvIC",
10455   "fNstcw",
10456   /* da */
10457   "fiadd{l|}",
10458   "fimul{l|}",
10459   "ficom{l|}",
10460   "ficomp{l|}",
10461   "fisub{l|}",
10462   "fisubr{l|}",
10463   "fidiv{l|}",
10464   "fidivr{l|}",
10465   /* db */
10466   "fild{l|}",
10467   "fisttp{l|}",
10468   "fist{l|}",
10469   "fistp{l|}",
10470   "(bad)",
10471   "fld{t||t|}",
10472   "(bad)",
10473   "fstp{t||t|}",
10474   /* dc */
10475   "fadd{l|}",
10476   "fmul{l|}",
10477   "fcom{l|}",
10478   "fcomp{l|}",
10479   "fsub{l|}",
10480   "fsubr{l|}",
10481   "fdiv{l|}",
10482   "fdivr{l|}",
10483   /* dd */
10484   "fld{l|}",
10485   "fisttp{ll|}",
10486   "fst{l||}",
10487   "fstp{l|}",
10488   "frstorIC",
10489   "(bad)",
10490   "fNsaveIC",
10491   "fNstsw",
10492   /* de */
10493   "fiadd",
10494   "fimul",
10495   "ficom",
10496   "ficomp",
10497   "fisub",
10498   "fisubr",
10499   "fidiv",
10500   "fidivr",
10501   /* df */
10502   "fild",
10503   "fisttp",
10504   "fist",
10505   "fistp",
10506   "fbld",
10507   "fild{ll|}",
10508   "fbstp",
10509   "fistp{ll|}",
10510 };
10511
10512 static const unsigned char float_mem_mode[] = {
10513   /* d8 */
10514   d_mode,
10515   d_mode,
10516   d_mode,
10517   d_mode,
10518   d_mode,
10519   d_mode,
10520   d_mode,
10521   d_mode,
10522   /* d9 */
10523   d_mode,
10524   0,
10525   d_mode,
10526   d_mode,
10527   0,
10528   w_mode,
10529   0,
10530   w_mode,
10531   /* da */
10532   d_mode,
10533   d_mode,
10534   d_mode,
10535   d_mode,
10536   d_mode,
10537   d_mode,
10538   d_mode,
10539   d_mode,
10540   /* db */
10541   d_mode,
10542   d_mode,
10543   d_mode,
10544   d_mode,
10545   0,
10546   t_mode,
10547   0,
10548   t_mode,
10549   /* dc */
10550   q_mode,
10551   q_mode,
10552   q_mode,
10553   q_mode,
10554   q_mode,
10555   q_mode,
10556   q_mode,
10557   q_mode,
10558   /* dd */
10559   q_mode,
10560   q_mode,
10561   q_mode,
10562   q_mode,
10563   0,
10564   0,
10565   0,
10566   w_mode,
10567   /* de */
10568   w_mode,
10569   w_mode,
10570   w_mode,
10571   w_mode,
10572   w_mode,
10573   w_mode,
10574   w_mode,
10575   w_mode,
10576   /* df */
10577   w_mode,
10578   w_mode,
10579   w_mode,
10580   w_mode,
10581   t_mode,
10582   q_mode,
10583   t_mode,
10584   q_mode
10585 };
10586
10587 #define ST { OP_ST, 0 }
10588 #define STi { OP_STi, 0 }
10589
10590 #define FGRPd9_2 NULL, { { NULL, 0 } }
10591 #define FGRPd9_4 NULL, { { NULL, 1 } }
10592 #define FGRPd9_5 NULL, { { NULL, 2 } }
10593 #define FGRPd9_6 NULL, { { NULL, 3 } }
10594 #define FGRPd9_7 NULL, { { NULL, 4 } }
10595 #define FGRPda_5 NULL, { { NULL, 5 } }
10596 #define FGRPdb_4 NULL, { { NULL, 6 } }
10597 #define FGRPde_3 NULL, { { NULL, 7 } }
10598 #define FGRPdf_4 NULL, { { NULL, 8 } }
10599
10600 static const struct dis386 float_reg[][8] = {
10601   /* d8 */
10602   {
10603     { "fadd",   { ST, STi } },
10604     { "fmul",   { ST, STi } },
10605     { "fcom",   { STi } },
10606     { "fcomp",  { STi } },
10607     { "fsub",   { ST, STi } },
10608     { "fsubr",  { ST, STi } },
10609     { "fdiv",   { ST, STi } },
10610     { "fdivr",  { ST, STi } },
10611   },
10612   /* d9 */
10613   {
10614     { "fld",    { STi } },
10615     { "fxch",   { STi } },
10616     { FGRPd9_2 },
10617     { "(bad)",  { XX } },
10618     { FGRPd9_4 },
10619     { FGRPd9_5 },
10620     { FGRPd9_6 },
10621     { FGRPd9_7 },
10622   },
10623   /* da */
10624   {
10625     { "fcmovb", { ST, STi } },
10626     { "fcmove", { ST, STi } },
10627     { "fcmovbe",{ ST, STi } },
10628     { "fcmovu", { ST, STi } },
10629     { "(bad)",  { XX } },
10630     { FGRPda_5 },
10631     { "(bad)",  { XX } },
10632     { "(bad)",  { XX } },
10633   },
10634   /* db */
10635   {
10636     { "fcmovnb",{ ST, STi } },
10637     { "fcmovne",{ ST, STi } },
10638     { "fcmovnbe",{ ST, STi } },
10639     { "fcmovnu",{ ST, STi } },
10640     { FGRPdb_4 },
10641     { "fucomi", { ST, STi } },
10642     { "fcomi",  { ST, STi } },
10643     { "(bad)",  { XX } },
10644   },
10645   /* dc */
10646   {
10647     { "fadd",   { STi, ST } },
10648     { "fmul",   { STi, ST } },
10649     { "(bad)",  { XX } },
10650     { "(bad)",  { XX } },
10651     { "fsub!M", { STi, ST } },
10652     { "fsubM",  { STi, ST } },
10653     { "fdiv!M", { STi, ST } },
10654     { "fdivM",  { STi, ST } },
10655   },
10656   /* dd */
10657   {
10658     { "ffree",  { STi } },
10659     { "(bad)",  { XX } },
10660     { "fst",    { STi } },
10661     { "fstp",   { STi } },
10662     { "fucom",  { STi } },
10663     { "fucomp", { STi } },
10664     { "(bad)",  { XX } },
10665     { "(bad)",  { XX } },
10666   },
10667   /* de */
10668   {
10669     { "faddp",  { STi, ST } },
10670     { "fmulp",  { STi, ST } },
10671     { "(bad)",  { XX } },
10672     { FGRPde_3 },
10673     { "fsub!Mp", { STi, ST } },
10674     { "fsubMp", { STi, ST } },
10675     { "fdiv!Mp", { STi, ST } },
10676     { "fdivMp", { STi, ST } },
10677   },
10678   /* df */
10679   {
10680     { "ffreep", { STi } },
10681     { "(bad)",  { XX } },
10682     { "(bad)",  { XX } },
10683     { "(bad)",  { XX } },
10684     { FGRPdf_4 },
10685     { "fucomip", { ST, STi } },
10686     { "fcomip", { ST, STi } },
10687     { "(bad)",  { XX } },
10688   },
10689 };
10690
10691 static char *fgrps[][8] = {
10692   /* d9_2  0 */
10693   {
10694     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10695   },
10696
10697   /* d9_4  1 */
10698   {
10699     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10700   },
10701
10702   /* d9_5  2 */
10703   {
10704     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10705   },
10706
10707   /* d9_6  3 */
10708   {
10709     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10710   },
10711
10712   /* d9_7  4 */
10713   {
10714     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10715   },
10716
10717   /* da_5  5 */
10718   {
10719     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10720   },
10721
10722   /* db_4  6 */
10723   {
10724     "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10725     "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10726   },
10727
10728   /* de_3  7 */
10729   {
10730     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10731   },
10732
10733   /* df_4  8 */
10734   {
10735     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10736   },
10737 };
10738
10739 static void
10740 swap_operand (void)
10741 {
10742   mnemonicendp[0] = '.';
10743   mnemonicendp[1] = 's';
10744   mnemonicendp += 2;
10745 }
10746
10747 static void
10748 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10749                int sizeflag ATTRIBUTE_UNUSED)
10750 {
10751   /* Skip mod/rm byte.  */
10752   MODRM_CHECK;
10753   codep++;
10754 }
10755
10756 static void
10757 dofloat (int sizeflag)
10758 {
10759   const struct dis386 *dp;
10760   unsigned char floatop;
10761
10762   floatop = codep[-1];
10763
10764   if (modrm.mod != 3)
10765     {
10766       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10767
10768       putop (float_mem[fp_indx], sizeflag);
10769       obufp = op_out[0];
10770       op_ad = 2;
10771       OP_E (float_mem_mode[fp_indx], sizeflag);
10772       return;
10773     }
10774   /* Skip mod/rm byte.  */
10775   MODRM_CHECK;
10776   codep++;
10777
10778   dp = &float_reg[floatop - 0xd8][modrm.reg];
10779   if (dp->name == NULL)
10780     {
10781       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10782
10783       /* Instruction fnstsw is only one with strange arg.  */
10784       if (floatop == 0xdf && codep[-1] == 0xe0)
10785         strcpy (op_out[0], names16[0]);
10786     }
10787   else
10788     {
10789       putop (dp->name, sizeflag);
10790
10791       obufp = op_out[0];
10792       op_ad = 2;
10793       if (dp->op[0].rtn)
10794         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10795
10796       obufp = op_out[1];
10797       op_ad = 1;
10798       if (dp->op[1].rtn)
10799         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10800     }
10801 }
10802
10803 static void
10804 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10805 {
10806   oappend ("%st" + intel_syntax);
10807 }
10808
10809 static void
10810 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10811 {
10812   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10813   oappend (scratchbuf + intel_syntax);
10814 }
10815
10816 /* Capital letters in template are macros.  */
10817 static int
10818 putop (const char *template, int sizeflag)
10819 {
10820   const char *p;
10821   int alt = 0;
10822   int cond = 1;
10823   unsigned int l = 0, len = 1;
10824   char last[4];
10825
10826 #define SAVE_LAST(c)                    \
10827   if (l < len && l < sizeof (last))     \
10828     last[l++] = c;                      \
10829   else                                  \
10830     abort ();
10831
10832   for (p = template; *p; p++)
10833     {
10834       switch (*p)
10835         {
10836         default:
10837           *obufp++ = *p;
10838           break;
10839         case '%':
10840           len++;
10841           break;
10842         case '!':
10843           cond = 0;
10844           break;
10845         case '{':
10846           alt = 0;
10847           if (intel_syntax)
10848             {
10849               while (*++p != '|')
10850                 if (*p == '}' || *p == '\0')
10851                   abort ();
10852             }
10853           /* Fall through.  */
10854         case 'I':
10855           alt = 1;
10856           continue;
10857         case '|':
10858           while (*++p != '}')
10859             {
10860               if (*p == '\0')
10861                 abort ();
10862             }
10863           break;
10864         case '}':
10865           break;
10866         case 'A':
10867           if (intel_syntax)
10868             break;
10869           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10870             *obufp++ = 'b';
10871           break;
10872         case 'B':
10873           if (intel_syntax)
10874             break;
10875           if (sizeflag & SUFFIX_ALWAYS)
10876             *obufp++ = 'b';
10877           break;
10878         case 'C':
10879           if (intel_syntax && !alt)
10880             break;
10881           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10882             {
10883               if (sizeflag & DFLAG)
10884                 *obufp++ = intel_syntax ? 'd' : 'l';
10885               else
10886                 *obufp++ = intel_syntax ? 'w' : 's';
10887               used_prefixes |= (prefixes & PREFIX_DATA);
10888             }
10889           break;
10890         case 'D':
10891           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10892             break;
10893           USED_REX (REX_W);
10894           if (modrm.mod == 3)
10895             {
10896               if (rex & REX_W)
10897                 *obufp++ = 'q';
10898               else if (sizeflag & DFLAG)
10899                 *obufp++ = intel_syntax ? 'd' : 'l';
10900               else
10901                 *obufp++ = 'w';
10902               used_prefixes |= (prefixes & PREFIX_DATA);
10903             }
10904           else
10905             *obufp++ = 'w';
10906           break;
10907         case 'E':               /* For jcxz/jecxz */
10908           if (address_mode == mode_64bit)
10909             {
10910               if (sizeflag & AFLAG)
10911                 *obufp++ = 'r';
10912               else
10913                 *obufp++ = 'e';
10914             }
10915           else
10916             if (sizeflag & AFLAG)
10917               *obufp++ = 'e';
10918           used_prefixes |= (prefixes & PREFIX_ADDR);
10919           break;
10920         case 'F':
10921           if (intel_syntax)
10922             break;
10923           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10924             {
10925               if (sizeflag & AFLAG)
10926                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10927               else
10928                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10929               used_prefixes |= (prefixes & PREFIX_ADDR);
10930             }
10931           break;
10932         case 'G':
10933           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10934             break;
10935           if ((rex & REX_W) || (sizeflag & DFLAG))
10936             *obufp++ = 'l';
10937           else
10938             *obufp++ = 'w';
10939           if (!(rex & REX_W))
10940             used_prefixes |= (prefixes & PREFIX_DATA);
10941           break;
10942         case 'H':
10943           if (intel_syntax)
10944             break;
10945           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10946               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10947             {
10948               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10949               *obufp++ = ',';
10950               *obufp++ = 'p';
10951               if (prefixes & PREFIX_DS)
10952                 *obufp++ = 't';
10953               else
10954                 *obufp++ = 'n';
10955             }
10956           break;
10957         case 'J':
10958           if (intel_syntax)
10959             break;
10960           *obufp++ = 'l';
10961           break;
10962         case 'K':
10963           USED_REX (REX_W);
10964           if (rex & REX_W)
10965             *obufp++ = 'q';
10966           else
10967             *obufp++ = 'd';
10968           break;
10969         case 'Z':
10970           if (intel_syntax)
10971             break;
10972           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10973             {
10974               *obufp++ = 'q';
10975               break;
10976             }
10977           /* Fall through.  */
10978           goto case_L;
10979         case 'L':
10980           if (l != 0 || len != 1)
10981             {
10982               SAVE_LAST (*p);
10983               break;
10984             }
10985 case_L:
10986           if (intel_syntax)
10987             break;
10988           if (sizeflag & SUFFIX_ALWAYS)
10989             *obufp++ = 'l';
10990           break;
10991         case 'M':
10992           if (intel_mnemonic != cond)
10993             *obufp++ = 'r';
10994           break;
10995         case 'N':
10996           if ((prefixes & PREFIX_FWAIT) == 0)
10997             *obufp++ = 'n';
10998           else
10999             used_prefixes |= PREFIX_FWAIT;
11000           break;
11001         case 'O':
11002           USED_REX (REX_W);
11003           if (rex & REX_W)
11004             *obufp++ = 'o';
11005           else if (intel_syntax && (sizeflag & DFLAG))
11006             *obufp++ = 'q';
11007           else
11008             *obufp++ = 'd';
11009           if (!(rex & REX_W))
11010             used_prefixes |= (prefixes & PREFIX_DATA);
11011           break;
11012         case 'T':
11013           if (intel_syntax)
11014             break;
11015           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11016             {
11017               *obufp++ = 'q';
11018               break;
11019             }
11020           /* Fall through.  */
11021         case 'P':
11022           if (intel_syntax)
11023             break;
11024           if ((prefixes & PREFIX_DATA)
11025               || (rex & REX_W)
11026               || (sizeflag & SUFFIX_ALWAYS))
11027             {
11028               USED_REX (REX_W);
11029               if (rex & REX_W)
11030                 *obufp++ = 'q';
11031               else
11032                 {
11033                    if (sizeflag & DFLAG)
11034                       *obufp++ = 'l';
11035                    else
11036                      *obufp++ = 'w';
11037                 }
11038               used_prefixes |= (prefixes & PREFIX_DATA);
11039             }
11040           break;
11041         case 'U':
11042           if (intel_syntax)
11043             break;
11044           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11045             {
11046               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11047                 *obufp++ = 'q';
11048               break;
11049             }
11050           /* Fall through.  */
11051           goto case_Q;
11052         case 'Q':
11053           if (l == 0 && len == 1)
11054             {
11055 case_Q:
11056               if (intel_syntax && !alt)
11057                 break;
11058               USED_REX (REX_W);
11059               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11060                 {
11061                   if (rex & REX_W)
11062                     *obufp++ = 'q';
11063                   else
11064                     {
11065                       if (sizeflag & DFLAG)
11066                         *obufp++ = intel_syntax ? 'd' : 'l';
11067                       else
11068                         *obufp++ = 'w';
11069                     }
11070                   used_prefixes |= (prefixes & PREFIX_DATA);
11071                 }
11072             }
11073           else
11074             {
11075               if (l != 1 || len != 2 || last[0] != 'L')
11076                 {
11077                   SAVE_LAST (*p);
11078                   break;
11079                 }
11080               if (intel_syntax
11081                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11082                 break;
11083               if ((rex & REX_W))
11084                 {
11085                   USED_REX (REX_W);
11086                   *obufp++ = 'q';
11087                 }
11088               else
11089                 *obufp++ = 'l';
11090             }
11091           break;
11092         case 'R':
11093           USED_REX (REX_W);
11094           if (rex & REX_W)
11095             *obufp++ = 'q';
11096           else if (sizeflag & DFLAG)
11097             {
11098               if (intel_syntax)
11099                   *obufp++ = 'd';
11100               else
11101                   *obufp++ = 'l';
11102             }
11103           else
11104             *obufp++ = 'w';
11105           if (intel_syntax && !p[1]
11106               && ((rex & REX_W) || (sizeflag & DFLAG)))
11107             *obufp++ = 'e';
11108           if (!(rex & REX_W))
11109             used_prefixes |= (prefixes & PREFIX_DATA);
11110           break;
11111         case 'V':
11112           if (intel_syntax)
11113             break;
11114           if (address_mode == mode_64bit && (sizeflag & DFLAG))
11115             {
11116               if (sizeflag & SUFFIX_ALWAYS)
11117                 *obufp++ = 'q';
11118               break;
11119             }
11120           /* Fall through.  */
11121         case 'S':
11122           if (intel_syntax)
11123             break;
11124           if (sizeflag & SUFFIX_ALWAYS)
11125             {
11126               if (rex & REX_W)
11127                 *obufp++ = 'q';
11128               else
11129                 {
11130                   if (sizeflag & DFLAG)
11131                     *obufp++ = 'l';
11132                   else
11133                     *obufp++ = 'w';
11134                   used_prefixes |= (prefixes & PREFIX_DATA);
11135                 }
11136             }
11137           break;
11138         case 'X':
11139           if (l != 0 || len != 1)
11140             {
11141               SAVE_LAST (*p);
11142               break;
11143             }
11144           if (need_vex && vex.prefix)
11145             {
11146               if (vex.prefix == DATA_PREFIX_OPCODE)
11147                 *obufp++ = 'd';
11148               else
11149                 *obufp++ = 's';
11150             }
11151           else if (prefixes & PREFIX_DATA)
11152             *obufp++ = 'd';
11153           else
11154             *obufp++ = 's';
11155           used_prefixes |= (prefixes & PREFIX_DATA);
11156           break;
11157         case 'Y':
11158           if (l == 0 && len == 1)
11159             {
11160               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11161                 break;
11162               if (rex & REX_W)
11163                 {
11164                   USED_REX (REX_W);
11165                   *obufp++ = 'q';
11166                 }
11167               break;
11168             }
11169           else
11170             {
11171               if (l != 1 || len != 2 || last[0] != 'X')
11172                 {
11173                   SAVE_LAST (*p);
11174                   break;
11175                 }
11176               if (!need_vex)
11177                 abort ();
11178               if (intel_syntax
11179                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11180                 break;
11181               switch (vex.length)
11182                 {
11183                 case 128:
11184                   *obufp++ = 'x';
11185                   break;
11186                 case 256:
11187                   *obufp++ = 'y';
11188                   break;
11189                 default:
11190                   abort ();
11191                 }
11192             }
11193           break;
11194         case 'W':
11195           /* operand size flag for cwtl, cbtw */
11196           USED_REX (REX_W);
11197           if (rex & REX_W)
11198             {
11199               if (intel_syntax)
11200                 *obufp++ = 'd';
11201               else
11202                 *obufp++ = 'l';
11203             }
11204           else if (sizeflag & DFLAG)
11205             *obufp++ = 'w';
11206           else
11207             *obufp++ = 'b';
11208           if (!(rex & REX_W))
11209             used_prefixes |= (prefixes & PREFIX_DATA);
11210           break;
11211         }
11212       alt = 0;
11213     }
11214   *obufp = 0;
11215   mnemonicendp = obufp;
11216   return 0;
11217 }
11218
11219 static void
11220 oappend (const char *s)
11221 {
11222   obufp = stpcpy (obufp, s);
11223 }
11224
11225 static void
11226 append_seg (void)
11227 {
11228   if (prefixes & PREFIX_CS)
11229     {
11230       used_prefixes |= PREFIX_CS;
11231       oappend ("%cs:" + intel_syntax);
11232     }
11233   if (prefixes & PREFIX_DS)
11234     {
11235       used_prefixes |= PREFIX_DS;
11236       oappend ("%ds:" + intel_syntax);
11237     }
11238   if (prefixes & PREFIX_SS)
11239     {
11240       used_prefixes |= PREFIX_SS;
11241       oappend ("%ss:" + intel_syntax);
11242     }
11243   if (prefixes & PREFIX_ES)
11244     {
11245       used_prefixes |= PREFIX_ES;
11246       oappend ("%es:" + intel_syntax);
11247     }
11248   if (prefixes & PREFIX_FS)
11249     {
11250       used_prefixes |= PREFIX_FS;
11251       oappend ("%fs:" + intel_syntax);
11252     }
11253   if (prefixes & PREFIX_GS)
11254     {
11255       used_prefixes |= PREFIX_GS;
11256       oappend ("%gs:" + intel_syntax);
11257     }
11258 }
11259
11260 static void
11261 OP_indirE (int bytemode, int sizeflag)
11262 {
11263   if (!intel_syntax)
11264     oappend ("*");
11265   OP_E (bytemode, sizeflag);
11266 }
11267
11268 static void
11269 print_operand_value (char *buf, int hex, bfd_vma disp)
11270 {
11271   if (address_mode == mode_64bit)
11272     {
11273       if (hex)
11274         {
11275           char tmp[30];
11276           int i;
11277           buf[0] = '0';
11278           buf[1] = 'x';
11279           sprintf_vma (tmp, disp);
11280           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11281           strcpy (buf + 2, tmp + i);
11282         }
11283       else
11284         {
11285           bfd_signed_vma v = disp;
11286           char tmp[30];
11287           int i;
11288           if (v < 0)
11289             {
11290               *(buf++) = '-';
11291               v = -disp;
11292               /* Check for possible overflow on 0x8000000000000000.  */
11293               if (v < 0)
11294                 {
11295                   strcpy (buf, "9223372036854775808");
11296                   return;
11297                 }
11298             }
11299           if (!v)
11300             {
11301               strcpy (buf, "0");
11302               return;
11303             }
11304
11305           i = 0;
11306           tmp[29] = 0;
11307           while (v)
11308             {
11309               tmp[28 - i] = (v % 10) + '0';
11310               v /= 10;
11311               i++;
11312             }
11313           strcpy (buf, tmp + 29 - i);
11314         }
11315     }
11316   else
11317     {
11318       if (hex)
11319         sprintf (buf, "0x%x", (unsigned int) disp);
11320       else
11321         sprintf (buf, "%d", (int) disp);
11322     }
11323 }
11324
11325 /* Put DISP in BUF as signed hex number.  */
11326
11327 static void
11328 print_displacement (char *buf, bfd_vma disp)
11329 {
11330   bfd_signed_vma val = disp;
11331   char tmp[30];
11332   int i, j = 0;
11333
11334   if (val < 0)
11335     {
11336       buf[j++] = '-';
11337       val = -disp;
11338
11339       /* Check for possible overflow.  */
11340       if (val < 0)
11341         {
11342           switch (address_mode)
11343             {
11344             case mode_64bit:
11345               strcpy (buf + j, "0x8000000000000000");
11346               break;
11347             case mode_32bit:
11348               strcpy (buf + j, "0x80000000");
11349               break;
11350             case mode_16bit:
11351               strcpy (buf + j, "0x8000");
11352               break;
11353             }
11354           return;
11355         }
11356     }
11357
11358   buf[j++] = '0';
11359   buf[j++] = 'x';
11360
11361   sprintf_vma (tmp, (bfd_vma) val);
11362   for (i = 0; tmp[i] == '0'; i++)
11363     continue;
11364   if (tmp[i] == '\0')
11365     i--;
11366   strcpy (buf + j, tmp + i);
11367 }
11368
11369 static void
11370 intel_operand_size (int bytemode, int sizeflag)
11371 {
11372   switch (bytemode)
11373     {
11374     case b_mode:
11375     case b_swap_mode:
11376     case dqb_mode:
11377       oappend ("BYTE PTR ");
11378       break;
11379     case w_mode:
11380     case dqw_mode:
11381       oappend ("WORD PTR ");
11382       break;
11383     case stack_v_mode:
11384       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11385         {
11386           oappend ("QWORD PTR ");
11387           used_prefixes |= (prefixes & PREFIX_DATA);
11388           break;
11389         }
11390       /* FALLTHRU */
11391     case v_mode:
11392     case v_swap_mode:
11393     case dq_mode:
11394       USED_REX (REX_W);
11395       if (rex & REX_W)
11396         oappend ("QWORD PTR ");
11397       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11398         oappend ("DWORD PTR ");
11399       else
11400         oappend ("WORD PTR ");
11401       used_prefixes |= (prefixes & PREFIX_DATA);
11402       break;
11403     case z_mode:
11404       if ((rex & REX_W) || (sizeflag & DFLAG))
11405         *obufp++ = 'D';
11406       oappend ("WORD PTR ");
11407       if (!(rex & REX_W))
11408         used_prefixes |= (prefixes & PREFIX_DATA);
11409       break;
11410     case a_mode:
11411       if (sizeflag & DFLAG)
11412         oappend ("QWORD PTR ");
11413       else
11414         oappend ("DWORD PTR ");
11415       used_prefixes |= (prefixes & PREFIX_DATA);
11416       break;
11417     case d_mode:
11418     case dqd_mode:
11419       oappend ("DWORD PTR ");
11420       break;
11421     case q_mode:
11422     case q_swap_mode:
11423       oappend ("QWORD PTR ");
11424       break;
11425     case m_mode:
11426       if (address_mode == mode_64bit)
11427         oappend ("QWORD PTR ");
11428       else
11429         oappend ("DWORD PTR ");
11430       break;
11431     case f_mode:
11432       if (sizeflag & DFLAG)
11433         oappend ("FWORD PTR ");
11434       else
11435         oappend ("DWORD PTR ");
11436       used_prefixes |= (prefixes & PREFIX_DATA);
11437       break;
11438     case t_mode:
11439       oappend ("TBYTE PTR ");
11440       break;
11441     case x_mode:
11442     case x_swap_mode:
11443       if (need_vex)
11444         {
11445           switch (vex.length)
11446             {
11447             case 128:
11448               oappend ("XMMWORD PTR ");
11449               break;
11450             case 256:
11451               oappend ("YMMWORD PTR ");
11452               break;
11453             default:
11454               abort ();
11455             }
11456         }
11457       else
11458         oappend ("XMMWORD PTR ");
11459       break;
11460     case xmm_mode:
11461       oappend ("XMMWORD PTR ");
11462       break;
11463     case xmmq_mode:
11464       if (!need_vex)
11465         abort ();
11466
11467       switch (vex.length)
11468         {
11469         case 128:
11470           oappend ("QWORD PTR ");
11471           break;
11472         case 256:
11473           oappend ("XMMWORD PTR ");
11474           break;
11475         default:
11476           abort ();
11477         }
11478       break;
11479     case ymmq_mode:
11480       if (!need_vex)
11481         abort ();
11482
11483       switch (vex.length)
11484         {
11485         case 128:
11486           oappend ("QWORD PTR ");
11487           break;
11488         case 256:
11489           oappend ("YMMWORD PTR ");
11490           break;
11491         default:
11492           abort ();
11493         }
11494       break;
11495     case o_mode:
11496       oappend ("OWORD PTR ");
11497       break;
11498     default:
11499       break;
11500     }
11501 }
11502
11503 static void
11504 OP_E_register (int bytemode, int sizeflag)
11505 {
11506   int reg = modrm.rm;
11507   const char **names;
11508
11509   USED_REX (REX_B);
11510   if ((rex & REX_B))
11511     reg += 8;
11512
11513   if ((sizeflag & SUFFIX_ALWAYS)
11514       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11515     swap_operand ();
11516
11517   switch (bytemode)
11518     {
11519     case b_mode:
11520     case b_swap_mode:
11521       USED_REX (0);
11522       if (rex)
11523         names = names8rex;
11524       else
11525         names = names8;
11526       break;
11527     case w_mode:
11528       names = names16;
11529       break;
11530     case d_mode:
11531       names = names32;
11532       break;
11533     case q_mode:
11534       names = names64;
11535       break;
11536     case m_mode:
11537       names = address_mode == mode_64bit ? names64 : names32;
11538       break;
11539     case stack_v_mode:
11540       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11541         {
11542           names = names64;
11543           used_prefixes |= (prefixes & PREFIX_DATA);
11544           break;
11545         }
11546       bytemode = v_mode;
11547       /* FALLTHRU */
11548     case v_mode:
11549     case v_swap_mode:
11550     case dq_mode:
11551     case dqb_mode:
11552     case dqd_mode:
11553     case dqw_mode:
11554       USED_REX (REX_W);
11555       if (rex & REX_W)
11556         names = names64;
11557       else if ((sizeflag & DFLAG)
11558                || (bytemode != v_mode
11559                    && bytemode != v_swap_mode))
11560         names = names32;
11561       else
11562         names = names16;
11563       used_prefixes |= (prefixes & PREFIX_DATA);
11564       break;
11565     case 0:
11566       return;
11567     default:
11568       oappend (INTERNAL_DISASSEMBLER_ERROR);
11569       return;
11570     }
11571   oappend (names[reg]);
11572 }
11573
11574 static void
11575 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11576 {
11577   bfd_vma disp = 0;
11578   int add = (rex & REX_B) ? 8 : 0;
11579   int riprel = 0;
11580
11581   USED_REX (REX_B);
11582   if (intel_syntax)
11583     intel_operand_size (bytemode, sizeflag);
11584   append_seg ();
11585
11586   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11587     {
11588       /* 32/64 bit address mode */
11589       int havedisp;
11590       int havesib;
11591       int havebase;
11592       int haveindex;
11593       int needindex;
11594       int base, rbase;
11595       int index = 0;
11596       int scale = 0;
11597
11598       havesib = 0;
11599       havebase = 1;
11600       haveindex = 0;
11601       base = modrm.rm;
11602
11603       if (base == 4)
11604         {
11605           havesib = 1;
11606           FETCH_DATA (the_info, codep + 1);
11607           index = (*codep >> 3) & 7;
11608           scale = (*codep >> 6) & 3;
11609           base = *codep & 7;
11610           USED_REX (REX_X);
11611           if (rex & REX_X)
11612             index += 8;
11613           haveindex = index != 4;
11614           codep++;
11615         }
11616       rbase = base + add;
11617
11618       /* If we have a DREX byte, skip it now
11619          (it has already been handled) */
11620       if (has_drex)
11621         {
11622           FETCH_DATA (the_info, codep + 1);
11623           codep++;
11624         }
11625
11626       switch (modrm.mod)
11627         {
11628         case 0:
11629           if (base == 5)
11630             {
11631               havebase = 0;
11632               if (address_mode == mode_64bit && !havesib)
11633                 riprel = 1;
11634               disp = get32s ();
11635             }
11636           break;
11637         case 1:
11638           FETCH_DATA (the_info, codep + 1);
11639           disp = *codep++;
11640           if ((disp & 0x80) != 0)
11641             disp -= 0x100;
11642           break;
11643         case 2:
11644           disp = get32s ();
11645           break;
11646         }
11647
11648       /* In 32bit mode, we need index register to tell [offset] from
11649          [eiz*1 + offset].  */
11650       needindex = (havesib
11651                    && !havebase
11652                    && !haveindex
11653                    && address_mode == mode_32bit);
11654       havedisp = (havebase
11655                   || needindex
11656                   || (havesib && (haveindex || scale != 0)));
11657
11658       if (!intel_syntax)
11659         if (modrm.mod != 0 || base == 5)
11660           {
11661             if (havedisp || riprel)
11662               print_displacement (scratchbuf, disp);
11663             else
11664               print_operand_value (scratchbuf, 1, disp);
11665             oappend (scratchbuf);
11666             if (riprel)
11667               {
11668                 set_op (disp, 1);
11669                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11670               }
11671           }
11672
11673       if (havebase || haveindex || riprel)
11674         used_prefixes |= PREFIX_ADDR;
11675
11676       if (havedisp || (intel_syntax && riprel))
11677         {
11678           *obufp++ = open_char;
11679           if (intel_syntax && riprel)
11680             {
11681               set_op (disp, 1);
11682               oappend (sizeflag & AFLAG ? "rip" : "eip");
11683             }
11684           *obufp = '\0';
11685           if (havebase)
11686             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11687                      ? names64[rbase] : names32[rbase]);
11688           if (havesib)
11689             {
11690               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11691                  print index to tell base + index from base.  */
11692               if (scale != 0
11693                   || needindex
11694                   || haveindex
11695                   || (havebase && base != ESP_REG_NUM))
11696                 {
11697                   if (!intel_syntax || havebase)
11698                     {
11699                       *obufp++ = separator_char;
11700                       *obufp = '\0';
11701                     }
11702                   if (haveindex)
11703                     oappend (address_mode == mode_64bit
11704                              && (sizeflag & AFLAG)
11705                              ? names64[index] : names32[index]);
11706                   else
11707                     oappend (address_mode == mode_64bit
11708                              && (sizeflag & AFLAG)
11709                              ? index64 : index32);
11710
11711                   *obufp++ = scale_char;
11712                   *obufp = '\0';
11713                   sprintf (scratchbuf, "%d", 1 << scale);
11714                   oappend (scratchbuf);
11715                 }
11716             }
11717           if (intel_syntax
11718               && (disp || modrm.mod != 0 || base == 5))
11719             {
11720               if (!havedisp || (bfd_signed_vma) disp >= 0)
11721                 {
11722                   *obufp++ = '+';
11723                   *obufp = '\0';
11724                 }
11725               else if (modrm.mod != 1)
11726                 {
11727                   *obufp++ = '-';
11728                   *obufp = '\0';
11729                   disp = - (bfd_signed_vma) disp;
11730                 }
11731
11732               if (havedisp)
11733                 print_displacement (scratchbuf, disp);
11734               else
11735                 print_operand_value (scratchbuf, 1, disp);
11736               oappend (scratchbuf);
11737             }
11738
11739           *obufp++ = close_char;
11740           *obufp = '\0';
11741         }
11742       else if (intel_syntax)
11743         {
11744           if (modrm.mod != 0 || base == 5)
11745             {
11746               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11747                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11748                 ;
11749               else
11750                 {
11751                   oappend (names_seg[ds_reg - es_reg]);
11752                   oappend (":");
11753                 }
11754               print_operand_value (scratchbuf, 1, disp);
11755               oappend (scratchbuf);
11756             }
11757         }
11758     }
11759   else
11760     { /* 16 bit address mode */
11761       switch (modrm.mod)
11762         {
11763         case 0:
11764           if (modrm.rm == 6)
11765             {
11766               disp = get16 ();
11767               if ((disp & 0x8000) != 0)
11768                 disp -= 0x10000;
11769             }
11770           break;
11771         case 1:
11772           FETCH_DATA (the_info, codep + 1);
11773           disp = *codep++;
11774           if ((disp & 0x80) != 0)
11775             disp -= 0x100;
11776           break;
11777         case 2:
11778           disp = get16 ();
11779           if ((disp & 0x8000) != 0)
11780             disp -= 0x10000;
11781           break;
11782         }
11783
11784       if (!intel_syntax)
11785         if (modrm.mod != 0 || modrm.rm == 6)
11786           {
11787             print_displacement (scratchbuf, disp);
11788             oappend (scratchbuf);
11789           }
11790
11791       if (modrm.mod != 0 || modrm.rm != 6)
11792         {
11793           *obufp++ = open_char;
11794           *obufp = '\0';
11795           oappend (index16[modrm.rm]);
11796           if (intel_syntax
11797               && (disp || modrm.mod != 0 || modrm.rm == 6))
11798             {
11799               if ((bfd_signed_vma) disp >= 0)
11800                 {
11801                   *obufp++ = '+';
11802                   *obufp = '\0';
11803                 }
11804               else if (modrm.mod != 1)
11805                 {
11806                   *obufp++ = '-';
11807                   *obufp = '\0';
11808                   disp = - (bfd_signed_vma) disp;
11809                 }
11810
11811               print_displacement (scratchbuf, disp);
11812               oappend (scratchbuf);
11813             }
11814
11815           *obufp++ = close_char;
11816           *obufp = '\0';
11817         }
11818       else if (intel_syntax)
11819         {
11820           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11821                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11822             ;
11823           else
11824             {
11825               oappend (names_seg[ds_reg - es_reg]);
11826               oappend (":");
11827             }
11828           print_operand_value (scratchbuf, 1, disp & 0xffff);
11829           oappend (scratchbuf);
11830         }
11831     }
11832 }
11833
11834 static void
11835 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11836 {
11837   /* Skip mod/rm byte.  */
11838   MODRM_CHECK;
11839   codep++;
11840
11841   if (modrm.mod == 3)
11842     OP_E_register (bytemode, sizeflag);
11843   else
11844     OP_E_memory (bytemode, sizeflag, has_drex);
11845 }
11846
11847 static void
11848 OP_E (int bytemode, int sizeflag)
11849 {
11850   OP_E_extended (bytemode, sizeflag, 0);
11851 }
11852
11853
11854 static void
11855 OP_G (int bytemode, int sizeflag)
11856 {
11857   int add = 0;
11858   USED_REX (REX_R);
11859   if (rex & REX_R)
11860     add += 8;
11861   switch (bytemode)
11862     {
11863     case b_mode:
11864       USED_REX (0);
11865       if (rex)
11866         oappend (names8rex[modrm.reg + add]);
11867       else
11868         oappend (names8[modrm.reg + add]);
11869       break;
11870     case w_mode:
11871       oappend (names16[modrm.reg + add]);
11872       break;
11873     case d_mode:
11874       oappend (names32[modrm.reg + add]);
11875       break;
11876     case q_mode:
11877       oappend (names64[modrm.reg + add]);
11878       break;
11879     case v_mode:
11880     case dq_mode:
11881     case dqb_mode:
11882     case dqd_mode:
11883     case dqw_mode:
11884       USED_REX (REX_W);
11885       if (rex & REX_W)
11886         oappend (names64[modrm.reg + add]);
11887       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11888         oappend (names32[modrm.reg + add]);
11889       else
11890         oappend (names16[modrm.reg + add]);
11891       used_prefixes |= (prefixes & PREFIX_DATA);
11892       break;
11893     case m_mode:
11894       if (address_mode == mode_64bit)
11895         oappend (names64[modrm.reg + add]);
11896       else
11897         oappend (names32[modrm.reg + add]);
11898       break;
11899     default:
11900       oappend (INTERNAL_DISASSEMBLER_ERROR);
11901       break;
11902     }
11903 }
11904
11905 static bfd_vma
11906 get64 (void)
11907 {
11908   bfd_vma x;
11909 #ifdef BFD64
11910   unsigned int a;
11911   unsigned int b;
11912
11913   FETCH_DATA (the_info, codep + 8);
11914   a = *codep++ & 0xff;
11915   a |= (*codep++ & 0xff) << 8;
11916   a |= (*codep++ & 0xff) << 16;
11917   a |= (*codep++ & 0xff) << 24;
11918   b = *codep++ & 0xff;
11919   b |= (*codep++ & 0xff) << 8;
11920   b |= (*codep++ & 0xff) << 16;
11921   b |= (*codep++ & 0xff) << 24;
11922   x = a + ((bfd_vma) b << 32);
11923 #else
11924   abort ();
11925   x = 0;
11926 #endif
11927   return x;
11928 }
11929
11930 static bfd_signed_vma
11931 get32 (void)
11932 {
11933   bfd_signed_vma x = 0;
11934
11935   FETCH_DATA (the_info, codep + 4);
11936   x = *codep++ & (bfd_signed_vma) 0xff;
11937   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11938   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11939   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11940   return x;
11941 }
11942
11943 static bfd_signed_vma
11944 get32s (void)
11945 {
11946   bfd_signed_vma x = 0;
11947
11948   FETCH_DATA (the_info, codep + 4);
11949   x = *codep++ & (bfd_signed_vma) 0xff;
11950   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11951   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11952   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11953
11954   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11955
11956   return x;
11957 }
11958
11959 static int
11960 get16 (void)
11961 {
11962   int x = 0;
11963
11964   FETCH_DATA (the_info, codep + 2);
11965   x = *codep++ & 0xff;
11966   x |= (*codep++ & 0xff) << 8;
11967   return x;
11968 }
11969
11970 static void
11971 set_op (bfd_vma op, int riprel)
11972 {
11973   op_index[op_ad] = op_ad;
11974   if (address_mode == mode_64bit)
11975     {
11976       op_address[op_ad] = op;
11977       op_riprel[op_ad] = riprel;
11978     }
11979   else
11980     {
11981       /* Mask to get a 32-bit address.  */
11982       op_address[op_ad] = op & 0xffffffff;
11983       op_riprel[op_ad] = riprel & 0xffffffff;
11984     }
11985 }
11986
11987 static void
11988 OP_REG (int code, int sizeflag)
11989 {
11990   const char *s;
11991   int add;
11992   USED_REX (REX_B);
11993   if (rex & REX_B)
11994     add = 8;
11995   else
11996     add = 0;
11997
11998   switch (code)
11999     {
12000     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12001     case sp_reg: case bp_reg: case si_reg: case di_reg:
12002       s = names16[code - ax_reg + add];
12003       break;
12004     case es_reg: case ss_reg: case cs_reg:
12005     case ds_reg: case fs_reg: case gs_reg:
12006       s = names_seg[code - es_reg + add];
12007       break;
12008     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12009     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12010       USED_REX (0);
12011       if (rex)
12012         s = names8rex[code - al_reg + add];
12013       else
12014         s = names8[code - al_reg];
12015       break;
12016     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12017     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12018       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12019         {
12020           s = names64[code - rAX_reg + add];
12021           break;
12022         }
12023       code += eAX_reg - rAX_reg;
12024       /* Fall through.  */
12025     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12026     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12027       USED_REX (REX_W);
12028       if (rex & REX_W)
12029         s = names64[code - eAX_reg + add];
12030       else if (sizeflag & DFLAG)
12031         s = names32[code - eAX_reg + add];
12032       else
12033         s = names16[code - eAX_reg + add];
12034       used_prefixes |= (prefixes & PREFIX_DATA);
12035       break;
12036     default:
12037       s = INTERNAL_DISASSEMBLER_ERROR;
12038       break;
12039     }
12040   oappend (s);
12041 }
12042
12043 static void
12044 OP_IMREG (int code, int sizeflag)
12045 {
12046   const char *s;
12047
12048   switch (code)
12049     {
12050     case indir_dx_reg:
12051       if (intel_syntax)
12052         s = "dx";
12053       else
12054         s = "(%dx)";
12055       break;
12056     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12057     case sp_reg: case bp_reg: case si_reg: case di_reg:
12058       s = names16[code - ax_reg];
12059       break;
12060     case es_reg: case ss_reg: case cs_reg:
12061     case ds_reg: case fs_reg: case gs_reg:
12062       s = names_seg[code - es_reg];
12063       break;
12064     case al_reg: case ah_reg: case cl_reg: case ch_reg:
12065     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12066       USED_REX (0);
12067       if (rex)
12068         s = names8rex[code - al_reg];
12069       else
12070         s = names8[code - al_reg];
12071       break;
12072     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12073     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12074       USED_REX (REX_W);
12075       if (rex & REX_W)
12076         s = names64[code - eAX_reg];
12077       else if (sizeflag & DFLAG)
12078         s = names32[code - eAX_reg];
12079       else
12080         s = names16[code - eAX_reg];
12081       used_prefixes |= (prefixes & PREFIX_DATA);
12082       break;
12083     case z_mode_ax_reg:
12084       if ((rex & REX_W) || (sizeflag & DFLAG))
12085         s = *names32;
12086       else
12087         s = *names16;
12088       if (!(rex & REX_W))
12089         used_prefixes |= (prefixes & PREFIX_DATA);
12090       break;
12091     default:
12092       s = INTERNAL_DISASSEMBLER_ERROR;
12093       break;
12094     }
12095   oappend (s);
12096 }
12097
12098 static void
12099 OP_I (int bytemode, int sizeflag)
12100 {
12101   bfd_signed_vma op;
12102   bfd_signed_vma mask = -1;
12103
12104   switch (bytemode)
12105     {
12106     case b_mode:
12107       FETCH_DATA (the_info, codep + 1);
12108       op = *codep++;
12109       mask = 0xff;
12110       break;
12111     case q_mode:
12112       if (address_mode == mode_64bit)
12113         {
12114           op = get32s ();
12115           break;
12116         }
12117       /* Fall through.  */
12118     case v_mode:
12119       USED_REX (REX_W);
12120       if (rex & REX_W)
12121         op = get32s ();
12122       else if (sizeflag & DFLAG)
12123         {
12124           op = get32 ();
12125           mask = 0xffffffff;
12126         }
12127       else
12128         {
12129           op = get16 ();
12130           mask = 0xfffff;
12131         }
12132       used_prefixes |= (prefixes & PREFIX_DATA);
12133       break;
12134     case w_mode:
12135       mask = 0xfffff;
12136       op = get16 ();
12137       break;
12138     case const_1_mode:
12139       if (intel_syntax)
12140         oappend ("1");
12141       return;
12142     default:
12143       oappend (INTERNAL_DISASSEMBLER_ERROR);
12144       return;
12145     }
12146
12147   op &= mask;
12148   scratchbuf[0] = '$';
12149   print_operand_value (scratchbuf + 1, 1, op);
12150   oappend (scratchbuf + intel_syntax);
12151   scratchbuf[0] = '\0';
12152 }
12153
12154 static void
12155 OP_I64 (int bytemode, int sizeflag)
12156 {
12157   bfd_signed_vma op;
12158   bfd_signed_vma mask = -1;
12159
12160   if (address_mode != mode_64bit)
12161     {
12162       OP_I (bytemode, sizeflag);
12163       return;
12164     }
12165
12166   switch (bytemode)
12167     {
12168     case b_mode:
12169       FETCH_DATA (the_info, codep + 1);
12170       op = *codep++;
12171       mask = 0xff;
12172       break;
12173     case v_mode:
12174       USED_REX (REX_W);
12175       if (rex & REX_W)
12176         op = get64 ();
12177       else if (sizeflag & DFLAG)
12178         {
12179           op = get32 ();
12180           mask = 0xffffffff;
12181         }
12182       else
12183         {
12184           op = get16 ();
12185           mask = 0xfffff;
12186         }
12187       used_prefixes |= (prefixes & PREFIX_DATA);
12188       break;
12189     case w_mode:
12190       mask = 0xfffff;
12191       op = get16 ();
12192       break;
12193     default:
12194       oappend (INTERNAL_DISASSEMBLER_ERROR);
12195       return;
12196     }
12197
12198   op &= mask;
12199   scratchbuf[0] = '$';
12200   print_operand_value (scratchbuf + 1, 1, op);
12201   oappend (scratchbuf + intel_syntax);
12202   scratchbuf[0] = '\0';
12203 }
12204
12205 static void
12206 OP_sI (int bytemode, int sizeflag)
12207 {
12208   bfd_signed_vma op;
12209   bfd_signed_vma mask = -1;
12210
12211   switch (bytemode)
12212     {
12213     case b_mode:
12214       FETCH_DATA (the_info, codep + 1);
12215       op = *codep++;
12216       if ((op & 0x80) != 0)
12217         op -= 0x100;
12218       mask = 0xffffffff;
12219       break;
12220     case v_mode:
12221       USED_REX (REX_W);
12222       if (rex & REX_W)
12223         op = get32s ();
12224       else if (sizeflag & DFLAG)
12225         {
12226           op = get32s ();
12227           mask = 0xffffffff;
12228         }
12229       else
12230         {
12231           mask = 0xffffffff;
12232           op = get16 ();
12233           if ((op & 0x8000) != 0)
12234             op -= 0x10000;
12235         }
12236       used_prefixes |= (prefixes & PREFIX_DATA);
12237       break;
12238     case w_mode:
12239       op = get16 ();
12240       mask = 0xffffffff;
12241       if ((op & 0x8000) != 0)
12242         op -= 0x10000;
12243       break;
12244     default:
12245       oappend (INTERNAL_DISASSEMBLER_ERROR);
12246       return;
12247     }
12248
12249   scratchbuf[0] = '$';
12250   print_operand_value (scratchbuf + 1, 1, op);
12251   oappend (scratchbuf + intel_syntax);
12252 }
12253
12254 static void
12255 OP_J (int bytemode, int sizeflag)
12256 {
12257   bfd_vma disp;
12258   bfd_vma mask = -1;
12259   bfd_vma segment = 0;
12260
12261   switch (bytemode)
12262     {
12263     case b_mode:
12264       FETCH_DATA (the_info, codep + 1);
12265       disp = *codep++;
12266       if ((disp & 0x80) != 0)
12267         disp -= 0x100;
12268       break;
12269     case v_mode:
12270       if ((sizeflag & DFLAG) || (rex & REX_W))
12271         disp = get32s ();
12272       else
12273         {
12274           disp = get16 ();
12275           if ((disp & 0x8000) != 0)
12276             disp -= 0x10000;
12277           /* In 16bit mode, address is wrapped around at 64k within
12278              the same segment.  Otherwise, a data16 prefix on a jump
12279              instruction means that the pc is masked to 16 bits after
12280              the displacement is added!  */
12281           mask = 0xffff;
12282           if ((prefixes & PREFIX_DATA) == 0)
12283             segment = ((start_pc + codep - start_codep)
12284                        & ~((bfd_vma) 0xffff));
12285         }
12286       used_prefixes |= (prefixes & PREFIX_DATA);
12287       break;
12288     default:
12289       oappend (INTERNAL_DISASSEMBLER_ERROR);
12290       return;
12291     }
12292   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12293   set_op (disp, 0);
12294   print_operand_value (scratchbuf, 1, disp);
12295   oappend (scratchbuf);
12296 }
12297
12298 static void
12299 OP_SEG (int bytemode, int sizeflag)
12300 {
12301   if (bytemode == w_mode)
12302     oappend (names_seg[modrm.reg]);
12303   else
12304     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12305 }
12306
12307 static void
12308 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12309 {
12310   int seg, offset;
12311
12312   if (sizeflag & DFLAG)
12313     {
12314       offset = get32 ();
12315       seg = get16 ();
12316     }
12317   else
12318     {
12319       offset = get16 ();
12320       seg = get16 ();
12321     }
12322   used_prefixes |= (prefixes & PREFIX_DATA);
12323   if (intel_syntax)
12324     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12325   else
12326     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12327   oappend (scratchbuf);
12328 }
12329
12330 static void
12331 OP_OFF (int bytemode, int sizeflag)
12332 {
12333   bfd_vma off;
12334
12335   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12336     intel_operand_size (bytemode, sizeflag);
12337   append_seg ();
12338
12339   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12340     off = get32 ();
12341   else
12342     off = get16 ();
12343
12344   if (intel_syntax)
12345     {
12346       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12347                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12348         {
12349           oappend (names_seg[ds_reg - es_reg]);
12350           oappend (":");
12351         }
12352     }
12353   print_operand_value (scratchbuf, 1, off);
12354   oappend (scratchbuf);
12355 }
12356
12357 static void
12358 OP_OFF64 (int bytemode, int sizeflag)
12359 {
12360   bfd_vma off;
12361
12362   if (address_mode != mode_64bit
12363       || (prefixes & PREFIX_ADDR))
12364     {
12365       OP_OFF (bytemode, sizeflag);
12366       return;
12367     }
12368
12369   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12370     intel_operand_size (bytemode, sizeflag);
12371   append_seg ();
12372
12373   off = get64 ();
12374
12375   if (intel_syntax)
12376     {
12377       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12378                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12379         {
12380           oappend (names_seg[ds_reg - es_reg]);
12381           oappend (":");
12382         }
12383     }
12384   print_operand_value (scratchbuf, 1, off);
12385   oappend (scratchbuf);
12386 }
12387
12388 static void
12389 ptr_reg (int code, int sizeflag)
12390 {
12391   const char *s;
12392
12393   *obufp++ = open_char;
12394   used_prefixes |= (prefixes & PREFIX_ADDR);
12395   if (address_mode == mode_64bit)
12396     {
12397       if (!(sizeflag & AFLAG))
12398         s = names32[code - eAX_reg];
12399       else
12400         s = names64[code - eAX_reg];
12401     }
12402   else if (sizeflag & AFLAG)
12403     s = names32[code - eAX_reg];
12404   else
12405     s = names16[code - eAX_reg];
12406   oappend (s);
12407   *obufp++ = close_char;
12408   *obufp = 0;
12409 }
12410
12411 static void
12412 OP_ESreg (int code, int sizeflag)
12413 {
12414   if (intel_syntax)
12415     {
12416       switch (codep[-1])
12417         {
12418         case 0x6d:      /* insw/insl */
12419           intel_operand_size (z_mode, sizeflag);
12420           break;
12421         case 0xa5:      /* movsw/movsl/movsq */
12422         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12423         case 0xab:      /* stosw/stosl */
12424         case 0xaf:      /* scasw/scasl */
12425           intel_operand_size (v_mode, sizeflag);
12426           break;
12427         default:
12428           intel_operand_size (b_mode, sizeflag);
12429         }
12430     }
12431   oappend ("%es:" + intel_syntax);
12432   ptr_reg (code, sizeflag);
12433 }
12434
12435 static void
12436 OP_DSreg (int code, int sizeflag)
12437 {
12438   if (intel_syntax)
12439     {
12440       switch (codep[-1])
12441         {
12442         case 0x6f:      /* outsw/outsl */
12443           intel_operand_size (z_mode, sizeflag);
12444           break;
12445         case 0xa5:      /* movsw/movsl/movsq */
12446         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12447         case 0xad:      /* lodsw/lodsl/lodsq */
12448           intel_operand_size (v_mode, sizeflag);
12449           break;
12450         default:
12451           intel_operand_size (b_mode, sizeflag);
12452         }
12453     }
12454   if ((prefixes
12455        & (PREFIX_CS
12456           | PREFIX_DS
12457           | PREFIX_SS
12458           | PREFIX_ES
12459           | PREFIX_FS
12460           | PREFIX_GS)) == 0)
12461     prefixes |= PREFIX_DS;
12462   append_seg ();
12463   ptr_reg (code, sizeflag);
12464 }
12465
12466 static void
12467 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12468 {
12469   int add;
12470   if (rex & REX_R)
12471     {
12472       USED_REX (REX_R);
12473       add = 8;
12474     }
12475   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12476     {
12477       lock_prefix = NULL;
12478       used_prefixes |= PREFIX_LOCK;
12479       add = 8;
12480     }
12481   else
12482     add = 0;
12483   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12484   oappend (scratchbuf + intel_syntax);
12485 }
12486
12487 static void
12488 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12489 {
12490   int add;
12491   USED_REX (REX_R);
12492   if (rex & REX_R)
12493     add = 8;
12494   else
12495     add = 0;
12496   if (intel_syntax)
12497     sprintf (scratchbuf, "db%d", modrm.reg + add);
12498   else
12499     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12500   oappend (scratchbuf);
12501 }
12502
12503 static void
12504 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12505 {
12506   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12507   oappend (scratchbuf + intel_syntax);
12508 }
12509
12510 static void
12511 OP_R (int bytemode, int sizeflag)
12512 {
12513   if (modrm.mod == 3)
12514     OP_E (bytemode, sizeflag);
12515   else
12516     BadOp ();
12517 }
12518
12519 static void
12520 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12521 {
12522   used_prefixes |= (prefixes & PREFIX_DATA);
12523   if (prefixes & PREFIX_DATA)
12524     {
12525       int add;
12526       USED_REX (REX_R);
12527       if (rex & REX_R)
12528         add = 8;
12529       else
12530         add = 0;
12531       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12532     }
12533   else
12534     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12535   oappend (scratchbuf + intel_syntax);
12536 }
12537
12538 static void
12539 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12540 {
12541   int add;
12542   USED_REX (REX_R);
12543   if (rex & REX_R)
12544     add = 8;
12545   else
12546     add = 0;
12547   if (need_vex && bytemode != xmm_mode)
12548     {
12549       switch (vex.length)
12550         {
12551         case 128:
12552           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12553           break;
12554         case 256:
12555           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12556           break;
12557         default:
12558           abort ();
12559         }
12560     }
12561   else
12562     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12563   oappend (scratchbuf + intel_syntax);
12564 }
12565
12566 static void
12567 OP_EM (int bytemode, int sizeflag)
12568 {
12569   if (modrm.mod != 3)
12570     {
12571       if (intel_syntax
12572           && (bytemode == v_mode || bytemode == v_swap_mode))
12573         {
12574           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12575           used_prefixes |= (prefixes & PREFIX_DATA);
12576         }
12577       OP_E (bytemode, sizeflag);
12578       return;
12579     }
12580
12581   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12582     swap_operand ();
12583
12584   /* Skip mod/rm byte.  */
12585   MODRM_CHECK;
12586   codep++;
12587   used_prefixes |= (prefixes & PREFIX_DATA);
12588   if (prefixes & PREFIX_DATA)
12589     {
12590       int add;
12591
12592       USED_REX (REX_B);
12593       if (rex & REX_B)
12594         add = 8;
12595       else
12596         add = 0;
12597       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12598     }
12599   else
12600     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12601   oappend (scratchbuf + intel_syntax);
12602 }
12603
12604 /* cvt* are the only instructions in sse2 which have
12605    both SSE and MMX operands and also have 0x66 prefix
12606    in their opcode. 0x66 was originally used to differentiate
12607    between SSE and MMX instruction(operands). So we have to handle the
12608    cvt* separately using OP_EMC and OP_MXC */
12609 static void
12610 OP_EMC (int bytemode, int sizeflag)
12611 {
12612   if (modrm.mod != 3)
12613     {
12614       if (intel_syntax && bytemode == v_mode)
12615         {
12616           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12617           used_prefixes |= (prefixes & PREFIX_DATA);
12618         }
12619       OP_E (bytemode, sizeflag);
12620       return;
12621     }
12622
12623   /* Skip mod/rm byte.  */
12624   MODRM_CHECK;
12625   codep++;
12626   used_prefixes |= (prefixes & PREFIX_DATA);
12627   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12628   oappend (scratchbuf + intel_syntax);
12629 }
12630
12631 static void
12632 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12633 {
12634   used_prefixes |= (prefixes & PREFIX_DATA);
12635   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12636   oappend (scratchbuf + intel_syntax);
12637 }
12638
12639 static void
12640 OP_EX (int bytemode, int sizeflag)
12641 {
12642   int add;
12643   if (modrm.mod != 3)
12644     {
12645       OP_E (bytemode, sizeflag);
12646       return;
12647     }
12648   USED_REX (REX_B);
12649   if (rex & REX_B)
12650     add = 8;
12651   else
12652     add = 0;
12653
12654   if ((sizeflag & SUFFIX_ALWAYS)
12655       && (bytemode == x_swap_mode || bytemode == q_swap_mode))
12656     swap_operand ();
12657
12658   /* Skip mod/rm byte.  */
12659   MODRM_CHECK;
12660   codep++;
12661   if (need_vex
12662       && bytemode != xmm_mode
12663       && bytemode != xmmq_mode)
12664     {
12665       switch (vex.length)
12666         {
12667         case 128:
12668           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12669           break;
12670         case 256:
12671           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12672           break;
12673         default:
12674           abort ();
12675         }
12676     }
12677   else
12678     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12679   oappend (scratchbuf + intel_syntax);
12680 }
12681
12682 static void
12683 OP_MS (int bytemode, int sizeflag)
12684 {
12685   if (modrm.mod == 3)
12686     OP_EM (bytemode, sizeflag);
12687   else
12688     BadOp ();
12689 }
12690
12691 static void
12692 OP_XS (int bytemode, int sizeflag)
12693 {
12694   if (modrm.mod == 3)
12695     OP_EX (bytemode, sizeflag);
12696   else
12697     BadOp ();
12698 }
12699
12700 static void
12701 OP_M (int bytemode, int sizeflag)
12702 {
12703   if (modrm.mod == 3)
12704     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12705     BadOp ();
12706   else
12707     OP_E (bytemode, sizeflag);
12708 }
12709
12710 static void
12711 OP_0f07 (int bytemode, int sizeflag)
12712 {
12713   if (modrm.mod != 3 || modrm.rm != 0)
12714     BadOp ();
12715   else
12716     OP_E (bytemode, sizeflag);
12717 }
12718
12719 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12720    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12721
12722 static void
12723 NOP_Fixup1 (int bytemode, int sizeflag)
12724 {
12725   if ((prefixes & PREFIX_DATA) != 0
12726       || (rex != 0
12727           && rex != 0x48
12728           && address_mode == mode_64bit))
12729     OP_REG (bytemode, sizeflag);
12730   else
12731     strcpy (obuf, "nop");
12732 }
12733
12734 static void
12735 NOP_Fixup2 (int bytemode, int sizeflag)
12736 {
12737   if ((prefixes & PREFIX_DATA) != 0
12738       || (rex != 0
12739           && rex != 0x48
12740           && address_mode == mode_64bit))
12741     OP_IMREG (bytemode, sizeflag);
12742 }
12743
12744 static const char *const Suffix3DNow[] = {
12745 /* 00 */        NULL,           NULL,           NULL,           NULL,
12746 /* 04 */        NULL,           NULL,           NULL,           NULL,
12747 /* 08 */        NULL,           NULL,           NULL,           NULL,
12748 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12749 /* 10 */        NULL,           NULL,           NULL,           NULL,
12750 /* 14 */        NULL,           NULL,           NULL,           NULL,
12751 /* 18 */        NULL,           NULL,           NULL,           NULL,
12752 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12753 /* 20 */        NULL,           NULL,           NULL,           NULL,
12754 /* 24 */        NULL,           NULL,           NULL,           NULL,
12755 /* 28 */        NULL,           NULL,           NULL,           NULL,
12756 /* 2C */        NULL,           NULL,           NULL,           NULL,
12757 /* 30 */        NULL,           NULL,           NULL,           NULL,
12758 /* 34 */        NULL,           NULL,           NULL,           NULL,
12759 /* 38 */        NULL,           NULL,           NULL,           NULL,
12760 /* 3C */        NULL,           NULL,           NULL,           NULL,
12761 /* 40 */        NULL,           NULL,           NULL,           NULL,
12762 /* 44 */        NULL,           NULL,           NULL,           NULL,
12763 /* 48 */        NULL,           NULL,           NULL,           NULL,
12764 /* 4C */        NULL,           NULL,           NULL,           NULL,
12765 /* 50 */        NULL,           NULL,           NULL,           NULL,
12766 /* 54 */        NULL,           NULL,           NULL,           NULL,
12767 /* 58 */        NULL,           NULL,           NULL,           NULL,
12768 /* 5C */        NULL,           NULL,           NULL,           NULL,
12769 /* 60 */        NULL,           NULL,           NULL,           NULL,
12770 /* 64 */        NULL,           NULL,           NULL,           NULL,
12771 /* 68 */        NULL,           NULL,           NULL,           NULL,
12772 /* 6C */        NULL,           NULL,           NULL,           NULL,
12773 /* 70 */        NULL,           NULL,           NULL,           NULL,
12774 /* 74 */        NULL,           NULL,           NULL,           NULL,
12775 /* 78 */        NULL,           NULL,           NULL,           NULL,
12776 /* 7C */        NULL,           NULL,           NULL,           NULL,
12777 /* 80 */        NULL,           NULL,           NULL,           NULL,
12778 /* 84 */        NULL,           NULL,           NULL,           NULL,
12779 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12780 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12781 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12782 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12783 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12784 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12785 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12786 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12787 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12788 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12789 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12790 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12791 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12792 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12793 /* C0 */        NULL,           NULL,           NULL,           NULL,
12794 /* C4 */        NULL,           NULL,           NULL,           NULL,
12795 /* C8 */        NULL,           NULL,           NULL,           NULL,
12796 /* CC */        NULL,           NULL,           NULL,           NULL,
12797 /* D0 */        NULL,           NULL,           NULL,           NULL,
12798 /* D4 */        NULL,           NULL,           NULL,           NULL,
12799 /* D8 */        NULL,           NULL,           NULL,           NULL,
12800 /* DC */        NULL,           NULL,           NULL,           NULL,
12801 /* E0 */        NULL,           NULL,           NULL,           NULL,
12802 /* E4 */        NULL,           NULL,           NULL,           NULL,
12803 /* E8 */        NULL,           NULL,           NULL,           NULL,
12804 /* EC */        NULL,           NULL,           NULL,           NULL,
12805 /* F0 */        NULL,           NULL,           NULL,           NULL,
12806 /* F4 */        NULL,           NULL,           NULL,           NULL,
12807 /* F8 */        NULL,           NULL,           NULL,           NULL,
12808 /* FC */        NULL,           NULL,           NULL,           NULL,
12809 };
12810
12811 static void
12812 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12813 {
12814   const char *mnemonic;
12815
12816   FETCH_DATA (the_info, codep + 1);
12817   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12818      place where an 8-bit immediate would normally go.  ie. the last
12819      byte of the instruction.  */
12820   obufp = mnemonicendp;
12821   mnemonic = Suffix3DNow[*codep++ & 0xff];
12822   if (mnemonic)
12823     oappend (mnemonic);
12824   else
12825     {
12826       /* Since a variable sized modrm/sib chunk is between the start
12827          of the opcode (0x0f0f) and the opcode suffix, we need to do
12828          all the modrm processing first, and don't know until now that
12829          we have a bad opcode.  This necessitates some cleaning up.  */
12830       op_out[0][0] = '\0';
12831       op_out[1][0] = '\0';
12832       BadOp ();
12833     }
12834   mnemonicendp = obufp;
12835 }
12836
12837 static struct op simd_cmp_op[] =
12838 {
12839   { STRING_COMMA_LEN ("eq") },
12840   { STRING_COMMA_LEN ("lt") },
12841   { STRING_COMMA_LEN ("le") },
12842   { STRING_COMMA_LEN ("unord") },
12843   { STRING_COMMA_LEN ("neq") },
12844   { STRING_COMMA_LEN ("nlt") },
12845   { STRING_COMMA_LEN ("nle") },
12846   { STRING_COMMA_LEN ("ord") }
12847 };
12848
12849 static void
12850 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12851 {
12852   unsigned int cmp_type;
12853
12854   FETCH_DATA (the_info, codep + 1);
12855   cmp_type = *codep++ & 0xff;
12856   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12857     {
12858       char suffix [3];
12859       char *p = mnemonicendp - 2;
12860       suffix[0] = p[0];
12861       suffix[1] = p[1];
12862       suffix[2] = '\0';
12863       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12864       mnemonicendp += simd_cmp_op[cmp_type].len;
12865     }
12866   else
12867     {
12868       /* We have a reserved extension byte.  Output it directly.  */
12869       scratchbuf[0] = '$';
12870       print_operand_value (scratchbuf + 1, 1, cmp_type);
12871       oappend (scratchbuf + intel_syntax);
12872       scratchbuf[0] = '\0';
12873     }
12874 }
12875
12876 static void
12877 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12878           int sizeflag ATTRIBUTE_UNUSED)
12879 {
12880   /* mwait %eax,%ecx  */
12881   if (!intel_syntax)
12882     {
12883       const char **names = (address_mode == mode_64bit
12884                             ? names64 : names32);
12885       strcpy (op_out[0], names[0]);
12886       strcpy (op_out[1], names[1]);
12887       two_source_ops = 1;
12888     }
12889   /* Skip mod/rm byte.  */
12890   MODRM_CHECK;
12891   codep++;
12892 }
12893
12894 static void
12895 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12896             int sizeflag ATTRIBUTE_UNUSED)
12897 {
12898   /* monitor %eax,%ecx,%edx"  */
12899   if (!intel_syntax)
12900     {
12901       const char **op1_names;
12902       const char **names = (address_mode == mode_64bit
12903                             ? names64 : names32);
12904
12905       if (!(prefixes & PREFIX_ADDR))
12906         op1_names = (address_mode == mode_16bit
12907                      ? names16 : names);
12908       else
12909         {
12910           /* Remove "addr16/addr32".  */
12911           addr_prefix = NULL;
12912           op1_names = (address_mode != mode_32bit
12913                        ? names32 : names16);
12914           used_prefixes |= PREFIX_ADDR;
12915         }
12916       strcpy (op_out[0], op1_names[0]);
12917       strcpy (op_out[1], names[1]);
12918       strcpy (op_out[2], names[2]);
12919       two_source_ops = 1;
12920     }
12921   /* Skip mod/rm byte.  */
12922   MODRM_CHECK;
12923   codep++;
12924 }
12925
12926 static void
12927 BadOp (void)
12928 {
12929   /* Throw away prefixes and 1st. opcode byte.  */
12930   codep = insn_codep + 1;
12931   oappend ("(bad)");
12932 }
12933
12934 static void
12935 REP_Fixup (int bytemode, int sizeflag)
12936 {
12937   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12938      lods and stos.  */
12939   if (prefixes & PREFIX_REPZ)
12940     repz_prefix = "rep ";
12941
12942   switch (bytemode)
12943     {
12944     case al_reg:
12945     case eAX_reg:
12946     case indir_dx_reg:
12947       OP_IMREG (bytemode, sizeflag);
12948       break;
12949     case eDI_reg:
12950       OP_ESreg (bytemode, sizeflag);
12951       break;
12952     case eSI_reg:
12953       OP_DSreg (bytemode, sizeflag);
12954       break;
12955     default:
12956       abort ();
12957       break;
12958     }
12959 }
12960
12961 static void
12962 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12963 {
12964   USED_REX (REX_W);
12965   if (rex & REX_W)
12966     {
12967       /* Change cmpxchg8b to cmpxchg16b.  */
12968       char *p = mnemonicendp - 2;
12969       mnemonicendp = stpcpy (p, "16b");
12970       bytemode = o_mode;
12971     }
12972   OP_M (bytemode, sizeflag);
12973 }
12974
12975 static void
12976 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12977 {
12978   if (need_vex)
12979     {
12980       switch (vex.length)
12981         {
12982         case 128:
12983           sprintf (scratchbuf, "%%xmm%d", reg);
12984           break;
12985         case 256:
12986           sprintf (scratchbuf, "%%ymm%d", reg);
12987           break;
12988         default:
12989           abort ();
12990         }
12991     }
12992   else
12993     sprintf (scratchbuf, "%%xmm%d", reg);
12994   oappend (scratchbuf + intel_syntax);
12995 }
12996
12997 static void
12998 CRC32_Fixup (int bytemode, int sizeflag)
12999 {
13000   /* Add proper suffix to "crc32".  */
13001   char *p = mnemonicendp;
13002
13003   switch (bytemode)
13004     {
13005     case b_mode:
13006       if (intel_syntax)
13007         goto skip;
13008
13009       *p++ = 'b';
13010       break;
13011     case v_mode:
13012       if (intel_syntax)
13013         goto skip;
13014
13015       USED_REX (REX_W);
13016       if (rex & REX_W)
13017         *p++ = 'q';
13018       else if (sizeflag & DFLAG)
13019         *p++ = 'l';
13020       else
13021         *p++ = 'w';
13022       used_prefixes |= (prefixes & PREFIX_DATA);
13023       break;
13024     default:
13025       oappend (INTERNAL_DISASSEMBLER_ERROR);
13026       break;
13027     }
13028   mnemonicendp = p;
13029   *p = '\0';
13030
13031 skip:
13032   if (modrm.mod == 3)
13033     {
13034       int add;
13035
13036       /* Skip mod/rm byte.  */
13037       MODRM_CHECK;
13038       codep++;
13039
13040       USED_REX (REX_B);
13041       add = (rex & REX_B) ? 8 : 0;
13042       if (bytemode == b_mode)
13043         {
13044           USED_REX (0);
13045           if (rex)
13046             oappend (names8rex[modrm.rm + add]);
13047           else
13048             oappend (names8[modrm.rm + add]);
13049         }
13050       else
13051         {
13052           USED_REX (REX_W);
13053           if (rex & REX_W)
13054             oappend (names64[modrm.rm + add]);
13055           else if ((prefixes & PREFIX_DATA))
13056             oappend (names16[modrm.rm + add]);
13057           else
13058             oappend (names32[modrm.rm + add]);
13059         }
13060     }
13061   else
13062     OP_E (bytemode, sizeflag);
13063 }
13064
13065 /* Print a DREX argument as either a register or memory operation.  */
13066 static void
13067 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
13068 {
13069   if (reg == DREX_REG_UNKNOWN)
13070     BadOp ();
13071
13072   else if (reg != DREX_REG_MEMORY)
13073     {
13074       sprintf (scratchbuf, "%%xmm%d", reg);
13075       oappend (scratchbuf + intel_syntax);
13076     }
13077
13078   else
13079     OP_E_extended (bytemode, sizeflag, 1);
13080 }
13081
13082 /* SSE5 instructions that have 4 arguments are encoded as:
13083    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
13084
13085    The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
13086    the DREX field (0x8) to determine how the arguments are laid out.
13087    The destination register must be the same register as one of the
13088    inputs, and it is encoded in the DREX byte.  No REX prefix is used
13089    for these instructions, since the DREX field contains the 3 extension
13090    bits provided by the REX prefix.
13091
13092    The bytemode argument adds 2 extra bits for passing extra information:
13093         DREX_OC1        -- Set the OC1 bit to indicate dest == 1st arg
13094         DREX_NO_OC0     -- OC0 in DREX is invalid
13095         (but pretend it is set).  */
13096
13097 static void
13098 OP_DREX4 (int flag_bytemode, int sizeflag)
13099 {
13100   unsigned int drex_byte;
13101   unsigned int regs[4];
13102   unsigned int modrm_regmem;
13103   unsigned int modrm_reg;
13104   unsigned int drex_reg;
13105   int bytemode;
13106   int rex_save = rex;
13107   int rex_used_save = rex_used;
13108   int has_sib = 0;
13109   int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
13110   int oc0;
13111   int i;
13112
13113   bytemode = flag_bytemode & ~ DREX_MASK;
13114
13115   for (i = 0; i < 4; i++)
13116     regs[i] = DREX_REG_UNKNOWN;
13117
13118   /* Determine if we have a SIB byte in addition to MODRM before the
13119      DREX byte.  */
13120   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13121       && (modrm.mod != 3)
13122       && (modrm.rm == 4))
13123     has_sib = 1;
13124
13125   /* Get the DREX byte.  */
13126   FETCH_DATA (the_info, codep + 2 + has_sib);
13127   drex_byte = codep[has_sib+1];
13128   drex_reg = DREX_XMM (drex_byte);
13129   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13130
13131   /* Is OC0 legal?  If not, hardwire oc0 == 1.  */
13132   if (flag_bytemode & DREX_NO_OC0)
13133     {
13134       oc0 = 1;
13135       if (DREX_OC0 (drex_byte))
13136         BadOp ();
13137     }
13138   else
13139     oc0 = DREX_OC0 (drex_byte);
13140
13141   if (modrm.mod == 3)
13142     {
13143       /* regmem == register  */
13144       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13145       rex = rex_used = 0;
13146       /* skip modrm/drex since we don't call OP_E_extended  */
13147       codep += 2;
13148     }
13149   else
13150     {
13151       /* regmem == memory, fill in appropriate REX bits  */
13152       modrm_regmem = DREX_REG_MEMORY;
13153       rex = drex_byte & (REX_B | REX_X | REX_R);
13154       if (rex)
13155         rex |= REX_OPCODE;
13156       rex_used = rex;
13157     }
13158
13159   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13160      order.  */
13161   switch (oc0 + oc1)
13162     {
13163     default:
13164       BadOp ();
13165       return;
13166
13167     case 0:
13168       regs[0] = modrm_regmem;
13169       regs[1] = modrm_reg;
13170       regs[2] = drex_reg;
13171       regs[3] = drex_reg;
13172       break;
13173
13174     case 1:
13175       regs[0] = modrm_reg;
13176       regs[1] = modrm_regmem;
13177       regs[2] = drex_reg;
13178       regs[3] = drex_reg;
13179       break;
13180
13181     case 2:
13182       regs[0] = drex_reg;
13183       regs[1] = modrm_regmem;
13184       regs[2] = modrm_reg;
13185       regs[3] = drex_reg;
13186       break;
13187
13188     case 3:
13189       regs[0] = drex_reg;
13190       regs[1] = modrm_reg;
13191       regs[2] = modrm_regmem;
13192       regs[3] = drex_reg;
13193       break;
13194     }
13195
13196   /* Print out the arguments.  */
13197   for (i = 0; i < 4; i++)
13198     {
13199       int j = (intel_syntax) ? 3 - i : i;
13200       if (i > 0)
13201         {
13202           *obufp++ = ',';
13203           *obufp = '\0';
13204         }
13205
13206       print_drex_arg (regs[j], bytemode, sizeflag);
13207     }
13208
13209   rex = rex_save;
13210   rex_used = rex_used_save;
13211 }
13212
13213 /* SSE5 instructions that have 3 arguments, and are encoded as:
13214    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>    (or)
13215    0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13216
13217    The DREX field has 1 bit (0x8) to determine how the arguments are
13218    laid out. The destination register is encoded in the DREX byte.
13219    No REX prefix is used for these instructions, since the DREX field
13220    contains the 3 extension bits provided by the REX prefix.  */
13221
13222 static void
13223 OP_DREX3 (int flag_bytemode, int sizeflag)
13224 {
13225   unsigned int drex_byte;
13226   unsigned int regs[3];
13227   unsigned int modrm_regmem;
13228   unsigned int modrm_reg;
13229   unsigned int drex_reg;
13230   int bytemode;
13231   int rex_save = rex;
13232   int rex_used_save = rex_used;
13233   int has_sib = 0;
13234   int oc0;
13235   int i;
13236
13237   bytemode = flag_bytemode & ~ DREX_MASK;
13238
13239   for (i = 0; i < 3; i++)
13240     regs[i] = DREX_REG_UNKNOWN;
13241
13242   /* Determine if we have a SIB byte in addition to MODRM before the
13243      DREX byte.  */
13244   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13245       && (modrm.mod != 3)
13246       && (modrm.rm == 4))
13247     has_sib = 1;
13248
13249   /* Get the DREX byte.  */
13250   FETCH_DATA (the_info, codep + 2 + has_sib);
13251   drex_byte = codep[has_sib+1];
13252   drex_reg = DREX_XMM (drex_byte);
13253   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13254
13255   /* Is OC0 legal?  If not, hardwire oc0 == 0 */
13256   oc0 = DREX_OC0 (drex_byte);
13257   if ((flag_bytemode & DREX_NO_OC0) && oc0)
13258     BadOp ();
13259
13260   if (modrm.mod == 3)
13261     {
13262       /* regmem == register */
13263       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13264       rex = rex_used = 0;
13265       /* skip modrm/drex since we don't call OP_E_extended.  */
13266       codep += 2;
13267     }
13268   else
13269     {
13270       /* regmem == memory, fill in appropriate REX bits.  */
13271       modrm_regmem = DREX_REG_MEMORY;
13272       rex = drex_byte & (REX_B | REX_X | REX_R);
13273       if (rex)
13274         rex |= REX_OPCODE;
13275       rex_used = rex;
13276     }
13277
13278   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13279      order.  */
13280   switch (oc0)
13281     {
13282     default:
13283       BadOp ();
13284       return;
13285
13286     case 0:
13287       regs[0] = modrm_regmem;
13288       regs[1] = modrm_reg;
13289       regs[2] = drex_reg;
13290       break;
13291
13292     case 1:
13293       regs[0] = modrm_reg;
13294       regs[1] = modrm_regmem;
13295       regs[2] = drex_reg;
13296       break;
13297     }
13298
13299   /* Print out the arguments.  */
13300   for (i = 0; i < 3; i++)
13301     {
13302       int j = (intel_syntax) ? 2 - i : i;
13303       if (i > 0)
13304         {
13305           *obufp++ = ',';
13306           *obufp = '\0';
13307         }
13308
13309       print_drex_arg (regs[j], bytemode, sizeflag);
13310     }
13311
13312   rex = rex_save;
13313   rex_used = rex_used_save;
13314 }
13315
13316 /* Emit a floating point comparison for comp<xx> instructions.  */
13317
13318 static void
13319 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13320               int sizeflag ATTRIBUTE_UNUSED)
13321 {
13322   unsigned char byte;
13323
13324   static const char *const cmp_test[] = {
13325     "eq",
13326     "lt",
13327     "le",
13328     "unord",
13329     "ne",
13330     "nlt",
13331     "nle",
13332     "ord",
13333     "ueq",
13334     "ult",
13335     "ule",
13336     "false",
13337     "une",
13338     "unlt",
13339     "unle",
13340     "true"
13341   };
13342
13343   FETCH_DATA (the_info, codep + 1);
13344   byte = *codep & 0xff;
13345
13346   if (byte >= ARRAY_SIZE (cmp_test)
13347       || obuf[0] != 'c'
13348       || obuf[1] != 'o'
13349       || obuf[2] != 'm')
13350     {
13351       /* The instruction isn't one we know about, so just append the
13352          extension byte as a numeric value.  */
13353       OP_I (b_mode, 0);
13354     }
13355
13356   else
13357     {
13358       sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13359       mnemonicendp = stpcpy (obuf, scratchbuf);
13360       codep++;
13361     }
13362 }
13363
13364 /* Emit an integer point comparison for pcom<xx> instructions,
13365    rewriting the instruction to have the test inside of it.  */
13366
13367 static void
13368 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13369               int sizeflag ATTRIBUTE_UNUSED)
13370 {
13371   unsigned char byte;
13372
13373   static const char *const cmp_test[] = {
13374     "lt",
13375     "le",
13376     "gt",
13377     "ge",
13378     "eq",
13379     "ne",
13380     "false",
13381     "true"
13382   };
13383
13384   FETCH_DATA (the_info, codep + 1);
13385   byte = *codep & 0xff;
13386
13387   if (byte >= ARRAY_SIZE (cmp_test)
13388       || obuf[0] != 'p'
13389       || obuf[1] != 'c'
13390       || obuf[2] != 'o'
13391       || obuf[3] != 'm')
13392     {
13393       /* The instruction isn't one we know about, so just print the
13394          comparison test byte as a numeric value.  */
13395       OP_I (b_mode, 0);
13396     }
13397
13398   else
13399     {
13400       sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13401       mnemonicendp = stpcpy (obuf, scratchbuf);
13402       codep++;
13403     }
13404 }
13405
13406 /* Display the destination register operand for instructions with
13407    VEX. */
13408
13409 static void
13410 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13411 {
13412   if (!need_vex)
13413     abort ();
13414
13415   if (!need_vex_reg)
13416     return;
13417
13418   switch (vex.length)
13419     {
13420     case 128:
13421       switch (bytemode)
13422         {
13423         case vex_mode:
13424         case vex128_mode:
13425           break;
13426         default:
13427           abort ();
13428           return;
13429         }
13430
13431       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13432       break;
13433     case 256:
13434       switch (bytemode)
13435         {
13436         case vex_mode:
13437         case vex256_mode:
13438           break;
13439         default:
13440           abort ();
13441           return;
13442         }
13443
13444       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13445       break;
13446     default:
13447       abort ();
13448       break;
13449     }
13450   oappend (scratchbuf + intel_syntax);
13451 }
13452
13453 /* Get the VEX immediate byte without moving codep.  */
13454
13455 static unsigned char
13456 get_vex_imm8 (int sizeflag)
13457 {
13458   int bytes_before_imm = 0;
13459
13460   /* Skip mod/rm byte.   */
13461   MODRM_CHECK;
13462   codep++;
13463
13464   if (modrm.mod != 3)
13465     {
13466       /* There are SIB/displacement bytes.  */
13467       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13468         {
13469           /* 32/64 bit address mode */
13470           int base = modrm.rm;
13471
13472           /* Check SIB byte.  */
13473           if (base == 4)
13474             {
13475               FETCH_DATA (the_info, codep + 1);
13476               base = *codep & 7;
13477               bytes_before_imm++;
13478             }
13479
13480           switch (modrm.mod)
13481             {
13482             case 0:
13483               /* When modrm.rm == 5 or modrm.rm == 4 and base in
13484                  SIB == 5, there is a 4 byte displacement.  */
13485               if (base != 5)
13486                 /* No displacement. */
13487                 break;
13488             case 2:
13489               /* 4 byte displacement.  */
13490               bytes_before_imm += 4;
13491               break;
13492             case 1:
13493               /* 1 byte displacement.  */
13494               bytes_before_imm++;
13495               break;
13496             }
13497         }
13498       else
13499         { /* 16 bit address mode */
13500           switch (modrm.mod)
13501             {
13502             case 0:
13503               /* When modrm.rm == 6, there is a 2 byte displacement.  */
13504               if (modrm.rm != 6)
13505                 /* No displacement. */
13506                 break;
13507             case 2:
13508               /* 2 byte displacement.  */
13509               bytes_before_imm += 2;
13510               break;
13511             case 1:
13512               /* 1 byte displacement.  */
13513               bytes_before_imm++;
13514               break;
13515             }
13516         }
13517     }
13518
13519   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13520   return codep [bytes_before_imm];
13521 }
13522
13523 static void
13524 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13525 {
13526   if (reg == -1 && modrm.mod != 3)
13527     {
13528       OP_E_memory (bytemode, sizeflag, 0);
13529       return;
13530     }
13531   else
13532     {
13533       if (reg == -1)
13534         {
13535           reg = modrm.rm;
13536           USED_REX (REX_B);
13537           if (rex & REX_B)
13538             reg += 8;
13539         }
13540       else if (reg > 7 && address_mode != mode_64bit)
13541         BadOp ();
13542     }
13543
13544   switch (vex.length)
13545     {
13546     case 128:
13547       sprintf (scratchbuf, "%%xmm%d", reg);
13548       break;
13549     case 256:
13550       sprintf (scratchbuf, "%%ymm%d", reg);
13551       break;
13552     default:
13553       abort ();
13554     }
13555   oappend (scratchbuf + intel_syntax);
13556 }
13557
13558 static void
13559 OP_EX_VexImmW (int bytemode, int sizeflag)
13560 {
13561   int reg = -1;
13562   static unsigned char vex_imm8;
13563
13564   if (!vex_w_done)
13565     {
13566       vex_imm8 = get_vex_imm8 (sizeflag);
13567       if (vex.w)
13568         reg = vex_imm8 >> 4;
13569       vex_w_done = 1;
13570     }
13571   else
13572     {
13573       if (!vex.w)
13574         reg = vex_imm8 >> 4;
13575     }
13576
13577   OP_EX_VexReg (bytemode, sizeflag, reg);
13578 }
13579
13580 static void
13581 OP_EX_VexW (int bytemode, int sizeflag)
13582 {
13583   int reg = -1;
13584
13585   if (!vex_w_done)
13586     {
13587       vex_w_done = 1;
13588       if (vex.w)
13589         reg = vex.register_specifier;
13590     }
13591   else
13592     {
13593       if (!vex.w)
13594         reg = vex.register_specifier;
13595     }
13596
13597   OP_EX_VexReg (bytemode, sizeflag, reg);
13598 }
13599
13600 static void
13601 OP_VEX_FMA (int bytemode, int sizeflag)
13602 {
13603   int reg = get_vex_imm8 (sizeflag) >> 4;
13604
13605   if (reg > 7 && address_mode != mode_64bit)
13606     BadOp ();
13607
13608   switch (vex.length)
13609     {
13610     case 128:
13611       switch (bytemode)
13612         {
13613         case vex_mode:
13614         case vex128_mode:
13615           break;
13616         default:
13617           abort ();
13618           return;
13619         }
13620
13621       sprintf (scratchbuf, "%%xmm%d", reg);
13622       break;
13623     case 256:
13624       switch (bytemode)
13625         {
13626         case vex_mode:
13627           break;
13628         default:
13629           abort ();
13630           return;
13631         }
13632
13633       sprintf (scratchbuf, "%%ymm%d", reg);
13634       break;
13635     default:
13636       abort ();
13637     }
13638   oappend (scratchbuf + intel_syntax);
13639 }
13640
13641 static void
13642 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13643              int sizeflag ATTRIBUTE_UNUSED)
13644 {
13645   /* Skip the immediate byte and check for invalid bits.  */
13646   FETCH_DATA (the_info, codep + 1);
13647   if (*codep++ & 0xf)
13648     BadOp ();
13649 }
13650
13651 static void
13652 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13653 {
13654   int reg;
13655   FETCH_DATA (the_info, codep + 1);
13656   reg = *codep++;
13657
13658   if (bytemode != x_mode)
13659     abort ();
13660
13661   if (reg & 0xf)
13662       BadOp ();
13663
13664   reg >>= 4;
13665   if (reg > 7 && address_mode != mode_64bit)
13666     BadOp ();
13667
13668   switch (vex.length)
13669     {
13670     case 128:
13671       sprintf (scratchbuf, "%%xmm%d", reg);
13672       break;
13673     case 256:
13674       sprintf (scratchbuf, "%%ymm%d", reg);
13675       break;
13676     default:
13677       abort ();
13678     }
13679   oappend (scratchbuf + intel_syntax);
13680 }
13681
13682 static void
13683 OP_XMM_VexW (int bytemode, int sizeflag)
13684 {
13685   /* Turn off the REX.W bit since it is used for swapping operands
13686      now.  */
13687   rex &= ~REX_W;
13688   OP_XMM (bytemode, sizeflag);
13689 }
13690
13691 static void
13692 OP_EX_Vex (int bytemode, int sizeflag)
13693 {
13694   if (modrm.mod != 3)
13695     {
13696       if (vex.register_specifier != 0)
13697         BadOp ();
13698       need_vex_reg = 0;
13699     }
13700   OP_EX (bytemode, sizeflag);
13701 }
13702
13703 static void
13704 OP_XMM_Vex (int bytemode, int sizeflag)
13705 {
13706   if (modrm.mod != 3)
13707     {
13708       if (vex.register_specifier != 0)
13709         BadOp ();
13710       need_vex_reg = 0;
13711     }
13712   OP_XMM (bytemode, sizeflag);
13713 }
13714
13715 static void
13716 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13717 {
13718   switch (vex.length)
13719     {
13720     case 128:
13721       mnemonicendp = stpcpy (obuf, "vzeroupper");
13722       break;
13723     case 256:
13724       mnemonicendp = stpcpy (obuf, "vzeroall");
13725       break;
13726     default:
13727       abort ();
13728     }
13729 }
13730
13731 static struct op vex_cmp_op[] =
13732 {
13733   { STRING_COMMA_LEN ("eq") },
13734   { STRING_COMMA_LEN ("lt") },
13735   { STRING_COMMA_LEN ("le") },
13736   { STRING_COMMA_LEN ("unord") },
13737   { STRING_COMMA_LEN ("neq") },
13738   { STRING_COMMA_LEN ("nlt") },
13739   { STRING_COMMA_LEN ("nle") },
13740   { STRING_COMMA_LEN ("ord") },
13741   { STRING_COMMA_LEN ("eq_uq") },
13742   { STRING_COMMA_LEN ("nge") },
13743   { STRING_COMMA_LEN ("ngt") },
13744   { STRING_COMMA_LEN ("false") },
13745   { STRING_COMMA_LEN ("neq_oq") },
13746   { STRING_COMMA_LEN ("ge") },
13747   { STRING_COMMA_LEN ("gt") },
13748   { STRING_COMMA_LEN ("true") },
13749   { STRING_COMMA_LEN ("eq_os") },
13750   { STRING_COMMA_LEN ("lt_oq") },
13751   { STRING_COMMA_LEN ("le_oq") },
13752   { STRING_COMMA_LEN ("unord_s") },
13753   { STRING_COMMA_LEN ("neq_us") },
13754   { STRING_COMMA_LEN ("nlt_uq") },
13755   { STRING_COMMA_LEN ("nle_uq") },
13756   { STRING_COMMA_LEN ("ord_s") },
13757   { STRING_COMMA_LEN ("eq_us") },
13758   { STRING_COMMA_LEN ("nge_uq") },
13759   { STRING_COMMA_LEN ("ngt_uq") },
13760   { STRING_COMMA_LEN ("false_os") },
13761   { STRING_COMMA_LEN ("neq_os") },
13762   { STRING_COMMA_LEN ("ge_oq") },
13763   { STRING_COMMA_LEN ("gt_oq") },
13764   { STRING_COMMA_LEN ("true_us") },
13765 };
13766
13767 static void
13768 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13769 {
13770   unsigned int cmp_type;
13771
13772   FETCH_DATA (the_info, codep + 1);
13773   cmp_type = *codep++ & 0xff;
13774   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13775     {
13776       char suffix [3];
13777       char *p = mnemonicendp - 2;
13778       suffix[0] = p[0];
13779       suffix[1] = p[1];
13780       suffix[2] = '\0';
13781       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13782       mnemonicendp += vex_cmp_op[cmp_type].len;
13783     }
13784   else
13785     {
13786       /* We have a reserved extension byte.  Output it directly.  */
13787       scratchbuf[0] = '$';
13788       print_operand_value (scratchbuf + 1, 1, cmp_type);
13789       oappend (scratchbuf + intel_syntax);
13790       scratchbuf[0] = '\0';
13791     }
13792 }
13793
13794 static const struct op pclmul_op[] =
13795 {
13796   { STRING_COMMA_LEN ("lql") },
13797   { STRING_COMMA_LEN ("hql") },
13798   { STRING_COMMA_LEN ("lqh") },
13799   { STRING_COMMA_LEN ("hqh") }
13800 };
13801
13802 static void
13803 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13804               int sizeflag ATTRIBUTE_UNUSED)
13805 {
13806   unsigned int pclmul_type;
13807
13808   FETCH_DATA (the_info, codep + 1);
13809   pclmul_type = *codep++ & 0xff;
13810   switch (pclmul_type)
13811     {
13812     case 0x10:
13813       pclmul_type = 2;
13814       break;
13815     case 0x11:
13816       pclmul_type = 3;
13817       break;
13818     default:
13819       break;
13820     }
13821   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13822     {
13823       char suffix [4];
13824       char *p = mnemonicendp - 3;
13825       suffix[0] = p[0];
13826       suffix[1] = p[1];
13827       suffix[2] = p[2];
13828       suffix[3] = '\0';
13829       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13830       mnemonicendp += pclmul_op[pclmul_type].len;
13831     }
13832   else
13833     {
13834       /* We have a reserved extension byte.  Output it directly.  */
13835       scratchbuf[0] = '$';
13836       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13837       oappend (scratchbuf + intel_syntax);
13838       scratchbuf[0] = '\0';
13839     }
13840 }
13841
13842 static const struct op vpermil2_op[] =
13843 {
13844   { STRING_COMMA_LEN ("td") },
13845   { STRING_COMMA_LEN ("td") },
13846   { STRING_COMMA_LEN ("mo") },
13847   { STRING_COMMA_LEN ("mz") }
13848 };
13849
13850 static void
13851 VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13852                 int sizeflag ATTRIBUTE_UNUSED)
13853 {
13854   unsigned int vpermil2_type;
13855
13856   FETCH_DATA (the_info, codep + 1);
13857   vpermil2_type = *codep++ & 0xf;
13858   if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13859     {
13860       char suffix [4];
13861       char *p = mnemonicendp - 3;
13862       suffix[0] = p[0];
13863       suffix[1] = p[1];
13864       suffix[2] = p[2];
13865       suffix[3] = '\0';
13866       sprintf (p, "%s%s", vpermil2_op[vpermil2_type].name, suffix);
13867       mnemonicendp += vpermil2_op[vpermil2_type].len;
13868     }
13869   else
13870     {
13871       /* We have a reserved extension byte.  Output it directly.  */
13872       scratchbuf[0] = '$';
13873       print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13874       oappend (scratchbuf + intel_syntax);
13875       scratchbuf[0] = '\0';
13876     }
13877 }
13878
13879 static void
13880 MOVBE_Fixup (int bytemode, int sizeflag)
13881 {
13882   /* Add proper suffix to "movbe".  */
13883   char *p = mnemonicendp;
13884
13885   switch (bytemode)
13886     {
13887     case v_mode:
13888       if (intel_syntax)
13889         goto skip;
13890
13891       USED_REX (REX_W);
13892       if (sizeflag & SUFFIX_ALWAYS)
13893         {
13894           if (rex & REX_W)
13895             *p++ = 'q';
13896           else if (sizeflag & DFLAG)
13897             *p++ = 'l';
13898           else
13899             *p++ = 'w';
13900         }
13901       used_prefixes |= (prefixes & PREFIX_DATA);
13902       break;
13903     default:
13904       oappend (INTERNAL_DISASSEMBLER_ERROR);
13905       break;
13906     }
13907   mnemonicendp = p;
13908   *p = '\0';
13909
13910 skip:
13911   OP_M (bytemode, sizeflag);
13912 }