1 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
2 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
3 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
4 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
5 Alan Modra <amodra@bigpond.net.au>
9 * configure.in: Add SPU support.
10 * disassemble.c: Likewise.
11 * Makefile.am: Likewise. Run "make dep-am".
12 * Makefile.in: Regenerate.
13 * configure: Regenerate.
14 * po/POTFILES.in: Regenerate.
16 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
18 * ppc-opc.c (CELL): New define.
19 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
20 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
22 * ppc-dis.c (powerpc_dialect): Handle cell.
24 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
26 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
27 amdfam10 architecture.
29 (print_insn): Disallow REP prefix for POPCNT.
31 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
33 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
36 2006-10-18 Dave Brolley <brolley@redhat.com>
38 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
39 * configure: Regenerated.
41 2006-09-29 Alan Modra <amodra@bigpond.net.au>
43 * po/POTFILES.in: Regenerate.
45 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
46 Joseph Myers <joseph@codesourcery.com>
47 Ian Lance Taylor <ian@wasabisystems.com>
48 Ben Elliston <bje@wasabisystems.com>
50 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
51 only be used with the default multiply-add operation, so if N is
52 set, don't bother printing X. Add new iwmmxt instructions.
53 (IWMMXT_INSN_COUNT): Update.
54 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
56 (print_insn_coprocessor): Check for iWMMXt2. Handle format
59 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
62 * i386-dis.c (prefix_user_table): Fix the second operand of
63 maskmovdqu instruction to allow only %xmm register instead of
64 both %xmm register and memory.
66 2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
69 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
72 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
74 * score-dis.c: New file.
75 * score-opc.h: New file.
76 * Makefile.am: Add Score files.
77 * Makefile.in: Regenerate.
78 * configure.in: Add support for Score target.
79 * configure: Regenerate.
80 * disassemble.c: Add support for Score target.
82 2006-09-16 Nick Clifton <nickc@redhat.com>
83 Pedro Alves <pedro_alves@portugalmail.pt>
85 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
86 macros defined in bfd.h.
87 * cris-dis.c: Likewise.
88 * h8300-dis.c: Likewise.
89 * i386-dis.c: Likewise.
90 * ia64-gen.c: Likewise.
93 2006-09-04 Paul Brook <paul@codesourcery.com>
95 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
97 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
99 * i386-dis.c (three_byte_table): Expand to 256 elements.
101 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
104 * i386-dis.c (MXC,EMC): Define.
105 (OP_MXC): New function to handle cvt* (convert instructions) between
106 %xmm and %mm register correctly.
108 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
109 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
112 2006-07-29 Richard Sandiford <richard@codesourcery.com>
114 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
117 2006-07-19 Paul Brook <paul@codesourcery.com>
119 * armd-dis.c (arm_opcodes): Fix rbit opcode.
121 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
123 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
124 "sldt", "str" and "smsw".
126 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
129 * i386-dis.c (GRP11_C6): NEW.
130 (GRP11_C7): Likewise.
137 (GRPPADLCK1): Likewise.
138 (GRPPADLCK2): Likewise.
139 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
141 (grps): Add entries for GRP11_C6 and GRP11_C7.
143 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
144 Michael Meissner <michael.meissner@amd.com>
146 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
147 support for amdfam10 SSE4a/ABM instructions. Modify all
148 initializer macros to have additional arguments. Disallow REP
149 prefix for non-string instructions.
152 2006-07-05 Julian Brown <julian@codesourcery.com>
154 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
156 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
158 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
159 (twobyte_has_modrm): Set 1 for 0x1f.
161 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
163 * i386-dis.c (NOP_Fixup): Removed.
165 (NOP_Fixup2): Likewise.
166 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
168 2006-06-12 Julian Brown <julian@codesourcery.com>
170 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
173 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
175 * i386.c (GRP10): Renamed to ...
177 (GRP11): Renamed to ...
179 (GRP12): Renamed to ...
181 (GRP13): Renamed to ...
183 (GRP14): Renamed to ...
185 (dis386_twobyte): Updated.
188 2006-06-09 Nick Clifton <nickc@redhat.com>
190 * po/fi.po: Updated Finnish translation.
192 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
194 * po/Make-in (pdf, ps): New dummy targets.
196 2006-06-06 Paul Brook <paul@codesourcery.com>
198 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
200 (neon_opcodes): Add conditional execution specifiers.
201 (thumb_opcodes): Ditto.
202 (thumb32_opcodes): Ditto.
203 (arm_conditional): Change 0xe to "al" and add "" to end.
204 (ifthen_state, ifthen_next_state, ifthen_address): New.
205 (IFTHEN_COND): Define.
206 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
207 (print_insn_arm): Change %c to use new values of arm_conditional.
208 (print_insn_thumb16): Print thumb conditions. Add %I.
209 (print_insn_thumb32): Print thumb conditions.
210 (find_ifthen_state): New function.
211 (print_insn): Track IT block state.
213 2006-06-06 Ben Elliston <bje@au.ibm.com>
214 Anton Blanchard <anton@samba.org>
215 Peter Bergner <bergner@vnet.ibm.com>
217 * ppc-dis.c (powerpc_dialect): Handle power6 option.
218 (print_ppc_disassembler_options): Mention power6.
220 2006-06-06 Thiemo Seufer <ths@mips.com>
221 Chao-ying Fu <fu@mips.com>
223 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
224 * mips-opc.c: Add DSP64 instructions.
226 2006-06-06 Alan Modra <amodra@bigpond.net.au>
228 * m68hc11-dis.c (print_insn): Warning fix.
230 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
232 * po/Make-in (top_builddir): Define.
234 2006-06-05 Alan Modra <amodra@bigpond.net.au>
236 * Makefile.am: Run "make dep-am".
237 * Makefile.in: Regenerate.
238 * config.in: Regenerate.
240 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
242 * Makefile.am (INCLUDES): Use @INCINTL@.
243 * acinclude.m4: Include new gettext macros.
244 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
245 Remove local code for po/Makefile.
246 * Makefile.in, aclocal.m4, configure: Regenerated.
248 2006-05-30 Nick Clifton <nickc@redhat.com>
250 * po/es.po: Updated Spanish translation.
252 2006-05-25 Richard Sandiford <richard@codesourcery.com>
254 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
255 and fmovem entries. Put register list entries before immediate
256 mask entries. Use "l" rather than "L" in the fmovem entries.
257 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
259 (m68k_scan_mask): New function, split out from...
260 (print_insn_m68k): ...here. If no architecture has been set,
261 first try printing an m680x0 instruction, then try a Coldfire one.
263 2006-05-24 Nick Clifton <nickc@redhat.com>
265 * po/ga.po: Updated Irish translation.
267 2006-05-22 Nick Clifton <nickc@redhat.com>
269 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
271 2006-05-22 Nick Clifton <nickc@redhat.com>
273 * po/nl.po: Updated translation.
275 2006-05-18 Alan Modra <amodra@bigpond.net.au>
277 * avr-dis.c: Formatting fix.
279 2006-05-14 Thiemo Seufer <ths@mips.com>
281 * mips16-opc.c (I1, I32, I64): New shortcut defines.
282 (mips16_opcodes): Change membership of instructions to their
285 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
287 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
289 2006-05-05 Julian Brown <julian@codesourcery.com>
291 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
294 2006-05-05 Thiemo Seufer <ths@mips.com>
295 David Ung <davidu@mips.com>
297 * mips-opc.c: Add macro for cache instruction.
299 2006-05-04 Thiemo Seufer <ths@mips.com>
300 Nigel Stephens <nigel@mips.com>
301 David Ung <davidu@mips.com>
303 * mips-dis.c (mips_arch_choices): Add smartmips instruction
304 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
305 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
307 * mips-opc.c: fix random typos in comments.
308 (INSN_SMARTMIPS): New defines.
309 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
310 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
311 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
312 FP_S and FP_D flags to denote single and double register
313 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
314 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
315 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
316 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
318 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
320 2006-05-03 Thiemo Seufer <ths@mips.com>
322 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
324 2006-05-02 Thiemo Seufer <ths@mips.com>
325 Nigel Stephens <nigel@mips.com>
326 David Ung <davidu@mips.com>
328 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
329 (print_mips16_insn_arg): Force mips16 to odd addresses.
331 2006-04-30 Thiemo Seufer <ths@mips.com>
332 David Ung <davidu@mips.com>
334 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
336 * mips-dis.c (print_insn_args): Adds udi argument handling.
338 2006-04-28 James E Wilson <wilson@specifix.com>
340 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
343 2006-04-28 Thiemo Seufer <ths@mips.com>
344 David Ung <davidu@mips.com>
345 Nigel Stephens <nigel@mips.com>
347 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
350 2006-04-28 Thiemo Seufer <ths@mips.com>
351 Nigel Stephens <nigel@mips.com>
352 David Ung <davidu@mips.com>
354 * mips-dis.c (print_insn_args): Add mips_opcode argument.
355 (print_insn_mips): Adjust print_insn_args call.
357 2006-04-28 Thiemo Seufer <ths@mips.com>
358 Nigel Stephens <nigel@mips.com>
360 * mips-dis.c (print_insn_args): Print $fcc only for FP
361 instructions, use $cc elsewise.
363 2006-04-28 Thiemo Seufer <ths@mips.com>
364 Nigel Stephens <nigel@mips.com>
366 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
367 Map MIPS16 registers to O32 names.
368 (print_mips16_insn_arg): Use mips16_reg_names.
370 2006-04-26 Julian Brown <julian@codesourcery.com>
372 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
375 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
376 Julian Brown <julian@codesourcery.com>
378 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
379 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
380 Add unified load/store instruction names.
381 (neon_opcode_table): New.
382 (arm_opcodes): Expand meaning of %<bitfield>['`?].
383 (arm_decode_bitfield): New.
384 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
385 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
386 (print_insn_neon): New.
387 (print_insn_arm): Adjust print_insn_coprocessor call. Call
388 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
389 (print_insn_thumb32): Likewise.
391 2006-04-19 Alan Modra <amodra@bigpond.net.au>
393 * Makefile.am: Run "make dep-am".
394 * Makefile.in: Regenerate.
396 2006-04-19 Alan Modra <amodra@bigpond.net.au>
398 * avr-dis.c (avr_operand): Warning fix.
400 * configure: Regenerate.
402 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
404 * po/POTFILES.in: Regenerated.
406 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
409 * avr-dis.c (avr_operand): Arrange for a comment to appear before
410 the symolic form of an address, so that the output of objdump -d
413 2006-04-10 DJ Delorie <dj@redhat.com>
415 * m32c-asm.c: Regenerate.
417 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
419 * Makefile.am: Add install-html target.
420 * Makefile.in: Regenerate.
422 2006-04-06 Nick Clifton <nickc@redhat.com>
424 * po/vi/po: Updated Vietnamese translation.
426 2006-03-31 Paul Koning <ni1d@arrl.net>
428 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
430 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
432 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
433 logic to identify halfword shifts.
435 2006-03-16 Paul Brook <paul@codesourcery.com>
437 * arm-dis.c (arm_opcodes): Rename swi to svc.
438 (thumb_opcodes): Ditto.
440 2006-03-13 DJ Delorie <dj@redhat.com>
442 * m32c-asm.c: Regenerate.
443 * m32c-desc.c: Likewise.
444 * m32c-desc.h: Likewise.
445 * m32c-dis.c: Likewise.
446 * m32c-ibld.c: Likewise.
447 * m32c-opc.c: Likewise.
448 * m32c-opc.h: Likewise.
450 2006-03-10 DJ Delorie <dj@redhat.com>
452 * m32c-desc.c: Regenerate with mul.l, mulu.l.
453 * m32c-opc.c: Likewise.
454 * m32c-opc.h: Likewise.
457 2006-03-09 Nick Clifton <nickc@redhat.com>
459 * po/sv.po: Updated Swedish translation.
461 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
464 * i386-dis.c (REP_Fixup): New function.
465 (AL): Remove duplicate.
470 (indirDXr): Likewise.
473 (dis386): Updated entries of ins, outs, movs, lods and stos.
475 2006-03-05 Nick Clifton <nickc@redhat.com>
477 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
478 signed 32-bit value into an unsigned 32-bit field when the host is
480 * fr30-ibld.c: Regenerate.
481 * frv-ibld.c: Regenerate.
482 * ip2k-ibld.c: Regenerate.
483 * iq2000-asm.c: Regenerate.
484 * iq2000-ibld.c: Regenerate.
485 * m32c-ibld.c: Regenerate.
486 * m32r-ibld.c: Regenerate.
487 * openrisc-ibld.c: Regenerate.
488 * xc16x-ibld.c: Regenerate.
489 * xstormy16-ibld.c: Regenerate.
491 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
493 * xc16x-asm.c: Regenerate.
494 * xc16x-dis.c: Regenerate.
496 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
498 * po/Make-in: Add html target.
500 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
502 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
503 Intel Merom New Instructions.
504 (THREE_BYTE_0): Likewise.
505 (THREE_BYTE_1): Likewise.
506 (three_byte_table): Likewise.
507 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
508 THREE_BYTE_1 for entry 0x3a.
509 (twobyte_has_modrm): Updated.
510 (twobyte_uses_SSE_prefix): Likewise.
511 (print_insn): Handle 3-byte opcodes used by Intel Merom New
514 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
516 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
517 (v9_hpriv_reg_names): New table.
518 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
519 New cases '$' and '%' for read/write hyperprivileged register.
520 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
521 window handling and rdhpr/wrhpr instructions.
523 2006-02-24 DJ Delorie <dj@redhat.com>
525 * m32c-desc.c: Regenerate with linker relaxation attributes.
526 * m32c-desc.h: Likewise.
527 * m32c-dis.c: Likewise.
528 * m32c-opc.c: Likewise.
530 2006-02-24 Paul Brook <paul@codesourcery.com>
532 * arm-dis.c (arm_opcodes): Add V7 instructions.
533 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
534 (print_arm_address): New function.
535 (print_insn_arm): Use it. Add 'P' and 'U' cases.
536 (psr_name): New function.
537 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
539 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
541 * ia64-opc-i.c (bXc): New.
543 (OpX2TaTbYaXcC): Likewise.
546 (ia64_opcodes_i): Add instructions for tf.
548 * ia64-opc.h (IMMU5b): New.
550 * ia64-asmtab.c: Regenerated.
552 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
554 * ia64-gen.c: Update copyright years.
555 * ia64-opc-b.c: Likewise.
557 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
559 * ia64-gen.c (lookup_regindex): Handle ".vm".
560 (print_dependency_table): Handle '\"'.
562 * ia64-ic.tbl: Updated from SDM 2.2.
563 * ia64-raw.tbl: Likewise.
564 * ia64-waw.tbl: Likewise.
565 * ia64-asmtab.c: Regenerated.
567 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
569 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
570 Anil Paranjape <anilp1@kpitcummins.com>
571 Shilin Shakti <shilins@kpitcummins.com>
573 * xc16x-desc.h: New file
574 * xc16x-desc.c: New file
575 * xc16x-opc.h: New file
576 * xc16x-opc.c: New file
577 * xc16x-ibld.c: New file
578 * xc16x-asm.c: New file
579 * xc16x-dis.c: New file
580 * Makefile.am: Entries for xc16x
581 * Makefile.in: Regenerate
582 * cofigure.in: Add xc16x target information.
583 * configure: Regenerate.
584 * disassemble.c: Add xc16x target information.
586 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
588 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
591 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
593 * i386-dis.c ('Z'): Add a new macro.
594 (dis386_twobyte): Use "movZ" for control register moves.
596 2006-02-10 Nick Clifton <nickc@redhat.com>
598 * iq2000-asm.c: Regenerate.
600 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
602 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
604 2006-01-26 David Ung <davidu@mips.com>
606 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
607 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
608 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
609 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
610 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
612 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
614 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
615 ld_d_r, pref_xd_cb): Use signed char to hold data to be
617 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
618 buffer overflows when disassembling instructions like
620 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
621 operand, if the offset is negative.
623 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
625 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
626 unsigned char to hold data to be disassembled.
628 2006-01-17 Andreas Schwab <schwab@suse.de>
631 * disassemble.c (disassemble_init_for_target): Set
632 disassembler_needs_relocs for bfd_arch_arm.
634 2006-01-16 Paul Brook <paul@codesourcery.com>
636 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
637 f?add?, and f?sub? instructions.
639 2006-01-16 Nick Clifton <nickc@redhat.com>
641 * po/zh_CN.po: New Chinese (simplified) translation.
642 * configure.in (ALL_LINGUAS): Add "zh_CH".
643 * configure: Regenerate.
645 2006-01-05 Paul Brook <paul@codesourcery.com>
647 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
649 2006-01-06 DJ Delorie <dj@redhat.com>
651 * m32c-desc.c: Regenerate.
652 * m32c-opc.c: Regenerate.
653 * m32c-opc.h: Regenerate.
655 2006-01-03 DJ Delorie <dj@redhat.com>
657 * cgen-ibld.in (extract_normal): Avoid memory range errors.
658 * m32c-ibld.c: Regenerated.
660 For older changes see ChangeLog-2005
666 version-control: never